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51. 发明申请

US20060065922A1 Semiconductor memory with vertical charge-trapping memory cells and fabrication 审中-公开
标题翻译：具有垂直电荷捕获存储单元和制造的半导体存储器
公开(公告)号：US20060065922A1
公开(公告)日：2006-03-30
申请号：US11272637
申请日：2005-11-14
申请人： Christoph Kleint , Joachim Deppe , Christoph Ludwig , Jens-Uwe Sachse
发明人： Christoph Kleint , Joachim Deppe , Christoph Ludwig , Jens-Uwe Sachse
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L29/40117 , H01L29/66833
摘要： A semiconductor device is formed by forming a plurality of trenches in a semiconductor body. The trenches alternate between active trenches and isolation trenches with the isolation trenches being deeper than the active trenches. The semiconductor body is doped so that a top surface of the semiconductor body adjacent each active trench and a floor of each active trench is doped. Memory cell components are formed in each active trench. The memory cell components include a gate electrode and a charge-trapping layer disposed between the gate electrode and a sidewall of the trench. The charge-trapping layer includes a memory layer disposed between first and second limiting layers. Bitlines are formed over the semiconductor body and electrically coupled doped regions adjacent to the top surface of the semiconductor body adjacent the active trenches. Bitline contacts are coupled to the bitlines.
摘要翻译：半导体器件通过在半导体本体中形成多个沟槽而形成。沟槽在有源沟槽和隔离沟槽之间交替，隔离沟槽比有源沟槽更深。半导体本体被掺杂，使得与每个有源沟槽相邻的半导体本体的顶表面和每个有源沟槽的底板被掺杂。在每个有源沟槽中形成存储单元元件。存储单元部件包括设置在栅电极和沟槽的侧壁之间的栅电极和电荷捕获层。电荷捕获层包括设置在第一和第二限制层之间的存储层。位线形成在半导体主体上并与邻近有源沟槽的半导体本体的顶表面相邻的电耦合掺杂区。位线触点耦合到位线。

52. 发明授权

US06992348B2 Semiconductor memory with vertical charge-trapping memory cells and fabrication 失效
标题翻译：具有垂直电荷捕获存储单元和制造的半导体存储器
公开(公告)号：US06992348B2
公开(公告)日：2006-01-31
申请号：US10741970
申请日：2003-12-19
申请人： Christoph Kleint , Joachim Deppe , Christoph Ludwig , Jens-Uwe Sachse
发明人： Christoph Kleint , Joachim Deppe , Christoph Ludwig , Jens-Uwe Sachse
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/105 , H01L27/115 , H01L29/66833
摘要： Outside a memory cell field, bit-line contacts are provided on the top bit lines and additional bit-line contacts are provided on the lower bit lines and are each connected in an electrically conductive way to a metallization layer provided for wiring. The bit-line contacts for the upper bit lines and the additional bit-line contacts for the lower bit lines are formed on opposite sides of the memory cell field and portions of the isolation trenches are present between the additional bit-line contacts.
摘要翻译：在存储单元场之外，在顶位线上提供位线触点，并且在下位线上提供额外的位线触点，并且各自以导电方式连接到为布线提供的金属化层。用于高位线的位线触点和用于低位线的附加位线触点形成在存储器单元场的相对侧上，并且隔离沟槽的部分存在于附加位线触点之间。

53. 发明申请

US20050286296A1 Semiconductor memory having charge trapping memory cells and fabrication method 有权
标题翻译：具有电荷捕获存储单元的半导体存储器和制造方法
公开(公告)号：US20050286296A1
公开(公告)日：2005-12-29
申请号：US11145541
申请日：2005-06-03
申请人： Michael Bollu , Armin Kohlhase , Christoph Ludwig , Herbert Palm , Josef Willer
发明人： Michael Bollu , Armin Kohlhase , Christoph Ludwig , Herbert Palm , Josef Willer
IPC分类号： H01L21/8246 , H01L27/115 , G11C11/34
CPC分类号： H01L27/11568 , H01L27/115
摘要： In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.
摘要翻译：在具有NROM单元的半导体存储器的情况下，存储晶体管的沟道区域在每种情况下相对于相关字线横向延伸，位线布置在字线的顶侧并且以电绝缘的方式并且存在导电交叉连接，这些交叉连接被布置在字线之间的间隔中并且以与后者的电绝缘的方式布置，并且在下一个序列中在每种情况下连接到位线。

54. 发明申请

US20050196923A1 SONOS memory cells and arrays and method of forming the same 有权
标题翻译： SONOS存储单元及阵列及其形成方法
公开(公告)号：US20050196923A1
公开(公告)日：2005-09-08
申请号：US11072695
申请日：2005-03-04
申请人： Joachim Deppe , Christoph Ludwig , Christoph Kleint , Josef Willer
发明人： Joachim Deppe , Christoph Ludwig , Christoph Kleint , Josef Willer
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8246 , H01L27/115 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A trench (2) is fabricated in a silicon body (1). The walls (4) of the trench are provided with a nitrogen implantation (6). An oxide layer between the source/drain regions (5) and a word line applied on the top side grows to a greater thickness than a lower oxide layer of an ONO storage layer fabricated as gate dielectric at the trench wall. Instead of the nitrogen implantation into the trench walls, it is possible to fabricate a metal silicide layer on the top sides of the source/drain regions in order to accelerate the oxide growth there.
摘要翻译：在硅体（1）中制造沟槽（2）。沟槽的壁（4）设置有氮注入（6）。源极/漏极区域（5）和施加在顶侧的字线之间的氧化物层比在沟槽壁上制作为栅极电介质的ONO存储层的低氧化物层增长更大的厚度。代替氮注入到沟槽壁中，可以在源极/漏极区的顶侧上制造金属硅化物层，以加速其中的氧化物生长。

55. 发明授权

US06917197B2 Device for adjusting an operating point of a magnetic field sensor 失效
标题翻译：用于调整磁场传感器的工作点的装置
公开(公告)号：US06917197B2
公开(公告)日：2005-07-12
申请号：US10487267
申请日：2002-08-07
申请人： Christoph Ludwig , Wolfgang Ludwig
发明人： Christoph Ludwig , Wolfgang Ludwig
IPC分类号： G01R33/035 , H01L39/22
CPC分类号： G01R33/0356
摘要： The invention relates to a device for setting an operating point of a magnetic field sensor having a periodic characteristic, in particular for a device for detecting a magnetic field and/or flux, having a SQUID as magnetic field sensor and a control unit which is connected downstream of the SQUID, has a control time constant (t) and has a feedback loop which acts on the SQUID and is designed such that it is active about a number of operating points of the SQUID, where flux quantum pump means are provided which are assigned to the SQUID, have a signal generation unit for generating a control and/or regulation signal for the SQUID and are designed such that, in order to pump at least one flux quantum into and out of the SQUID, a signal form of the control and/or regulation signal, generated by the signal generation unit, is different and, referred to a rising and a falling edge of a signal form, is unsymmetrical, where in each case only one of the edges of a signal form is short referred to the control time constant.
摘要翻译：本发明涉及一种用于设置具有周期性特性的磁场传感器的工作点的装置，特别是用于检测具有作为磁场传感器的SQUID和连接的控制单元的用于检测磁场和/或磁通的装置的装置 SQUID的下游具有控制时间常数（t）并且具有作用在SQUID上的反馈回路，并且被设计为使得其关于SQUID的多个工作点是活动的，其中提供了通量量子泵装置分配给SQUID的信号产生单元用于产生用于SQUID的控制和/或调节信号，并且被设计成使得为了将至少一个通量量子泵入和流出SQUID，控制信号形式和/或由信号产生单元生成的调节信号是不对称的，并且被称为信号形式的上升沿和下降沿是不对称的，其中在每种情况下，信号形式的边缘中只有一个是短的 d到控制时间常数。

56. 发明申请

US20050030780A1 Memory cell 有权
标题翻译：存储单元
公开(公告)号：US20050030780A1
公开(公告)日：2005-02-10
申请号：US10913707
申请日：2004-08-05
申请人： Joachim Deppe , Christoph Kleint , Christoph Ludwig
发明人： Joachim Deppe , Christoph Kleint , Christoph Ludwig
IPC分类号： H01L21/8247 , H01L21/28 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , G11C11/21
CPC分类号： H01L29/792 , H01L21/28282
摘要： In a memory cell, in a trench, a layer sequence comprising a first oxide layer, a nitride layer provided on the first oxide layer, and a second oxide layer, facing the gate electrode, and provided at the lateral trench walls, while the nitride layer is absent in a curved region of the trench bottom. In an alternative configuration, in each case at least one step is formed at the lateral walls of the trench, preferably below the source region or the drain region, respectively.
摘要翻译：在存储器单元中，在沟槽中，包括第一氧化物层，设置在第一氧化物层上的氮化物层和面向栅电极的第二氧化物层并且设置在侧向沟槽壁处的层序列，而氮化物在沟槽底部的弯曲区域中不存在层。在替代配置中，在每种情况下，在沟槽的侧壁上分别形成至少一个台阶，优选地分别在源区域或漏极区域下方形成。

57. 发明授权

US06628544B2 Flash memory cell and method to achieve multiple bits per cell 有权
标题翻译：闪存单元和方法来实现每个单元的多个位
公开(公告)号：US06628544B2
公开(公告)日：2003-09-30
申请号：US10057039
申请日：2002-01-25
申请人： Danny Shum , Georg Tempel , Christoph Ludwig
发明人： Danny Shum , Georg Tempel , Christoph Ludwig
IPC分类号： G11C1604
CPC分类号： G11C11/5642 , G11C5/145 , G11C11/5628 , G11C11/5635 , G11C16/0416 , G11C16/0433 , G11C2211/565
摘要： A method of flash memory cell programming is provided which uses a uniform electric potential across tunnel oxide. The tight Vt distribution and very stable Vt shift over program/erase cycling allows for a multi-level cell capable of having more than 2 bits per cell.
摘要翻译：提供了一种在隧道氧化物上使用均匀电势的闪存单元编程方法。紧密的Vt分布和非常稳定的Vt在编程/擦除循环中的移位允许一个能够在每个单元上具有超过2位的多级单元。

58. 外观设计

USD442873S1 Stand, especially for the mounting of a recording, detecting and controlling device 失效
标题翻译：特别适用于安装录音，检测和控制设备
公开(公告)号：USD442873S1
公开(公告)日：2001-05-29
申请号：US29124150
申请日：2000-05-31
申请人： Christoph Koennecke , Christoph Ludwig
设计人： Christoph Koennecke , Christoph Ludwig

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