专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US08039381B2 Photoresist etch back method for gate last process 有权
标题翻译：光栅蚀刻回路法最后一道工序
公开(公告)号：US08039381B2
公开(公告)日：2011-10-18
申请号：US12477618
申请日：2009-06-03
申请人： Chiung-Han Yeh , Chen-Pin Hsu , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang
发明人： Chiung-Han Yeh , Chen-Pin Hsu , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L29/42376 , H01L21/28079 , H01L21/28088 , H01L21/28105 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： A method is provided for fabricating a semiconductor device. The method includes providing a substrate including a dummy gate structure formed thereon, removing the dummy gate structure to form a trench, forming a first metal layer over the substrate to fill a portion of the trench, forming a protection layer in a remaining portion of the trench, removing a unprotected portion of the first metal layer, removing the protection layer from the trench, and forming a second metal layer over the substrate to fill the trench.
摘要翻译：提供了制造半导体器件的方法。该方法包括提供包括形成在其上的虚拟栅极结构的衬底，去除伪栅极结构以形成沟槽，在衬底上形成第一金属层以填充沟槽的一部分，在其中的一部分形成保护层去除所述第一金属层的未受保护部分，从所述沟槽移除所述保护层，以及在所述衬底上形成第二金属层以填充所述沟槽。

52. 发明申请

US20110233682A1 Reducing Device Performance Drift Caused by Large Spacings Between Active Regions 有权
标题翻译：降低活动区域之间大间距引起的设备性能漂移
公开(公告)号：US20110233682A1
公开(公告)日：2011-09-29
申请号：US13155251
申请日：2011-06-07
申请人： Harry Chuang , Kong-Beng Thei , Mong-Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Mong-Song Liang
IPC分类号： H01L27/088 , H01L27/092 , B82Y99/00
CPC分类号： H01L21/823475 , H01L21/31155 , H01L21/823412 , H01L21/823481 , H01L29/7846
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.
摘要翻译：形成集成电路结构的方法包括提供半导体衬底; 以及形成第一和第二MOS器件。第一MOS器件包括半导体衬底中的第一有源区; 和第一个主动区域的第一个门。第二MOS器件包括半导体衬底中的第二有源区; 以及在第二活动区域上的第二栅极。该方法还包括在第一和第二有源区之间形成电介质区域，其中电介质区域具有固有应力; 以及注入所述电介质区域以在所述电介质区域中形成应力释放区域，其中所述第一和第二MOS器件的源极和漏极区域在植入步骤期间不被植入。

53. 发明授权

US08017473B2 Modifying work function in PMOS devices by counter-doping 有权
标题翻译：通过反掺杂改进PMOS器件的功能
公开(公告)号：US08017473B2
公开(公告)日：2011-09-13
申请号：US12791656
申请日：2010-06-01
申请人： Chun-Yi Lee , Harry Chuang , Ping-Wei Wang , Kong-Beng Thei
发明人： Chun-Yi Lee , Harry Chuang , Ping-Wei Wang , Kong-Beng Thei
IPC分类号： H01L21/8238
CPC分类号： H01L27/0883 , G11C11/412 , H01L27/092 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/1083 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , Y10S438/919
摘要： A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.
摘要翻译：提供了包括SRAM /反相器单元的半导体结构及其形成方法，其中SRAM /反相器单元具有改善的写入裕度。 SRAM /反相器单元包括上拉PMOS器件，其包括半导体衬底上的栅极电介质，栅极电介质上的栅电极，其中栅电极包括p型杂质和n型杂质，以及形成在源极/漏极区域。上拉PMOS器件的器件驱动电流由于栅电极的反掺杂而降低。

54. 发明授权

US08008145B2 High-K metal gate structure fabrication method including hard mask 有权
标题翻译：高K金属栅极结构制造方法包括硬掩模
公开(公告)号：US08008145B2
公开(公告)日：2011-08-30
申请号：US12270466
申请日：2008-11-13
申请人： Shun-Jang Liao , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
发明人： Shun-Jang Liao , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L29/4966 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66628 , H01L29/7834 , H01L29/7848
摘要： Provided is a method of fabricating a semiconductor device including a high-k metal gate structure. A substrate is provided including a dummy gate structure (e.g., a sacrificial polysilicon gate), a first and second hard mask layer overlie the dummy gate structure. In one embodiment, a strained region is formed on the substrate. After forming the strained region, the second hard mask layer may be removed. A source/drain region may be formed. An ILD layer is then formed on the substrate. A CMP process may planarize the ILD layer using the first hard mask layer as a stop layer. The CMP process may be continued to remove the first hard mask layer. The dummy gate structure is then removed and a metal gate provided.
摘要翻译：提供一种制造包括高k金属栅极结构的半导体器件的方法。提供了包括伪栅极结构（例如，牺牲多晶硅栅极），覆盖在虚拟栅极结构上的第一和第二硬掩模层的衬底。在一个实施例中，在基底上形成应变区域。形成应变区后，可以除去第二硬掩模层。可以形成源极/漏极区域。然后在衬底上形成ILD层。 CMP工艺可以使用第一硬掩模层作为停止层来平坦化ILD层。 CMP工艺可以继续去除第一硬掩模层。然后去除虚拟栅极结构并提供金属栅极。

55. 发明授权

US07955964B2 Dishing-free gap-filling with multiple CMPs 有权
标题翻译：无间隙填充多个CMP
公开(公告)号：US07955964B2
公开(公告)日：2011-06-07
申请号：US12152380
申请日：2008-05-14
申请人： Ming-Yuan Wu , Kong-Beng Thei , Chiun-Han Yeh , Harry Chuang , Mong-Song Liang
发明人： Ming-Yuan Wu , Kong-Beng Thei , Chiun-Han Yeh , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/76883 , H01L21/76229
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.
摘要翻译：形成集成电路结构的方法包括提供半导体衬底; 在所述半导体衬底上形成图案化特征，其中在所述图案化特征之间形成间隙; 用第一填充材料填充间隙，其中第一填充材料具有高于图案化特征的顶表面的第一顶表面; 以及执行第一平面化以降低所述第一填充材料的顶表面，直到所述图案化特征的顶表面露出。该方法还包括沉积第二填充材料，其中第二填充材料具有高于图案化特征的顶表面的第二顶表面; 以及执行第二平面化以降低第二填充材料的顶表面，直到图案化特征的顶表面露出。

56. 发明授权

US07927943B2 Method for tuning a work function of high-k metal gate devices 有权
标题翻译：用于调谐高k金属栅极器件功能的方法
公开(公告)号：US07927943B2
公开(公告)日：2011-04-19
申请号：US12488960
申请日：2009-06-22
申请人： Chiung-Han Yeh , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
发明人： Chiung-Han Yeh , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/517 , H01L29/66545
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming first and second transistors in the substrate, the first transistor having a first gate structure that includes a first dummy gate, the second transistor having a second gate structure that includes a second dummy gate, removing the first and second dummy gates thereby forming a first trench and a second trench, respectively, forming a first metal layer to partially fill in the first and second trenches, removing the first metal layer within the first trench, forming a second metal layer to partially fill in the first and second trenches, forming a third metal layer to partially fill in the first and second trenches, reflowing the second metal layer and the third metal layer, and forming a fourth metal layer to fill in the remainder of the first and second trenches.
摘要翻译：本公开提供一种制造半导体器件的方法，该半导体器件包括提供半导体衬底，在衬底中形成第一和第二晶体管，第一晶体管具有包括第一虚拟栅极的第一栅极结构，第二晶体管具有第二栅极结构包括第二伪栅极，去除第一和第二伪栅极，从而分别形成第一沟槽和第二沟槽，形成第一金属层以部分地填充在第一和第二沟槽中，去除第一沟槽内的第一金属层形成第二金属层以部分地填充在第一和第二沟槽中，形成第三金属层以部分地填充在第一和第二沟槽中，回流第二金属层和第三金属层，以及形成第四金属层以填充在第一和第二个沟槽的剩余部分。

57. 发明申请

US20110076813A1 Semiconductor Device with both I/O and Core Components and Method of Fabricating Same 有权
标题翻译：具有I / O和核心组件的半导体器件及其制造方法
公开(公告)号：US20110076813A1
公开(公告)日：2011-03-31
申请号：US12961167
申请日：2010-12-06
申请人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong Song Liang
发明人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong Song Liang
IPC分类号： H01L21/8238
CPC分类号： H01L29/66477 , H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L27/0629 , H01L27/088 , H01L27/0922 , H01L29/7848
摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
摘要翻译：具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。可以在与芯井相邻的隔离结构上形成电阻器。在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。在一些实施例中，产生p型I / O阱和n型I / O阱。在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

58. 发明申请

US20100311231A1 METHOD FOR A GATE LAST PROCESS 有权
标题翻译：门过程的方法
公开(公告)号：US20100311231A1
公开(公告)日：2010-12-09
申请号：US12478358
申请日：2009-06-04
申请人： Kong-Beng Thei , Harry Chuang , Su-Chen Lai , Gary Shen
发明人： Kong-Beng Thei , Harry Chuang , Su-Chen Lai , Gary Shen
IPC分类号： H01L21/336 , H01L21/306 , H01L21/8234
CPC分类号： H01L29/7833 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66583
摘要： A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming one or more gate structures over the substrate; forming a buffer layer over the substrate, including over the one or more gate structures; forming an etch stop layer over the buffer layer; forming a interlevel dielectric (ILD) layer over the etch stop layer; and removing a portion of the buffer layer, a portion of the etch stop layer, and a portion of the ILD layer over the one or more gate structures.
摘要翻译：公开了一种制造半导体器件的方法。该方法包括提供基板; 在所述衬底上形成一个或多个栅极结构; 在衬底上形成缓冲层，包括在一个或多个栅极结构上; 在缓冲层上形成蚀刻停止层; 在所述蚀刻停止层上形成层间电介质（ILD）层; 以及去除所述缓冲层的一部分，所述蚀刻停止层的一部分以及所述一个或多个栅极结构上的所述ILD层的一部分。

59. 发明申请

US20100155783A1 Standard Cell Architecture and Methods with Variable Design Rules 有权
标题翻译：具有可变设计规则的标准单元架构和方法
公开(公告)号：US20100155783A1
公开(公告)日：2010-06-24
申请号：US12338632
申请日：2008-12-18
申请人： Oscar M.K. Law , Manoj Achyutrao Joshi , Kong-Beng Thei , Harry Chuang
发明人： Oscar M.K. Law , Manoj Achyutrao Joshi , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L25/07 , H01L21/8232
CPC分类号： H01L27/11807 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a conductive layer having at least two portions spaced apart by a minimum spacing distance, the conductive layer having at least one portion spaced from a cell boundary by a first spacing distance of less than half of the minimum spacing distance; a second standard cell disposed adjacent the first standard cell with at least one second portion of the conductive layer in the second cell disposed adjacent the first portion in the first standard cell and spaced apart from a common cell boundary by a second spacing greater than half of the minimum; wherein the sum of the first and second spacings is at least as great as the minimum spacing. A method for forming standard is disclosed.
摘要翻译：公开了具有层与单元边界间隔的可变规则的标准单元布局的结构和方法。在一个实施例中，第一标准单元布局设置有导电层，其具有间隔最小间隔距离的至少两个部分，所述导电层具有至少一个与单元边界隔开的部分，第一间隔距离小于一半的最小间距; 与所述第一标准单元相邻设置的第二标准单元，所述第二单元中的所述导电层的至少一个第二部分与所述第一标准单元中的所述第一部分相邻设置并且与所述第一标准单元间隔开第二间隔，最小其中所述第一和第二间距的总和至少与所述最小间隔一样大。公开了一种形成标准的方法。

60. 发明申请

US20100059823A1 RESISTIVE DEVICE FOR HIGH-K METAL GATE TECHNOLOGY AND METHOD OF MAKING 审中-公开
标题翻译：用于高K金属门技术的电阻装置及其制造方法
公开(公告)号：US20100059823A1
公开(公告)日：2010-03-11
申请号：US12432926
申请日：2009-04-30
申请人： Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
发明人： Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L23/525 , H01L27/10 , H01L27/092
CPC分类号： H01L23/5256 , H01L21/823878 , H01L27/0629 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device is provided which includes a semiconductor substrate, an isolation structure formed in the substrate for isolating an active region of the substrate, the isolation structure being formed of a first material, an active device formed in the active region of the substrate, the active device having a high-k dielectric and metal gate, and a passive device formed in the isolation structure, the passive device being formed of a second material different from the first material and having a predefined resistivity.
摘要翻译：提供了一种半导体器件，其包括半导体衬底，形成在衬底中用于隔离衬底的有源区的隔离结构，隔离结构由第一材料形成，有源器件形成在衬底的有源区中，具有高k电介质和金属栅极的有源器件和形成在隔离结构中的无源器件，无源器件由不同于第一材料并具有预定电阻率的第二材料形成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式