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51. 发明授权

US08309398B2 Electronic device wafer level scale packages and fabrication methods thereof 有权
标题翻译：电子装置晶圆级规包装及其制造方法
公开(公告)号：US08309398B2
公开(公告)日：2012-11-13
申请号：US13152891
申请日：2011-06-03
申请人： Chien-Hung Liu , Sih-Dian Lee
发明人： Chien-Hung Liu , Sih-Dian Lee
IPC分类号： H01L21/00 , H01L21/78
CPC分类号： H01L31/0203 , H01L23/3114 , H01L24/05 , H01L24/13 , H01L24/97 , H01L27/14618 , H01L27/14687 , H01L29/0657 , H01L2224/0401 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/014 , H01L2924/12043 , H01L2924/14 , H01L2924/00
摘要： Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A first trench is formed by etching the semiconductor exposing an inter-layered dielectric layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the first trench is removed to create a second trench. The insulating layer and the ILD layer are sequentially removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an S-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed.
摘要翻译：电子装置晶圆级规包装及其制造方法。提供了形成有多个电子器件的半导体晶片。半导体晶片与支撑基板结合。半导体衬底的背面变薄。通过蚀刻暴露层间电介质层的半导体形成第一沟槽。绝缘层顺应地沉积在半导体衬底的背面上。去除第一沟槽底部的绝缘层以产生第二沟槽。依次去除绝缘层和ILD层，暴露一对接触焊盘的一部分。导电层顺应地形成在半导体的背面上。导电层被图案化之后，导电层和接触垫构成S形连接。接下来，随后形成外部连接和端子接触焊盘。

52. 发明申请

US20110248310A1 CHIP PACKAGE AND METHOD FOR FORMING THE SAME 有权
标题翻译：芯片包装及其形成方法
公开(公告)号：US20110248310A1
公开(公告)日：2011-10-13
申请号：US13081346
申请日：2011-04-06
申请人： Chia-Ming CHENG , Chien-Hung Liu
发明人： Chia-Ming CHENG , Chien-Hung Liu
IPC分类号： H01L33/62 , H01L21/78 , H01L29/78
CPC分类号： H01L23/49805 , H01L21/76898 , H01L23/13 , H01L23/481 , H01L23/50 , H01L24/03 , H01L24/05 , H01L24/16 , H01L2224/02371 , H01L2224/02372 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2924/0002 , H01L2924/01021 , H01L2924/12041 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/3025 , H01L2924/00 , H01L2224/05552
摘要： An embodiment of the invention provides a chip package which includes a substrate having an upper surface and a lower surface and having at least a side surface, and at least a trench extending from the upper surface towards the lower surface and extending from the side surface towards an inner portion of the substrate, wherein a width of the trench near the upper surface is not equal to a width of the trench near the lower surface, and at least an insulating layer located on a sidewall of the trench, and at least a conducting pattern located on the insulating layer, wherein the side surface is separated from the conducting pattern in the trench by a predetermined distance such that a portion of the insulating layer is exposed, and at least a conducting region electrically connected to the conducting pattern.
摘要翻译：本发明的一个实施例提供了一种芯片封装，其包括具有上表面和下表面的基板，并且至少具有一个侧表面，以及至少一个从上表面向下表面延伸并且从侧表面向着衬底的内部部分，其中靠近上表面的沟槽的宽度不等于下表面附近的沟槽的宽度，以及至少位于沟槽的侧壁上的绝缘层，并且至少导电位于所述绝缘层上，其中所述侧表面与所述沟槽中的导电图案分离预定距离，使得所述绝缘层的一部分露出，以及至少导电区域电连接到所述导电图案。

53. 发明授权

US07773234B2 Means for measuring a working machine's structural deviation from five reference axes 有权
标题翻译：用于测量工作机械与五个参考轴的结构偏差的手段
公开(公告)号：US07773234B2
公开(公告)日：2010-08-10
申请号：US12206026
申请日：2008-09-08
申请人： Wen-Yuh Jywe , Chien-Hung Liu , Yi-Tsung Li , Tung-Hsien Hsieh , Tung-Hui Hsu , Hung-Shu Wang
发明人： Wen-Yuh Jywe , Chien-Hung Liu , Yi-Tsung Li , Tung-Hsien Hsieh , Tung-Hui Hsu , Hung-Shu Wang
IPC分类号： G01B11/14
CPC分类号： G01B11/272 , B23Q17/24 , B23Q2230/002
摘要： Means for measuring a working machine's structural deviation from five reference axes includes a main sensing body bonded with a main axis of the working machine (or controlled to revolve), and a lighting unit set around the main sensing body to circle about the main sensing body with a fixed radius (or the lighting unit radiates a light on the main sensing body from that radial distance and circles along with the main sensing body) such that as soon as the main sensing body has detected an optical signal, it is converted to an error signal informing of the working machine's structural deviation in two or three dimensional displacement.
摘要翻译：用于测量工作机械与五个参考轴的结构偏差的装置包括与工作机的主轴（或控制旋转）结合的主感测体，以及围绕主感测体围绕主感测体环绕的照明单元具有固定半径（或者照明单元从该径向距离辐射主感测体上的光并与主感测体一起旋转），使得一旦主感测体检测到光信号，就将其转换为误差信号通知工作机械在二维或三维位移中的结构偏差。

54. 发明授权

US07636170B1 Static/dynamic multi-function measuring device for linear unit 失效
标题翻译：用于线性单元的静态/动态多功能测量装置
公开(公告)号：US07636170B1
公开(公告)日：2009-12-22
申请号：US12209251
申请日：2008-09-12
申请人： Wen-Yuh Jywe , Chien-Hung Liu , Tung-Hsien Hsieh , Yun-Feng Teng
发明人： Wen-Yuh Jywe , Chien-Hung Liu , Tung-Hsien Hsieh , Yun-Feng Teng
IPC分类号： G01B11/14 , G01B11/26 , G01C1/00 , G01B11/02 , G01N21/86 , B23Q1/62 , G01B5/004 , G01B5/00
CPC分类号： G01B5/0004
摘要： A static/dynamic multi-function measuring device for linear unit, includes a foundation, a multi-direction sliding unit having eddy current detector, a linear motor, a linear unit with a sensing element and an optical measuring unit; the static/dynamic multi-function measuring device uses the linear motor to drive the multi-direction sliding unit with low friction to provide a non-contact measurement of a parallel alignment of the linear unit, a linear accuracy measurement of the linear unit, and a vibration measurement of the linear unit to detect the parallel alignment of the linear unit and the linear accuracy of a slide rail and so on, the static/dynamic multi-function measuring device also measures errors of the linear unit and a slide block moving in the vibrating and the rolling direction.
摘要翻译：一种用于线性单元的静态/动态多功能测量装置，包括基座，具有涡流检测器的多向滑动单元，线性电动机，具有感测元件的线性单元和光学测量单元; 静态/动态多功能测量装置使用线性电动机以低摩擦力驱动多向滑动单元，以提供线性单元的平行对准的非接触测量，线性单元的线性精度测量和用于检测线性单元的平行排列和滑轨的线性精度的线性单元的振动测量等，静态/动态多功能测量装置还测量线性单元和滑块移动的误差振动和滚动方向。

55. 发明申请

US20090050995A1 Electronic device wafer level scale packges and fabrication methods thereof 审中-公开
标题翻译：电子器件晶圆级封装及其制造方法
公开(公告)号：US20090050995A1
公开(公告)日：2009-02-26
申请号：US11987227
申请日：2007-11-28
申请人： Chien-Hung Liu , Sih-Dian Lee
发明人： Chien-Hung Liu , Sih-Dian Lee
IPC分类号： H01L31/0203 , H01L23/15 , H01L31/18 , H01L21/58
CPC分类号： H01L31/0203 , H01L23/3114 , H01L24/13 , H01L24/97 , H01L27/14618 , H01L27/14687 , H01L29/0657 , H01L2224/05001 , H01L2224/05548 , H01L2924/01005 , H01L2924/01006 , H01L2924/12043 , H01L2924/14 , H01L2924/00
摘要： Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A trench is formed by etching the semiconductor exposing an inter-layered dielectric (ILD) layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the trench is removed, and the ILD layer is subsequently removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an L-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed.
摘要翻译：电子装置晶圆级规包装及其制造方法。提供了形成有多个电子器件的半导体晶片。半导体晶片与支撑基板结合。半导体衬底的背面变薄。通过蚀刻暴露层间电介质（ILD）层的半导体形成沟槽。绝缘层顺应地沉积在半导体衬底的背面上。去除沟槽底部的绝缘层，随后去除暴露部分一对接触垫的ILD层。导电层顺应地形成在半导体的背面上。在导电层被图案化之后，导电层和接触垫构成L形连接。接下来，随后形成外部连接和端子接触焊盘。

56. 发明申请

US20080191343A1 Integrated circuit package having large conductive area and method for fabricating the same 审中-公开
标题翻译：具有大导电面积的集成电路封装及其制造方法
公开(公告)号：US20080191343A1
公开(公告)日：2008-08-14
申请号：US11798159
申请日：2007-05-10
申请人： Chien-Hung Liu
发明人： Chien-Hung Liu
IPC分类号： H01L23/48 , H01L21/98
CPC分类号： H01L27/14687 , H01L27/14618 , H01L2224/05001 , H01L2224/05008 , H01L2224/05548 , H01L2224/05569 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/10 , H01L2924/00014 , H01L2224/05099
摘要： An integrated circuit package having large conductive area and method for fabricating the same is provided. The package includes an integrated circuit chip having upper and lower surfaces and a photosensitive device formed on the upper surface. A bonding pad is subsequently formed on the upper surface of the integrated circuit chip and electrically connected to the photosensitive device. A conductive layer is then formed on a sidewall of the integrated circuit chip and wrapped around an edge of the bonding pad to electrically connect to the bonding pad. In the package, the conductive layer is in contact with the upper and lower surfaces and a sidewall of the bonding pad. Because the conductive layer is wrapped around the edge of the bonding pad, contact surface and structural strength between the conductive layer and the bonding pad are increased.
摘要翻译：提供一种具有大导电面积的集成电路封装及其制造方法。该封装包括具有上表面和下表面的集成电路芯片和形成在上表面上的感光装置。随后在集成电路芯片的上表面上形成接合焊盘并电连接到感光装置。然后在集成电路芯片的侧壁上形成导电层，并且缠绕在焊盘的边缘上以电连接到焊盘。在封装中，导电层与焊盘的上下表面和侧壁接触。由于导电层缠绕在接合焊盘的边缘周围，导电层和焊盘之间的接触表面和结构强度增加。

57. 发明申请

US20080007934A1 Electronic device with EMI screen & packing process thereof 有权
标题翻译：具有EMI屏蔽及其包装工艺的电子设备
公开(公告)号：US20080007934A1
公开(公告)日：2008-01-10
申请号：US11706411
申请日：2007-02-15
申请人： Chien-Hung Liu
发明人： Chien-Hung Liu
IPC分类号： H05K9/00
CPC分类号： H01L23/552 , H01L23/3114 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L2224/0231 , H01L2224/02331 , H01L2224/02371 , H01L2224/02377 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/06102 , H01L2224/11334 , H01L2224/13022 , H01L2224/131 , H01L2224/1403 , H01L2224/14051 , H01L2224/14104 , H01L2224/14515 , H01L2224/16 , H01L2224/94 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01072 , H01L2924/01082 , H01L2924/014 , H01L2224/03 , H01L2224/11 , H01L2224/05552
摘要： An electronic device with EMI screen and packaging process thereof to provide even active EMI prevention means includes adhesion of a transit substrate to a. soldering surface of the electronic device, a protection circuit layer functioning as EMI screen being paved on the bottom of the transit substrate; a packaging circuit layer being laid; protection circuit layer and the transit substrate as well as the packaging and protection circuit layers being segregated with an insulation material; and solder balls provided with electric continuity to the protection circuit layer and the packaging circuit layer being respectively implanted as soldering points respectively for EMI grounding and linkage between the electronic device and a printed circuit.
摘要翻译：具有EMI屏蔽及其封装工艺的电子设备提供均匀的有源EMI防止装置，包括将运输衬底粘附到一个电子器件的焊接表面，用作EMI屏蔽层的保护电路层铺设在运输衬底的底部; 铺设的包装电路层; 保护电路层和运输基板以及与绝缘材料隔离的封装和保护电路层; 分别为保护电路层和封装电路层提供与电连接的焊料球分别作为焊接点植入电子设备和印刷电路之间的EMI接地和连接。

58. 发明申请

US20070159419A1 Communication device with an adjustable brightness 有权
公开(公告)号：US20070159419A1
公开(公告)日：2007-07-12
申请号：US11329245
申请日：2006-01-11
申请人： Chien-Hung Liu
发明人： Chien-Hung Liu
IPC分类号： G09G3/30
CPC分类号： G09G3/3406 , G09G2320/0606 , G09G2320/0626 , H04M1/22 , H04W52/027 , Y02D70/00
摘要： The present invention discloses a communication device with an adjustable brightness that includes a control circuit coupled to a modulating unit, and the modulating unit includes a tuning button disposed on the communication device that allows user to make adjustments or controls by the tuning button to produce a first set value, and the modulating unit converts the power received by a power supply circuit of the communication device into a corresponding operating voltage according to the first set value and sends the operating voltage to a light emitting unit of the communication device for projecting a light source according to the magnitude of the operating voltage, so as to adjust and change the brightness of the light emitting unit, and achieve the effects of saving power and extending the life of the light emitting units.

59. 发明授权

US07179710B2 Method for fabricating NAND type dual bit nitride read only memory 有权
标题翻译：用于制造NAND型双位氮化物只读存储器的方法
公开(公告)号：US07179710B2
公开(公告)日：2007-02-20
申请号：US11171353
申请日：2005-07-01
申请人： Chien-Hung Liu
发明人： Chien-Hung Liu
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/513 , H01L29/518 , H01L29/7923
摘要： A NAND type dual bit nitride read only memory and a method for fabricating thereof are provided. Firstly, a plurality of isolation layers, which are spaced and parallel to each other are formed in the substrate. Next, a plurality of word lines and a plurality of oxide-nitride-oxide (ONO) stack structures are formed on the substrate. The word lines are spaced and parallel to each other, and also the word lines are perpendicular to the isolation layers. Each of the ONO stack structure is located between the corresponding word line and the substrate. And then a plurality of discontinuous bit lines, which are located between the word lines and between the isolation layers are formed on the substrate. The structure of the present invention of the NAND type dual bit nitride read only memory is similar to that of a complementary metal-oxide semiconductor (CMOS), and their fabrication processes are fully compatible.
摘要翻译：提供NAND型双位氮化物只读存储器及其制造方法。首先，在衬底中形成彼此间隔开并平行的多个隔离层。接下来，在基板上形成多个字线和多个氧化物 - 氮化物 - 氧化物（ONO）堆叠结构。字线彼此间隔开并平行，字线也垂直于隔离层。每个ONO堆叠结构位于相应的字线和基板之间。然后在衬底上形成位于字线之间和隔离层之间的多个不连续位线。本发明的NAND型双位氮化物只读存储器的结构类似于互补金属氧化物半导体（CMOS）的结构，并且它们的制造工艺是完全兼容的。

60. 发明申请

US20060272147A1 Structure of inkjet-head chip 失效
公开(公告)号：US20060272147A1
公开(公告)日：2006-12-07
申请号：US11505647
申请日：2006-08-17
申请人： Chien-Hung Liu , Jian-Chiun Liou , Chi-Ming Huang , Chia-Cheng Chiao , Chun-Jung Chen
发明人： Chien-Hung Liu , Jian-Chiun Liou , Chi-Ming Huang , Chia-Cheng Chiao , Chun-Jung Chen
IPC分类号： B41J2/205
CPC分类号： B41J2/1629 , B41J2/14129 , B41J2/1601 , B41J2/1639 , B41J2202/13 , Y10T29/49083 , Y10T29/49085 , Y10T29/49099 , Y10T29/49117 , Y10T29/49155 , Y10T29/49346 , Y10T29/49401
摘要： A structure of inkjet-head chip and a method for making the same are disclosed. Driven by the need of making a thin insulator layer to lower the working power of the inkjet-head chip, we separately manufacture a passivation layer and a second conductive layer. The passivation layer and the second conductive layer have to be formed from different materials. The defining means for the passivation layer and the second conductive layer have high selectivity and do not overetch or damage the structure of inkjet-head chip.

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