专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US06553441B1 Method and apparatus for using serial bus for PC management 失效
标题翻译：串行总线用于PC管理的方法和装置
公开(公告)号：US06553441B1
公开(公告)日：2003-04-22
申请号：US09451636
申请日：1999-11-30
申请人： Chi-Lie Wang , Eric Davis
发明人： Chi-Lie Wang , Eric Davis
IPC分类号： G06F130
CPC分类号： G06F13/385
摘要： A serial bus with pre-defined protocol may be used on the NIC to provide PC management functions. While these functions may be used with the PC powered up, they may further perform valuable tasks while the PC is powered down. With these new added functions, centralized control may be achieved which will lower the administrative cost and serve better for distributed computing.
摘要翻译：可以在NIC上使用具有预定义协议的串行总线来提供PC管理功能。虽然这些功能可以在PC上电的情况下使用，但是当PC断电时，它们可能进一步执行有价值的任务。通过这些新的附加功能，可以实现集中控制，降低管理成本，为分布式计算提供更好的服务。

52. 发明授权

US06327625B1 FIFO-based network interface supporting out-of-order processing 有权
标题翻译：基于FIFO的网络接口支持无序处理
公开(公告)号：US06327625B1
公开(公告)日：2001-12-04
申请号：US09451395
申请日：1999-11-30
申请人： Chi-Lie Wang , Li-Jau Yang , Ngo Thanh Ho
发明人： Chi-Lie Wang , Li-Jau Yang , Ngo Thanh Ho
IPC分类号： G06F1516
CPC分类号： H04L63/0236 , H04L47/2441 , H04L47/34 , H04L47/50 , H04L47/624 , H04L47/6245
摘要： Support for priority and IP security packets, and other protocols at the network interface level and in conjunction with FIFO-based packet buffers is provided by allowing out of order processing of certain packets in the FIFO. The optimized character of FIFO for sequential transfer is maintained, while particular types of packets are processed out of order to achieve minimum latency and maximum data security in an intelligent network interface card. A buffer stores data packets in an order of receipt. Logic is included in the network interface to transfer packets out of the buffer according to the order of receipt, and according to the respective packet types so that packets having a particular packet type are transferred out of the order of receipt relative to packets having other packet types.
摘要翻译：通过允许对FIFO中的某些数据包进行故障处理，来支持优先级和IP安全性数据包以及网络接口级别的其他协议以及基于FIFO的数据包缓冲区。维持用于顺序传输的FIFO的优化特性，同时特定类型的数据包处理不正常，以实现智能网络接口卡中的最小延迟和最大数据安全性。缓冲器以接收顺序存储数据包。逻辑包括在网络接口中，以根据接收顺序将数据包从缓冲器传送出去，并根据各自的分组类型，使得具有特定分组类型的分组相对于具有其他分组的分组被传送出接收顺序类型。

53. 发明授权

US5875175A Method and apparatus for time-based download control 失效
标题翻译：用于基于时间的下载控制的方法和装置
公开(公告)号：US5875175A
公开(公告)日：1999-02-23
申请号：US846900
申请日：1997-05-01
申请人： William Paul Sherer , David R. Brown , Richard Reid , Glenn Connery , Chi-Lie Wang
发明人： William Paul Sherer , David R. Brown , Richard Reid , Glenn Connery , Chi-Lie Wang
IPC分类号： H04L12/56
CPC分类号： H04L47/263 , H04L47/10 , H04L47/2441 , H04L47/28
摘要： A network transmitter schedules packets so that packets are transmitted to a host or group of hosts so as not to overload any particular part of the network. In an embodiment, the transmitter uses packet data structures with a schedule indication for packets placed in the queue so that an independently running adaptor may know when to remove packets from the queue and transmit them. In an alternative embodiment, packets are scheduled by setting a future interrupt for transmitting a packet or group of packets. In a further embodiment, packets are placed in temporal sets where a temporal set is a group of packets that can be transmitted in succession without violating the bandwidth limitations of any network segment.
摘要翻译：网络发射机调度数据包，以便将数据包传输到主机或主机组，以免过载网络的任何特定部分。在一个实施例中，发射机使用具有针对放置在队列中的分组的分组指示的分组数据结构，使得独立运行的适配器可以知道何时从队列中移除分组并传送它们。在替代实施例中，通过设置用于发送分组或分组分组的将来中断来调度分组。在另一个实施例中，分组被放置在时间集合中，其中时间集合是可以连续发送的分组组，而不违反任何网段的带宽限制。

54. 发明授权

US08291246B2 High speed network interface with automatic power management with auto-negotiation 有权
标题翻译：高速网络接口，具有自动电源管理功能，具有自动协商功能
公开(公告)号：US08291246B2
公开(公告)日：2012-10-16
申请号：US13277817
申请日：2011-10-20
申请人： Nathan Henderson , Chi-Lie Wang , Baodong Hu
发明人： Nathan Henderson , Chi-Lie Wang , Baodong Hu
IPC分类号： G06F1/32
CPC分类号： G06F1/325 , G06F1/3203 , G06F1/3209 , Y02D30/32 , Y02D50/20
摘要： A power management circuit for managing power of a network interface is provided. The network interface includes a medium interface unit coupled to a network media supporting at least a high speed protocol and a lower speed protocol. The power management logic includes logic to determine that an event signalling entry of the medium interface unit into the lower speed protocol has occurred; and logic to force the medium interface unit into the lower speed protocol in response to a determination that the event has occurred.
摘要翻译：提供了一种用于管理网络接口的电源的电源管理电路。网络接口包括耦合到支持至少高速协议和低速协议的网络媒体的媒体接口单元。电源管理逻辑包括确定媒体接口单元的事件信令条目进入低速协议的逻辑已经发生; 以及响应于事件已经发生的确定而迫使介质接口单元进入较低速度协议的逻辑。

55. 发明申请

US20120089853A1 HIGH SPEED NETWORK INTERFACE WITH AUTOMATIC POWER MANAGEMENT WITH AUTO-NEGOTIATION 有权
标题翻译：具有自动调节自动电源管理的高速网络接口
公开(公告)号：US20120089853A1
公开(公告)日：2012-04-12
申请号：US13277817
申请日：2011-10-20
申请人： Nathan Henderson , Chi-Lie Wang , Baodong Hu
发明人： Nathan Henderson , Chi-Lie Wang , Baodong Hu
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/325 , G06F1/3203 , G06F1/3209 , Y02D30/32 , Y02D50/20
摘要： A power management circuit for managing power of a network interface is provided. The network interface includes a medium interface unit coupled to a network media supporting at least a high speed protocol and a lower speed protocol. The power management logic includes logic to determine that an event signalling entry of the medium interface unit into the lower speed protocol has occurred; and logic to force the medium interface unit into the lower speed protocol in response to a determination that the event has occurred.
摘要翻译：提供了一种用于管理网络接口的电源的电源管理电路。网络接口包括耦合到支持至少高速协议和低速协议的网络媒体的媒体接口单元。电源管理逻辑包括确定媒体接口单元的事件信令条目进入低速协议的逻辑已经发生; 以及响应于事件已经发生的确定而迫使介质接口单元进入较低速度协议的逻辑。

56. 发明授权

US07945716B2 Serial buffer supporting virtual queue to physical memory mapping 有权
标题翻译：串行缓冲区支持虚拟队列到物理内存映射
公开(公告)号：US07945716B2
公开(公告)日：2011-05-17
申请号：US11863176
申请日：2007-09-27
申请人： Chi-Lie Wang , Calvin Nguyen , Mario Au
发明人： Chi-Lie Wang , Calvin Nguyen , Mario Au
IPC分类号： G06F13/10
CPC分类号： G06F12/0223 , G06F5/065 , G11C7/1075 , G11C8/12
摘要： A serial buffer having a plurality of virtual queues, which can be allocated to include various combinations of on-chip dual-port memory blocks, on-chip internal memory blocks and/or off-chip external memory blocks. The virtual queues are allocated and accessed in response to configuration bits and size bits stored on the serial buffer. Relatively large external memory blocks can be allocated to virtual queues used for data intensive operations, while relatively small and fast dual-port memory blocks can advantageously be allocated to virtual queues used for passing command and status information. The serial buffer provides an efficient and flexible manner for utilizing available memory, which not only minimizes the access latency but also provides a large amount of buffer space to meet different application needs.
摘要翻译：具有多个虚拟队列的串行缓冲器，其可以被分配以包括片上双端口存储器块，片上内部存储器块和/或片外外部存储器块的各种组合。响应于存储在串行缓冲器上的配置位和大小位，分配和访问虚拟队列。可以将相对较大的外部存储器块分配给用于数据密集型操作的虚拟队列，而相对小且快速的双端口存储器块可以有利地被分配给用于传递命令和状态信息的虚拟队列。串行缓冲器提供了一种有效和灵活的方式来利用可用的存储器，这不仅使访问延迟最小化，而且提供了大量的缓冲空间以满足不同的应用需求。

57. 发明授权

US07894480B1 Computer system and network interface with hardware based rule checking for embedded firewall 有权
标题翻译：计算机系统和网络接口，用于嵌入式防火墙的基于硬件的规则检查
公开(公告)号：US07894480B1
公开(公告)日：2011-02-22
申请号：US10228492
申请日：2002-08-27
申请人： Chi-Lie Wang , BaoDong Hu , Scott W. Mitchell
发明人： Chi-Lie Wang , BaoDong Hu , Scott W. Mitchell
IPC分类号： H04J3/24 , H04L12/56
CPC分类号： H04L63/0263 , H04L63/0209 , H04L69/16
摘要： A data processing system adapted for high-speed network communications, a method for managing a network interface and a network interface for such system, are provided, in which processing of packets received over the network is achieved by embedded logic at the network interface level. Incoming packets on the network interface are parsed and classified as they are stored in a buffer memory. Functional logic coupled to the buffer memory on the network interface is enabled to access any data field within a packet in a single cycle, using pointers and packet classification information produced by the parsing and classifying step. Results of operations on the data fields in the packets are available before the packets are transferred out of the buffer memory. A data processing system, a method for management of a network interface and a network interface are also provided by the present invention that include an embedded firewall at the network interface level of the system, which protects against inside and outside attacks on the security of data processing system. Furthermore, a data processing system, a method for management of a network interface and a network interface are a provided by the present invention that support class of service management for packets incoming from the network, by applying priority rules at the network interface level of the system.
摘要翻译：提供了适用于高速网络通信的数据处理系统，用于管理这种系统的网络接口和网络接口的方法，其中通过网络接收的分组的处理由网络接口层的嵌入式逻辑实现。网络接口上的传入数据包被解析和分类，因为它们存储在缓冲存储器中。耦合到网络接口上的缓冲存储器的功能逻辑能够使用由解析和分类步骤产生的指针和分组分类信息在单个周期内访问分组内的任何数据字段。在数据包从缓冲存储器传出之前，数据包中的数据字段的操作结果是可用的。本发明还提供了一种数据处理系统，网络接口管理方法和网络接口，该系统包括在系统的网络接口层的嵌入式防火墙，可防止内部和外部对数据安全的攻击处理系统。此外，本发明提供了一种数据处理系统，网络接口管理方法和网络接口，其通过在网络接口级别应用优先级规则来支持从网络进入的分组的服务管理类别系统。

58. 发明申请

US20090228733A1 Power Management On sRIO Endpoint 审中-公开
标题翻译：电源管理在sRIO端点
公开(公告)号：US20090228733A1
公开(公告)日：2009-09-10
申请号：US12043940
申请日：2008-03-06
申请人： Chi-Lie Wang
发明人： Chi-Lie Wang
IPC分类号： G06F1/10 , G06F1/04
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128
摘要： Clock signals used to operate core receive logic and core transmit logic within a serial buffer are dynamically enabled and disabled to minimize power consumption. A physical layer interface and an event monitor are continuously enabled to identify the start of incoming transactions. Upon detecting the start of an incoming transaction, the event monitor activates a packet retry signal, and also initiates generation of a receive clock signal within the serial buffer. By the time that the incoming transaction is re-sent, the receive clock signal is enabled, thereby enabling the associated core receive logic. Once enabled, the receive clock signal remains enabled until the period between consecutive incoming transactions exceeds a timeout period, whereupon the receive clock signal is disabled. A similar mechanism is provided to dynamically enable and disable a transmit clock signal, which enables and disables corresponding core transmit logic of the serial buffer.
摘要翻译：用于在串行缓冲器内操作核心接收逻辑和核心传输逻辑的时钟信号被动态地启用和禁用，以最小化功耗。连续启用物理层接口和事件监视器，以识别传入事务的开始。在检测到进入事务的开始时，事件监视器激活分组重试信号，并且还启动在串行缓冲器内产生接收时钟信号。在传入事务被重新发送的时刻，接收时钟信号被使能，从而使得相关联的核心接收逻辑能够被执行。一旦使能，接收时钟信号保持使能，直到连续传入事务之间的周期超过超时周期，接收时钟信号被禁止。提供了类似的机制来动态地启用和禁用发送时钟信号，其使能和禁止串行缓冲器的相应核心发送逻辑。

59. 发明授权

US07307998B1 Computer system and network interface supporting dynamically optimized receive buffer queues 有权
标题翻译：计算机系统和网络接口支持动态优化的接收缓冲区队列
公开(公告)号：US07307998B1
公开(公告)日：2007-12-11
申请号：US10229361
申请日：2002-08-27
申请人： Chi-Lie Wang , BaoDong Hu , Scott W. Mitchell
发明人： Chi-Lie Wang , BaoDong Hu , Scott W. Mitchell
IPC分类号： H04L12/54
CPC分类号： H04L49/9063 , H04L49/90 , H04L49/9052
摘要： A network interface comprises the first port on which incoming data is transmitted and received at the data transfer rate of the network, a buffer memory coupled to the first port, and a second port coupled with the buffer memory, and through which transfer of packets between the host system, and the buffer memory is executed. A driver in the host system allocates a plurality of sets of receive buffers, where each set of receive buffers is composed of receive buffers having different sizes. A receive buffer descriptor cache located at the interface level stores receive buffer descriptors corresponding to receive buffers in the plurality of sets. As incoming packets arrive at the interface, logic determines the size of the incoming packet and assigns the packet to a receive buffer descriptor in the receive buffer descriptor cache according to the determined size. Upload logic at the interface level manages the uploading of packets from the buffer memory to the host system using the assigned receive buffer descriptors. A driver in the host dynamically adjusts the sizes of receive buffers in response to statistics about packet size.
摘要翻译：网络接口包括以网络的数据传输速率发送和接收输入数据的第一端口，耦合到第一端口的缓冲存储器和与缓冲存储器耦合的第二端口，执行主机系统和缓冲存储器。主机系统中的驱动器分配多组接收缓冲器，其中每组接收缓冲器由具有不同大小的接收缓冲器组成。位于接口级的接收缓冲器描述符缓存存储对应于多个集合中的接收缓冲器的接收缓冲器描述符。当输入分组到达接口时，逻辑确定输入分组的大小，并根据确定的大小将分组分配给接收缓冲器描述符高速缓存中的接收缓冲器描述符。接口级的上传逻辑管理使用分配的接收缓冲区描述符将数据包从缓冲存储器上传到主机系统。主机中的驱动程序根据数据包大小的统计信息动态调整接收缓冲区的大小。

60. 发明授权

US06640262B1 Method and apparatus for automatically configuring a configurable integrated circuit 失效
标题翻译：用于自动配置可配置集成电路的方法和装置
公开(公告)号：US06640262B1
公开(公告)日：2003-10-28
申请号：US09467724
申请日：1999-12-20
申请人： Krishna Uppunda , Eric R. Davis , Nathaniel Henderson , Chi-Lie Wang , Alexander Herrera
发明人： Krishna Uppunda , Eric R. Davis , Nathaniel Henderson , Chi-Lie Wang , Alexander Herrera
IPC分类号： G06F15177
CPC分类号： G06F15/7867
摘要： A method and apparatus for automatically configuring a configurable integrated circuit. One embodiment comprises a method for automatically loading data including configuration data to a configurable integrated circuit upon initialization of a system in which the configurable integrated circuit is embedded. The method of one embodiment comprises storing a plurality of commands and a plurality of data elements in a non-volatile memory of the system. The method further comprises reading contents of an initial address in the non-volatile memory. If the initial address contains a command, depending upon a type of the command, the method comprises writing contents of a next address in the non-volatile memory to a register space of the configurable integrated circuit, to a configuration space of the configurable integrated circuit, or to a command space of the configurable integrated circuit.
摘要翻译：一种用于自动配置可配置集成电路的方法和装置。一个实施例包括在嵌入可配置集成电路的系统的初始化时自动将包括配置数据的数据加载到可配置集成电路的方法。一个实施例的方法包括将多个命令和多个数据元素存储在系统的非易失性存储器中。该方法还包括读取非易失性存储器中的初始地址的内容。如果初始地址包含命令，则取决于命令的类型，该方法包括将非易失性存储器中的下一个地址的内容写入可配置集成电路的寄存器空间到可配置集成电路的配置空间，或可配置集成电路的命令空间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式