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51. 发明授权

US06502224B2 Method and apparatus for synthesizing levelized logic 失效
标题翻译：用于合成等级化逻辑的方法和装置
公开(公告)号：US06502224B2
公开(公告)日：2002-12-31
申请号：US09833413
申请日：2001-04-12
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5054 , Y02T10/82
摘要： A method and apparatus for synthesizing logic circuits with synchronized outputs is disclosed. A logic designer selects a fixed number of levels in which to synthesize the circuit, each level implementing a plurality of different logic function all having the same propagation delay. Circuit outputs are synchronized by ensuring that each logic function is synthesized by connecting logic functions from level to level such that each signal path passes through each level once and only once.
摘要翻译：公开了一种用于合成具有同步输出的逻辑电路的方法和装置。逻辑设计者选择固定数量的电平来合成电路，每个级别实现多个具有相同传播延迟的不同逻辑功能。通过确保每个逻辑功能通过将逻辑功能从电平连接到电平来合成，使得每个信号路径通过每个级别一次且仅一次，从而同步电路输出。

52. 发明授权

US6138208A Multiple level cache memory with overlapped L1 and L2 memory access 失效
标题翻译：具有重叠的L1和L2存储器访问的多级高速缓存
公开(公告)号：US6138208A
公开(公告)日：2000-10-24
申请号：US59000
申请日：1998-04-13
申请人： Sang Hoo Dhong , Harm Peter Hofstee , David Meltzer , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Harm Peter Hofstee , David Meltzer , Joel Abraham Silberman
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0884
摘要： A method of providing simultaneous, or overlapped, access to multiple cache levels to reduce the latency penalty for a higher level cache miss. A request for a value (data or instruction) is issued by the processor, and is forwarded to the lower level of the cache before determining whether a cache miss of the value has occurred at the higher level of the cache. In the embodiment wherein the lower level is an L2 cache, the L2 cache may supply the value directly to the processor. Address decoders are operated in parallel at the higher level of the cache to satisfy a plurality of simultaneous memory requests. One of the addresses (selected by priority logic based on hit/miss information from the higher level of the cache) is gated by a multiplexer to a plurality of memory array word line drivers of the lower level of the cache. Some bits in the address which do not require virtual-to-real translation can be immediately decoded.
摘要翻译：提供对多个高速缓存级别的同时或重叠访问以减少对于较高级别的高速缓存未命中的延迟损失的方法。处理器发出值（数据或指令）的请求，并且在确定高速缓存的较高级别是否发生了该值的高速缓存未命中之前被转发到高速缓存的较低级。在其中较低级别是L2高速缓存的实施例中，L2高速缓存可以将该值直接提供给处理器。地址解码器在高速缓存的较高级并行操作以满足多个同时的存储器请求。其中一个地址（由基于来自高速缓存的较高级别的命中/未命中信息的优先级逻辑选择）由多路复用器选通到高速缓存的较低级的多个存储器阵列字线驱动器。可以立即解码地址中的一些不需要虚拟到实际转换的位。

53. 发明授权

US08838950B2 Security architecture for system on chip 有权
标题翻译：片上系统的安全架构
公开(公告)号：US08838950B2
公开(公告)日：2014-09-16
申请号：US10601374
申请日：2003-06-23
申请人： David John Craft , Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , John Samuel Liberty
发明人： David John Craft , Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , John Samuel Liberty
IPC分类号： G06F21/00 , H04L9/32 , G06F21/53
CPC分类号： G06F21/53 , H04L9/3226 , H04L2209/56
摘要： The present invention provides for authenticating code and/or data and providing a protected environment for execution. The present invention provides for dynamically partitioning and un-partitioning a local store for the authentication of code or data. The local store is partitioned into an isolated and non-isolated section. Code or data is loaded into the isolated section. The code or data is authenticated in the isolated section of the local store. After authentication, the code is executed. After execution, the memory within the isolated region of the attached processor unit is erased, and the attached processor unit de-partitions the isolated section within the local store.
摘要翻译：本发明提供了验证代码和/或数据并提供受保护的环境以供执行。本发明提供了用于对代码或数据的认证的动态分区和分区本地存储。本地商店被划分成一个隔离和非隔离的部分。代码或数据被加载到隔离的部分。代码或数据在本地存储的隔离部分进行身份验证。认证后，执行代码。在执行之后，附着的处理器单元的隔离区域内的存储器被擦除，并且附加的处理器单元对本地存储器内的隔离部分进行分区。

54. 发明授权

US08677136B2 Authenticating messages using cryptographic algorithm constants supplied to a storage-constrained target 失效
标题翻译：使用提供给存储受限目标的加密算法常数验证消息
公开(公告)号：US08677136B2
公开(公告)日：2014-03-18
申请号：US13326489
申请日：2011-12-15
申请人： Daniel Alan Brokenshire , Harm Peter Hofstee , Mohammad Peyravian
发明人： Daniel Alan Brokenshire , Harm Peter Hofstee , Mohammad Peyravian
IPC分类号： H04L9/12
CPC分类号： H04L9/3242
摘要： The present invention provides for authenticating a message. A security function is performed upon the message. The message is sent to a target. The output of the security function is sent to the target. At least one publicly known constant is sent to the target. The received message is authenticated as a function of at least a shared key, the received publicly known constants, the security function, the received message, and the output of the security function. If the output of the security function received by the target is the same as the output generated as a function of at least the received message, the received publicly known constants, the security function, and the shared key, neither the message nor the constants have been altered.
摘要翻译：本发明提供用于认证消息。对消息执行安全功能。该消息被发送到目标。安全功能的输出被发送到目标。至少有一个公认的常数被发送到目标。接收到的消息被认证为至少共享密钥，接收的公知常数，安全功能，接收到的消息和安全功能的输出的功能。如果目标接收到的安全功能的输出与至少作为接收到的消息的函数产生的输出相同，则所接收的公知常数，安全功能和共享密钥，消息和常数都不具有被改变了

55. 发明申请

US20120301977A1 SILICON CARRIER STRUCTURE AND METHOD OF FORMING SAME 审中-公开
标题翻译：硅载体结构及其形成方法
公开(公告)号：US20120301977A1
公开(公告)日：2012-11-29
申请号：US13569872
申请日：2012-08-08
申请人： Paul Stephen Andry , Harm Peter Hofstee , George A. Katopis , John Ulrich Knickerbocker , Robert K. Montoye , Chirag S. Patel
发明人： Paul Stephen Andry , Harm Peter Hofstee , George A. Katopis , John Ulrich Knickerbocker , Robert K. Montoye , Chirag S. Patel
IPC分类号： H01L21/66 , G06F17/50
CPC分类号： H01L25/0655 , H01L23/147 , H01L23/60 , H01L25/0652 , H01L2224/16225 , H01L2924/10253 , H01L2924/157 , H01L2924/00
摘要： A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate.
摘要翻译：一种用于电子封装的硅载体结构包括基底，设置在基底基板上的硅载体衬底，设置在硅载体衬底上的存储芯片，设置在硅载体衬底上的微处理器芯片，设置在硅衬底上的输入/输出芯片硅载体衬底和设置在硅载体衬底上的时钟芯片。

56. 发明申请

US20120096278A1 Authenticating Messages Using Cryptographic Algorithm Constants Supplied to a Storage-Constrained Target 失效
标题翻译：使用提供给存储约束目标的密码算法常数验证消息
公开(公告)号：US20120096278A1
公开(公告)日：2012-04-19
申请号：US13326489
申请日：2011-12-15
申请人： Daniel Alan Brokenshire , Harm Peter Hofstee , Mohammad Peyravian
发明人： Daniel Alan Brokenshire , Harm Peter Hofstee , Mohammad Peyravian
IPC分类号： H04L9/32
CPC分类号： H04L9/3242
摘要： The present invention provides for authenticating a message. A security function is performed upon the message. The message is sent to a target. The output of the security function is sent to the target. At least one publicly known constant is sent to the target. The received message is authenticated as a function of at least a shared key, the received publicly known constants, the security function, the received message, and the output of the security function. If the output of the security function received by the target is the same as the output generated as a function of at least the received message, the received publicly known constants, the security function, and the shared key, neither the message nor the constants have been altered.
摘要翻译：本发明提供用于认证消息。对消息执行安全功能。该消息被发送到目标。安全功能的输出被发送到目标。至少有一个公认的常数被发送到目标。接收到的消息被认证为至少共享密钥，接收的公知常数，安全功能，接收到的消息和安全功能的输出的功能。如果目标接收到的安全功能的输出与至少作为接收到的消息的函数产生的输出相同，则所接收的公知常数，安全功能和共享密钥，消息和常数都不具有被改变了

57. 发明授权

US08024574B2 Unidirectional message masking and validation system and method 有权
标题翻译：单向消息屏蔽和验证系统和方法
公开(公告)号：US08024574B2
公开(公告)日：2011-09-20
申请号：US10763079
申请日：2004-01-22
申请人： Daniel Brokenshire , Harm Peter Hofstee , Mohammad Peyravian
发明人： Daniel Brokenshire , Harm Peter Hofstee , Mohammad Peyravian
IPC分类号： H04L9/32
CPC分类号： H04L9/0662 , H04L2209/04
摘要： A system for secure communication is provided. A random value generator is configured to generate a random value. A message validation code generator is coupled to the random value generator and configured to generate a message validation code based on a predetermined key, a message, and the random value. A one-time pad generator is coupled to the random number generator and configured to generate a one-time pad based on the random value and the predetermined key. And a masked message generator is coupled to the one-time pad generator and configured to generate a masked message based on the one-time pad and the message. A protected message envelope generator is coupled to the random value generator, the message validation code generator, and the masked message generator, and is configured to generate a protected message envelope based on the random value, the message validation code, and the masked message.
摘要翻译：提供了用于安全通信的系统。随机值生成器被配置为生成随机值。消息验证码发生器耦合到随机值生成器并且被配置为基于预定密钥，消息和随机值生成消息验证码。一次性垫发生器耦合到随机数发生器并且被配置为基于随机值和预定密钥生成一次性焊盘。并且屏蔽的消息发生器耦合到一次性衬垫发生器并且被配置为基于一次性焊盘和消息来生成屏蔽消息。受保护的消息包络生成器耦合到随机值生成器，消息验证码生成器和掩蔽消息生成器，并且被配置为基于随机值，消息验证码和掩蔽消息来生成受保护的消息包络。

58. 发明授权

US07720982B2 Computer architecture and software cells for broadband networks 有权
标题翻译：宽带网络的计算机架构和软件单元
公开(公告)号：US07720982B2
公开(公告)日：2010-05-18
申请号：US11716845
申请日：2007-03-12
申请人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Peter Hofstee , Martin E. Hopkins , Charles Ray Johns , James Allan Kahle , Shigehiro Asano , Atsushi Kunimatsu
发明人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Peter Hofstee , Martin E. Hopkins , Charles Ray Johns , James Allan Kahle , Shigehiro Asano , Atsushi Kunimatsu
IPC分类号： G06F15/16
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

59. 发明授权

US07496673B2 SIMD-RISC microprocessor architecture 失效
标题翻译： SIMD-RISC微处理器架构
公开(公告)号：US07496673B2
公开(公告)日：2009-02-24
申请号：US11065707
申请日：2005-02-24
申请人： Michael Karl Gschwind , Harm Peter Hofstee , Martin E. Hopkins , James Allan Kahle
发明人： Michael Karl Gschwind , Harm Peter Hofstee , Martin E. Hopkins , James Allan Kahle
IPC分类号： G06F15/16
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。

60. 发明申请

US20090024684A1 Method for Controlling Rounding Modes in Single Instruction Multiple Data (SIMD) Floating-Point Units 有权
标题翻译：用于控制单指令多数据（SIMD）浮点单元中舍入模式的方法
公开(公告)号：US20090024684A1
公开(公告)日：2009-01-22
申请号：US12238500
申请日：2008-09-26
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/483
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49968 , G06F7/49973 , G06F7/49989 , G06F2207/3828
摘要： A method for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.
摘要翻译：公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的方法。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。

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