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51. 发明授权

US08645633B2 Facilitating data coherency using in-memory tag bits and faulting stores 有权
标题翻译：使用内存中标记位和故障存储来促进数据一致性
公开(公告)号：US08645633B2
公开(公告)日：2014-02-04
申请号：US13109249
申请日：2011-05-17
申请人： Guy L. Guthrie , Geraint North , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Geraint North , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/145 , G06F9/4552 , G06F12/1045 , G06F2212/1008
摘要： Fine-grained detection of data modification of original data is provided by associating separate guard bits with granules of memory storing the original data from which translated data has been obtained. The guard bits facilitate indicating whether the original data stored in the associated granule is indicated as protected. The guard bits are set and cleared by special-purpose instructions. Responsive to initiating a data store operation to modify the original data, the associated guard bit(s) are checked to determine whether the original data is indicated as protected. Responsive to the checking indicating that a guard bit is set for the associated original data, the data store operation to modify the original data is faulted and the translated data is discarded, thereby facilitating data coherency between the original data and the translated data.
摘要翻译：通过将单独的保护位与存储已经获得翻译数据的原始数据的存储器的颗粒相关联来提供原始数据的数据修改的细粒度检测。保护位有助于指示存储在相关联的颗粒中的原始数据是否被指示为受保护的。保护位通过专用指令进行设置和清除。响应于启动数据存储操作以修改原始数据，检查相关联的保护位以确定原始数据是否被指示为受保护的。响应于指示为相关联的原始数据设置了保护位的检查，修改原始数据的数据存储操作发生故障，并且转换的数据被丢弃，从而促进原始数据和转换的数据之间的数据一致性。

52. 发明申请

US20120324189A1 AGGREGATE DATA PROCESSING SYSTEM HAVING MULTIPLE OVERLAPPING SYNTHETIC COMPUTERS 有权
标题翻译：具有多重叠加合成计算机的综合数据处理系统
公开(公告)号：US20120324189A1
公开(公告)日：2012-12-20
申请号：US13599856
申请日：2012-08-30
申请人： Guy L. Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
IPC分类号： G06F12/14
CPC分类号： G06F12/0813 , G06F12/0284 , G06F15/167
摘要： A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third SMP computer has at least fifth and sixth processing units and third, fourth and fifth system memory pools. The fourth system memory pool is inaccessible to the third, fourth and sixth processing units and accessible to at least the second and fifth processing units, and the fifth system memory pool is inaccessible to the first, second and sixth processing units and accessible to at least the fourth and fifth processing units. A first interconnect couples the second processing unit for load-store coherent, ordered access to the fourth system memory pool, and a second interconnect couples the fourth processing unit for load-store coherent, ordered access to the fifth system memory pool.
摘要翻译：第一SMP计算机具有第一和第二处理单元和第一系统存储器池，第二SMP计算机具有第三和第四处理单元和第二系统存储器池，并且第三SMP计算机具有至少第五和第六处理单元，第三SMP计算机具有至少第五和第六处理单元，第四和第五系统内存池。第四系统存储器池对于第三，第四和第六处理单元是不可访问的，并且可访问至少第二和第五处理单元，并且第五系统存储器池对于第一，第二和第六处理单元是不可访问的，并且至少可访问第四和第五处理单元。第一互连耦合第二处理单元，用于对第四系统存储池进行加载存储相关的有序访问，并且第二互连耦合第四处理单元，用于加载存储相关的有序访问到第五系统存储池。

53. 发明授权

US08205024B2 Protecting ownership transfer with non-uniform protection windows 有权
标题翻译：用不均匀的保护窗保护所有权转让
公开(公告)号：US08205024B2
公开(公告)日：2012-06-19
申请号：US11560619
申请日：2006-11-16
申请人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F15/173
摘要： In a data processing system, a plurality of agents communicate operations therebetween. Each operation includes a request and a combined response representing a system-wide response to the request. Latencies of requests and combined responses between the plurality of agents are observed. Each of the plurality of agents is configured with a respective duration of a protection window extension by reference to the observed latencies. Each protection window extension is a period following receipt of a combined response during winch an associated one of the plurality of agents protects transfer of coherency ownership of a data granule between agents. The plurality of agents employing protection window extensions in accordance with the configuration, and at least two of the agents have protection window extensions of differing durations.
摘要翻译：在数据处理系统中，多个代理之间进行通信。每个操作包括一个请求和组合的响应，代表对该请求的全系统响应。观察到请求的延迟和多个代理之间的组合响应。通过参考所观察到的延迟，多个代理中的每个被配置有保护窗口扩展的相应持续时间。每个保护窗口扩展是在绞盘期间接收到组合响应之后的周期，多个代理之一相关联的一个代理保护代理之间的数据粒子的一致性所有权的传送。多个代理根据配置使用保护窗口扩展，并且至少两个代理具有不同持续时间的保护窗口扩展。

54. 发明授权

US08095733B2 Virtual barrier synchronization cache castout election 失效
标题翻译：虚拟屏障同步缓存突发选举
公开(公告)号：US08095733B2
公开(公告)日：2012-01-10
申请号：US12419343
申请日：2009-04-07
申请人： Ravi K. Arimilli , Guy L. Guthrie , Michael Siegel , William J. Starke , Derek E. Williams
发明人： Ravi K. Arimilli , Guy L. Guthrie , Michael Siegel , William J. Starke , Derek E. Williams
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/0811 , G06F9/30101 , G06F9/3851 , G06F9/522
摘要： A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region. Each of the plurality of processing units includes a processor core and a cache memory including a cache controller and a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory. The cache controller of a first processing unit, responsive to a memory access request from its processor core that targets a first VBSR line, transfers responsibility for writing back to the virtual barrier synchronization region a second VBSR line contemporaneously held in the cache arrays of first, second and third processing units. The responsibility is transferred via an election held over the interconnect fabric.
摘要翻译：数据处理系统包括互连结构，耦合到互连结构并包括分配给虚拟屏障同步寄存器（VBSR）的存储的虚拟屏障同步区域的系统存储器，以及耦合到互连结构的多个处理单元，访问虚拟屏障同步区域。多个处理单元中的每一个包括处理器核心和高速缓存存储器，其包括高速缓存控制器和从系统存储器的虚拟屏障同步区域缓存VBSR行的高速缓存阵列。响应于来自其处理器核心的第一VBSR线路的存储器访问请求的第一处理单元的高速缓存控制器将负责向第一虚拟屏障同步区域写回同时保存在第一VBSR线路的高速缓存阵列中的第二VBSR线路，第二和第三处理单元。通过互连结构上的选举来转移责任。

55. 发明申请

US20110161588A1 FORMATION OF AN EXCLUSIVE OWNERSHIP COHERENCE STATE IN A LOWER LEVEL CACHE 有权
标题翻译：在较低级别的高速缓存中形成独家所有权的相关状态
公开(公告)号：US20110161588A1
公开(公告)日：2011-06-30
申请号：US12649725
申请日：2009-12-30
申请人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams , Phillip G. Williams
发明人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811 , G06F9/3834 , G06F12/0815 , G06F12/0831 , Y02D10/13
摘要： In response to a memory access request of a processor core that targets a target cache line, the lower level cache of a vertical cache hierarchy associated with the processor core supplies a copy of the target cache line to an upper level cache in the vertical cache hierarchy and retains a copy in a shared coherence state. The upper level cache holds the copy of the target cache line in a private shared ownership coherence state indicating that each cached copy of the target memory block is cached within the vertical cache hierarchy associated with the processor core. In response to the upper level cache signaling replacement of the copy of the target cache line in the private shared ownership coherence state, the lower level cache updates its copy of the target cache line to the exclusive ownership coherence state without coherency messaging with other vertical cache hierarchies.
摘要翻译：响应于针对目标高速缓存线的处理器核心的存储器访问请求，与处理器核心相关联的垂直高速缓存层级的较低级缓存将目标高速缓存行的副本提供给垂直高速缓存层级中的高级缓存并保留共享一致状态的副本。高级缓存将目标高速缓存行的副本保存在私有共享所有权一致状态中，指示目标存储器块的每个高速缓存副本被缓存在与处理器核心相关联的垂直高速缓存层级内。响应于在私有共享所有权相干状态下高级缓存信令替换目标高速缓存行的副本，下级缓存将其目标高速缓存行的副本更新为独占所有权相干状态，而不与其他垂直高速缓存的一致性消息传递层次结构。

56. 发明申请

US20110153943A1 Aggregate Data Processing System Having Multiple Overlapping Synthetic Computers 有权
标题翻译：具有多重重合成计算机的综合数据处理系统
公开(公告)号：US20110153943A1
公开(公告)日：2011-06-23
申请号：US12643800
申请日：2009-12-21
申请人： Guy L. Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00 , G06F12/14 , G06F12/08
CPC分类号： G06F12/0813 , G06F12/0284 , G06F15/167
摘要： A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third SMP computer has at least fifth and sixth processing units and third, fourth and fifth system memory pools. The fourth system memory pool is inaccessible to the third, fourth and sixth processing units and accessible to at least the second and fifth processing units, and the fifth system memory pool is inaccessible to the first, second and sixth processing units and accessible to at least the fourth and fifth processing units. A first interconnect couples the second processing unit for load-store coherent, ordered access to the fourth system memory pool, and a second interconnect couples the fourth processing unit for load-store coherent, ordered access to the fifth system memory pool.
摘要翻译：第一SMP计算机具有第一和第二处理单元和第一系统存储器池，第二SMP计算机具有第三和第四处理单元和第二系统存储器池，并且第三SMP计算机具有至少第五和第六处理单元，第三SMP计算机具有至少第五和第六处理单元，第四和第五系统内存池。第四系统存储器池对于第三，第四和第六处理单元是不可访问的，并且可访问至少第二和第五处理单元，并且第五系统存储器池对于第一，第二和第六处理单元是不可访问的，并且至少可访问第四和第五处理单元。第一互连耦合第二处理单元，用于对第四系统存储池进行加载存储相关的有序访问，并且第二互连耦合第四处理单元，用于加载存储相关的有序访问到第五系统存储池。

57. 发明申请

US20100268884A1 Updating Partial Cache Lines in a Data Processing System 有权
标题翻译：更新数据处理系统中的部分缓存行
公开(公告)号：US20100268884A1
公开(公告)日：2010-10-21
申请号：US12424434
申请日：2009-04-15
申请人： David W. Cummings , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams , Phillip G. Williams
发明人： David W. Cummings , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0822 , G06F12/0897 , G06F2212/507
摘要： A processing unit for a data processing system includes a processor core having one or more execution units for processing instructions and a register file for storing data accessed in processing of the instructions. The processing unit also includes a multi-level cache hierarchy coupled to and supporting the processor core. The multi-level cache hierarchy includes at least one upper level of cache memory having a lower access latency and at least one lower level of cache memory having a higher access latency. The lower level of cache memory, responsive to receipt of a memory access request that hits only a partial cache line in the lower level cache memory, sources the partial cache line to the at least one upper level cache memory to service the memory access request. The at least one upper level cache memory services the memory access request without caching the partial cache line.
摘要翻译：用于数据处理系统的处理单元包括具有一个或多个用于处理指令的执行单元的处理器核心和用于存储在指令处理中访问的数据的寄存器文件。处理单元还包括耦合到并支持处理器核的多级高速缓存层级。多级高速缓存层级包括具有较低访问延迟的至少一个高级缓存存储器和具有较高访问延迟的至少一个较低级别的高速缓存存储器。响应于仅接收低级高速缓冲存储器中的部分高速缓存行的存储器访问请求的响应，较低级别的高速缓存存储器将部分高速缓存行源送到至少一个上级高速缓冲存储器以服务存储器访问请求。至少一个上级缓存存储器服务于存储器访问请求，而不缓存部分高速缓存行。

58. 发明申请

US20100257316A1 Virtual Barrier Synchronization Cache Castout Election 失效
标题翻译：虚拟障碍同步缓存铸造选举
公开(公告)号：US20100257316A1
公开(公告)日：2010-10-07
申请号：US12419343
申请日：2009-04-07
申请人： Ravi K. Arimilli , Guy L. Guthrie , Michael Siegel , William J. Starke , Derek E. Williams
发明人： Ravi K. Arimilli , Guy L. Guthrie , Michael Siegel , William J. Starke , Derek E. Williams
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811 , G06F9/30101 , G06F9/3851 , G06F9/522
摘要： A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region. Each of the plurality of processing units includes a processor core and a cache memory including a cache controller and a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory. The cache controller of a first processing unit, responsive to a memory access request from its processor core that targets a first VBSR line, transfers responsibility for writing back to the virtual barrier synchronization region a second VBSR line contemporaneously held in the cache arrays of first, second and third processing units. The responsibility is transferred via an election held over the interconnect fabric.
摘要翻译：数据处理系统包括互连结构，耦合到互连结构并包括分配给虚拟屏障同步寄存器（VBSR）的存储的虚拟屏障同步区域的系统存储器，以及耦合到互连结构的多个处理单元，访问虚拟屏障同步区域。多个处理单元中的每一个包括处理器核心和高速缓存存储器，其包括高速缓存控制器和从系统存储器的虚拟屏障同步区域缓存VBSR行的高速缓存阵列。响应于来自其处理器核心的第一VBSR线路的存储器访问请求的第一处理单元的高速缓存控制器将负责向第一虚拟屏障同步区域写回同时保存在第一VBSR线路的高速缓存阵列中的第二VBSR线路，第二和第三处理单元。通过互连结构上的选举来转移责任。

59. 发明授权

US07478201B2 Data processing system, cache system and method for passively scrubbing a domain indication 失效
标题翻译：数据处理系统，缓存系统和被动清理域指示的方法
公开(公告)号：US07478201B2
公开(公告)日：2009-01-13
申请号：US11136652
申请日：2005-05-24
申请人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： Scrubbing logic in a local coherency domain issues a domain query request to at least one cache hierarchy in a remote coherency domain. The domain query request is a non-destructive probe of a coherency state associated with a target memory block by the at least one cache hierarchy. A coherency response to the domain query request is received. In response to the coherency response indicating that the target memory block is not cached in the remote coherency domain, a domain indication in the local coherency domain is updated to indicate that the target memory block is cached, if at all, only within the local coherency domain.
摘要翻译：本地一致性域中的擦除逻辑向远程一致性域中的至少一个缓存层次结构发出域查询请求。域查询请求是由至少一个高速缓存层次结构与目标存储器块相关联的一致性状态的非破坏性探测。接收到域查询请求的一致性响应。响应于指示目标存储器块未被缓存在远程一致性域中的相关性响应，本地一致性域中的域指示被更新以指示目标存储器块被缓存，如果完全只在本地一致性内域。

60. 发明授权

US07447845B2 Data processing system, processor and method of data processing in which local memory access requests are serviced by state machines with differing functionality 失效
标题翻译：数据处理系统，处理器和数据处理方法，其中本地存储器访问请求由具有不同功能的状态机服务
公开(公告)号：US07447845B2
公开(公告)日：2008-11-04
申请号：US11457333
申请日：2006-07-13
申请人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0817 , G06F12/1416
摘要： A data processing system includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array, at least one snoop machine that services memory access requests of a remote processor core, and multiple state machines that service memory access requests of the local processor core. The multiple state machines include a first state machine that has a first set of memory access requests of the local processor core that it is capable of servicing and a second state machine that has a different second set of memory access requests of the local processor core that it is capable of servicing.
摘要翻译：数据处理系统包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。高速缓冲存储器包括数据阵列，数据阵列的内容目录，至少一个服务于远程处理器核的存储器访问请求的窥探机器，以及服务于本地处理器核心的存储器访问请求的多个状态机。多状态机包括第一状态机，其具有能够服务的本地处理器核心的第一组存储器访问请求;以及第二状态机，其具有本地处理器核心的不同的第二组存储器访问请求，它能够维修。

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