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51. 发明授权

US07755104B2 FinFET pMOS double gate semiconductor device with uniaxial tensile strain applied to channel by shrinkable gate electrode material, current flow in <110> crystal orientation, and source and drain Schottky contacts with channel and manufacturing method thereof 有权
标题翻译： FinFET pMOS双栅极半导体器件具有通过可收缩的栅电极材料施加到沟道的单轴拉伸应变，<110>晶体取向的电流流动，以及沟道的源极和漏极肖特基接触及其制造方法
公开(公告)号：US07755104B2
公开(公告)日：2010-07-13
申请号：US11790389
申请日：2007-04-25
申请人： Atsushi Yagishita
发明人： Atsushi Yagishita
IPC分类号： H01L29/04 , H01L21/84
CPC分类号： H01L29/045 , H01L29/66643 , H01L29/66795 , H01L29/7839 , H01L29/7842 , H01L29/7845 , H01L29/785 , H01L29/78684
摘要： A semiconductor device that has a pMOS double-gate structure, has a substrate, the crystal orientation of the top surface of which is (100), a semiconductor layer that is made of silicon or germanium, formed on the substrate such that currents flow in a direction of a first crystal orientation, and channels are located at sidewall of the semiconductor layer, a source layer that is formed on the substrate adjacent to one end of the semiconductor layer in the direction of first crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer; a drain layer that is formed on the substrate adjacent to the other end of the semiconductor layer in the direction of first crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer; a gate electrode that is formed on the semiconductor layer in a direction of a second crystal orientation perpendicular to the current flow direction, and a gate insulating film that is disposed between the semiconductor layer and the gate electrode, wherein a uniaxial tensile strain is applied to the semiconductor layer in the direction of the second crystal orientation perpendicular to the current flow direction.
摘要翻译：具有pMOS双栅极结构的半导体器件具有衬底，其表面的晶体取向为（100），由硅或锗制成的半导体层，形成在衬底上，使得电流流过第一<110>晶体取向的方向，并且沟道位于半导体层的侧壁处，源极层在与第一<110>晶体取向的方向相邻的半导体层的一端形成在基板上，以及由金属或金属硅化物形成与半导体层的肖特基结; 漏极层，其形成在与第一<110>晶体取向方向相邻的半导体层的另一端的基板上，并且由金属或金属硅化物形成，以与半导体层形成肖特基结; 在垂直于电流流动方向的第二<110>晶体取向的方向上形成在半导体层上的栅电极，以及设置在半导体层和栅电极之间的栅极绝缘膜，其中单轴拉伸应变沿垂直于电流流动方向的第二<110>晶体取向的方向施加到半导体层。

52. 发明申请

US20090174036A1 PLASMA CURING OF PATTERNING MATERIALS FOR AGGRESSIVELY SCALED FEATURES 审中-公开
标题翻译：等离子体固化材料的等离子体刻蚀特性
公开(公告)号：US20090174036A1
公开(公告)日：2009-07-09
申请号：US11969525
申请日：2008-01-04
申请人： Nicholas C. Fuller , Michael A. Guillorn , Hirohisa Kawasaki , Atsushi Yagishita
发明人： Nicholas C. Fuller , Michael A. Guillorn , Hirohisa Kawasaki , Atsushi Yagishita
IPC分类号： H01L29/30 , G03F7/26
CPC分类号： G03F7/40
摘要： A methodology is disclosed that enables the fabrication of semiconductor devices (i.e., STI structures, gates, and interconnects) with significantly reduced line edge roughness (LER) and line width roughness (LEW) post lithography patterning. The inventive methodology entails the use of an inert species containing plasma tuned to enhanced its' vacuum ultra violet (VUV) emissions post lithography and/or post one of the etch processes of a given feature (on an identical etch platform) to entice increased crosslinking of one or more patterning materials, thus enabling increased etch resistance and reduced LER and LEW post etching processing.
摘要翻译：公开了一种能够在光刻图案化之后显着降低线边缘粗糙度（LER）和线宽粗糙度（LEW）来制造半导体器件（即STI结构，栅极和互连）的方法。本发明的方法需要使用含有等离子体的惰性物质来调整光刻后的真空紫外（VUV）发射和/或给定特征（在相同的蚀刻平台上）的一个蚀刻工艺，以引发增加的交联的一个或多个图案形成材料，因此能够提高耐蚀刻性和减少LER和LEW后蚀刻处理。

53. 发明授权

US07462917B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07462917B2
公开(公告)日：2008-12-09
申请号：US11411909
申请日：2006-04-27
申请人： Atsushi Yagishita
发明人： Atsushi Yagishita
IPC分类号： H01L27/088
CPC分类号： H01L29/7851 , H01L29/66795
摘要： According to the present invention, there is provided a semiconductor device having:first and second fins formed on a semiconductor substrate to oppose each other, and made of a semiconductor layer;an active region which is formed on the semiconductor substrate so as to be connected to the first and second fins, and supplies a predetermined voltage to the first and second fins; anda gate electrode formed on an insulating film formed on the semiconductor substrate, in a position separated from the active region by a predetermined spacing, so as to cross the first and second fins,wherein in the active region, a predetermined portion between a first portion connected to the first fin and a second portion connected to the second fin is removed.
摘要翻译：根据本发明，提供了一种半导体器件，其具有：形成在半导体衬底上的第一和第二鳍片彼此相对，并由半导体层制成; 形成在所述半导体基板上以与第一和第二散热片连接并将预定电压提供给第一和第二散热片的有源区; 以及栅电极，形成在形成在所述半导体基板上的绝缘膜上，在与所述有源区隔开预定间隔的位置处，以跨越所述第一和第二鳍片，其中在所述有源区域中，在第一连接到第一翅片的部分和连接到第二翅片的第二部分被去除。

54. 发明申请

US20080220582A1 Semiconductor device and method of fabricating the same 失效
公开(公告)号：US20080220582A1
公开(公告)日：2008-09-11
申请号：US12078585
申请日：2008-04-02
申请人： Atsushi Yagishita , Akio Kaneko , Kazunari Ishimaru
发明人： Atsushi Yagishita , Akio Kaneko , Kazunari Ishimaru
IPC分类号： H01L21/8234
CPC分类号： H01L29/785 , H01L21/28097 , H01L21/823431 , H01L27/0886 , H01L29/66795 , H01L29/6681 , H01L29/7851
摘要： According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region; burying a device isolation insulating film in the trench; etching away a predetermined amount of the device isolation insulating film formed in the first region; etching away the mask material formed in the second region; forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection; depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film; planarizing the first gate electrode material by using as stoppers the mask material formed in the first region and the device isolation insulating film formed in the second region; depositing a second gate electrode material on the mask material, first gate electrode material, and device isolation insulating film; and patterning the first and second gate electrode materials, thereby forming a first gate electrode in the first region, and a second gate electrode in the second region.

55. 发明申请

US20070235819A1 Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070235819A1
公开(公告)日：2007-10-11
申请号：US11717067
申请日：2007-03-13
申请人： Atsushi Yagishita
发明人： Atsushi Yagishita
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/785 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/78621 , H01L29/78684
摘要： There is provided a semiconductor device including: convex semiconductor layers formed on a semiconductor substrate via an insulating film; gate electrodes formed on a pair of facing sides of the semiconductor layers via a gate insulating film; a channel region formed of silicon between the gate electrodes in the semiconductor layers; a source extension region and a drain extension region formed of silicon germanium or silicon carbon on both sides of the channel region in the semiconductor layers; and a source region formed of silicon so as to adjoin to the opposite side of the channel region in the source extension region, and a drain region formed of silicon so as to adjoin to the opposite side of the channel region in the drain extension region in the semiconductor layers.
摘要翻译：提供了一种半导体器件，包括：通过绝缘膜形成在半导体衬底上的凸形半导体层; 经由栅极绝缘膜形成在半导体层的一对相对侧上的栅电极; 在半导体层中的栅电极之间由硅形成的沟道区; 源极延伸区域和在半导体层中的沟道区域的两侧上由硅锗或硅碳形成的漏极延伸区域; 以及由硅形成的源极区域，以与源极延伸区域中的沟道区域的相对侧相邻，以及由硅形成的漏极区域，以与漏极延伸区域中的沟道区域的相对侧邻接半导体层。

56. 发明授权

US07242064B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07242064B2
公开(公告)日：2007-07-10
申请号：US10810837
申请日：2004-03-29
申请人： Atsushi Yagishita , Tomohiro Saito , Toshihiko Iinuma
发明人： Atsushi Yagishita , Tomohiro Saito , Toshihiko Iinuma
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66545 , H01L29/66583 , H01L29/66795 , H01L29/7853 , H01L29/78609
摘要： In a semiconductor device in which the gate electrode of a MISFET formed on a semiconductor substrate is electrically connected to a well region under the channel of the MISFET, the MISFET is formed in an island-shaped element region formed on the semiconductor substrate, and electrical connection between the gate electrode of the MISFET and the well region in the semiconductor substrate is done on the side surface of the island-shaped element region.
摘要翻译：在半导体器件中，形成在半导体衬底上的MISFET的栅极电连接到MISFET的沟道下方的阱区，MISFET形成在形成在半导体衬底上的岛状元件区域中，并且电气 MISFET的栅电极和半导体衬底中的阱区之间的连接在岛状元件区域的侧表面上进行。

57. 发明申请

US20070148843A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070148843A1
公开(公告)日：2007-06-28
申请号：US11635039
申请日：2006-12-07
申请人： Tomohiro Saito , Akio Kaneko , Atsushi Yagishita
发明人： Tomohiro Saito , Akio Kaneko , Atsushi Yagishita
IPC分类号： H01L21/8242 , H01L21/8234 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/4908 , H01L29/785
摘要： This disclosure concerns a manufacturing method of a semiconductor device includes forming a Fin-type body on an insulation layer, the Fin-type body being made of a semiconductor material and having an upper surface covered with a protective film; forming a gate insulation film on side surfaces of the Fin-type body; depositing a gate electrode material so as to cover the Fin-type body; planarizing the gate electrode material; forming a gate electrode by processing the gate electrode material; depositing an interlayer insulation film so as to cover the gate electrode; exposing the upper surface of the gate electrode; depositing a metal layer on the upper surface of the gate electrode; siliciding the gate electrode by reacting the gate electrode with the metal layer; forming a trench on the upper surface of the protective film by removing an unreacted metal in the metal layer; and filling the trench with a conductor.
摘要翻译：本公开涉及半导体器件的制造方法，包括在绝缘层上形成鳍状体，所述鳍状体由半导体材料制成，并且具有被保护膜覆盖的上表面; 在鳍型体的侧表面上形成栅极绝缘膜; 沉积栅电极材料以覆盖鳍型体; 平面化栅电极材料; 通过处理栅电极材料形成栅电极; 沉积层间绝缘膜以覆盖栅电极; 露出栅电极的上表面; 在栅电极的上表面上沉积金属层; 通过使栅电极与金属层反应来硅化栅电极; 通过去除金属层中的未反应金属在保护膜的上表面上形成沟槽; 并用导体填充沟槽。

58. 发明授权

US07214576B1 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07214576B1
公开(公告)日：2007-05-08
申请号：US11284184
申请日：2005-11-22
申请人： Akio Kaneko , Atsushi Yagishita
发明人： Akio Kaneko , Atsushi Yagishita
IPC分类号： H01L21/336 , H01L21/00 , H01L21/8242 , H01L29/80 , H01L23/48
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： A manufacturing method of a semiconductor device disclosed herein comprises: forming a first protrusion; forming a second protrusion which is higher than the first protrusion; forming a first sidewall on a side surface of the second protrusion; forming a first film so that a surface of the first film is located lower than the second protrusion; forming a mask on a side surface of the first sidewall on a side surface of the second protrusion which protrudes from the surface of the first film; and etching the first film with the mask so as to form a second sidewall on the side surface of the first sidewall on the side surface of the second protrusion but not to form the second sidewall on a side surface of the first protrusion, the second sidewall being formed of the mask and the first film.
摘要翻译：本文公开的半导体器件的制造方法包括：形成第一突起; 形成比第一突起高的第二突起; 在所述第二突起的侧表面上形成第一侧壁; 形成第一膜，使得第一膜的表面位于比第二突起低的位置; 在所述第二突起的从所述第一膜的表面突出的侧表面上在所述第一侧壁的侧表面上形成掩模; 以及用所述掩模蚀刻所述第一膜，以在所述第二突起的侧表面上的所述第一侧壁的侧表面上形成第二侧壁，但在所述第一突起的侧表面上不形成所述第二侧壁，由掩模和第一膜形成。

59. 发明申请

US20070045736A1 FinFET and method for manufacturing the same 审中-公开
标题翻译： FinFET及其制造方法
公开(公告)号：US20070045736A1
公开(公告)日：2007-03-01
申请号：US11266357
申请日：2005-11-04
申请人： Atsushi Yagishita
发明人： Atsushi Yagishita
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L29/045 , H01L29/6681 , H01L29/785
摘要： A gate electrode is arranged in a direction parallel or perpendicular to a specified crystal orientation of a substrate. A first transistor of a first conductivity type has a first active region, which is arranged in a direction perpendicular to the gate electrode. A second transistor of a second conductivity type has a second active region, which is inclined relative to the gate electrode.
摘要翻译：栅极布置在与衬底的指定晶体取向平行或垂直的方向上。第一导电类型的第一晶体管具有沿垂直于栅电极的方向排列的第一有源区。第二导电类型的第二晶体管具有相对于栅电极倾斜的第二有源区。

60. 发明申请

US20060194378A1 Semiconductor device and method of fabricating the same 有权
公开(公告)号：US20060194378A1
公开(公告)日：2006-08-31
申请号：US11411909
申请日：2006-04-27
申请人： Atsushi Yagishita
发明人： Atsushi Yagishita
IPC分类号： H01L21/338
CPC分类号： H01L29/7851 , H01L29/66795
摘要： According to the present invention, there is provided a semiconductor device having: first and second fins formed on a semiconductor substrate to oppose each other, and made of a semiconductor layer; an active region which is formed on the semiconductor substrate so as to be connected to the first and second fins, and supplies a predetermined voltage to the first and second fins; and a gate electrode formed on an insulating film formed on the semiconductor substrate, in a position separated from the active region by a predetermined spacing, so as to cross the first and second fins, wherein in the active region, a predetermined portion between a first portion connected to the first fin and a second portion connected to the second fin is removed.

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