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51. 发明授权

US07165131B2 Separating transactions into different virtual channels 有权
标题翻译：将事务分为不同的虚拟通道
公开(公告)号：US07165131B2
公开(公告)日：2007-01-16
申请号：US10833236
申请日：2004-04-27
申请人： Kenneth C. Creta , Aaron T. Spink , Robert G. Blankenship
发明人： Kenneth C. Creta , Aaron T. Spink , Robert G. Blankenship
IPC分类号： G06F13/00 , G06F13/36 , G06F13/42
CPC分类号： G06F13/36 , G06F13/12
摘要： In one embodiment of the present invention, a method may include separating incoming transactions to an agent of a coherent system into at least a first channel, a second channel, and a third channel, based upon a type of the incoming transactions. The incoming transactions may be sent by a peer device coupled to the coherent system. By separating the transactions based on type, deadlocks may be avoided.
摘要翻译：在本发明的一个实施例中，一种方法可以包括基于传入事务的类型，将进入的事务分离为至少第一信道，第二信道和第三信道中的相干系统的代理。传入的事务可以由耦合到相干系统的对等设备发送。通过基于类型分离事务，可能会避免死锁。

52. 发明授权

US06842827B2 Cache coherency arrangement to enhance inbound bandwidth 失效
标题翻译：缓存一致性排列，以增强入站带宽
公开(公告)号：US06842827B2
公开(公告)日：2005-01-11
申请号：US10038996
申请日：2002-01-02
申请人： Robert G. Blankenship , Matthew A. Lambert , Tony S. Rand
发明人： Robert G. Blankenship , Matthew A. Lambert , Tony S. Rand
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0835
摘要： A cache coherency arrangement with support for pre-fetch ownership, to enhance inbound bandwidth for single leaf and multiple leaf, input-output interfaces, with shared memory space is disclosed. Embodiments comprise ownership stealing to enhance inbound bandwidth and to prevent or attenuate starvation of transactions or of an input-output interface for transactions.
摘要翻译：公开了一种支持预取所有权的高速缓存一致性布置，以增强具有共享存储空间的单页和多页输入输出接口的入站带宽。实施例包括所有权盗取以增强入站带宽并且防止或衰减交易的饥饿或交易的输入 - 输出接口。

53. 发明授权

US09753885B2 Multislot link layer flit wherein flit includes three or more slots whereby each slot comprises respective control field and respective payload field 有权
公开(公告)号：US09753885B2
公开(公告)日：2017-09-05
申请号：US14437612
申请日：2013-03-16
申请人： Jeff Willey , Robert G. Blankenship , Jeffrey C. Swanson , Robert J. Safranek
发明人： Jeff Willey , Robert G. Blankenship , Jeffrey C. Swanson , Robert J. Safranek
IPC分类号： G06F13/00 , G06F13/42 , G06F12/0831 , G06F9/30 , G06F12/0806 , H04L12/933 , G06F9/46 , G06F13/40 , G06F12/0813 , G06F12/0815 , G06F9/445 , H04L12/741 , G06F9/44 , H04L12/46
CPC分类号： G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/73 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4282 , G06F13/4286 , G06F13/4291 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L9/0662 , H04L12/4641 , H04L45/74 , H04L49/15 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/40 , Y02D10/44 , Y02D30/30
摘要： Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.

54. 发明申请

US20170187805A1 Systems, Methods, and Apparatuses for Range Protection 审中-公开
公开(公告)号：US20170187805A1
公开(公告)日：2017-06-29
申请号：US14983087
申请日：2015-12-29
申请人： Francesc Guim Bernet , Karthik Kumar , Thomas Willhalm , Raj K. Ramanujan , Robert G. Blankenship
发明人： Francesc Guim Bernet , Karthik Kumar , Thomas Willhalm , Raj K. Ramanujan , Robert G. Blankenship
IPC分类号： H04L29/08 , G06F3/06 , G06F9/46
摘要： Systems, methods, and apparatuses for range protection. In some embodiments, an apparatus comprises at least one monitoring circuit to monitor for memory accesses to an address space and take action upon a violation to the address space, wherein the action is one of generating a notification to a node that requested the monitor, generating the wrong request, generate a notification in a specific context of the home node, and generating a notification in a node that has ownership of the address space; at least one a protection table to store an identifier of the address space; and at least one hardware core to execute an instruction to enable the monitoring circuit.

55. 发明授权

US09208110B2 Raw memory transaction support 有权
标题翻译：原始内存事务支持
公开(公告)号：US09208110B2
公开(公告)日：2015-12-08
申请号：US13994130
申请日：2011-11-29
申请人： Robert J. Safranek , Robert G. Blankenship , Zhong-Ning Cai
发明人： Robert J. Safranek , Robert G. Blankenship , Zhong-Ning Cai
IPC分类号： G06F13/40 , G06F13/16
CPC分类号： G06F13/16 , G06F13/1663 , G06F13/40 , G06F13/4004 , G06F13/4022
摘要： Methods, systems, and apparatus for implementing raw memory transactions. An SoC is configured with a plurality of nodes coupled together forming a ring interconnect. Processing cores and memory cache components are operatively coupled to and co-located at respective nodes. The memory cache components include a plurality of last level caches (LLC's) operating as a distributed LLC and a plurality of home agents and caching agents employed for supporting coherent memory transactions. Route-back tables are used to encode memory transactions requests with embedded routing data that is implemented by agents that facilitate data transfers between link interface nodes and memory controllers. Accordingly, memory request data corresponding to raw memory transactions may be routed back to requesting entities using headerless packets.
摘要翻译：用于实现原始内存事务的方法，系统和装置。 SoC配置有耦合在一起的多个节点，形成环形互连。处理核心和存储器高速缓存组件可操作地耦合到并位于相应节点处。存储器高速缓存组件包括作为分布式LLC操作的多个最后级别缓存（LLC）和用于支持相干存储器事务的多个归属代理和高速缓存代理。路由表用于使用便于在链路接口节点和存储器控制器之间进行数据传输的代理实现的嵌入式路由数据对内存事务请求进行编码。因此，对应于原始存储器事务的存储器请求数据可以使用无头段分组路由回请求实体。

56. 发明申请

US20150127907A1 METHOD, APPARATUS AND SYSTEM FOR HANDLING CACHE MISSES IN A PROCESSOR 有权
标题翻译：处理器中处理缓存错误的方法，装置和系统
公开(公告)号：US20150127907A1
公开(公告)日：2015-05-07
申请号：US14070864
申请日：2013-11-04
申请人： Bahaa Fahim , Samuel D. Strom , Vedaraman Geetha , Robert G. Blankenship , Yen-Cheng Liu , Krishnakumar Ganapathy , Cesar Maldonado
发明人： Bahaa Fahim , Samuel D. Strom , Vedaraman Geetha , Robert G. Blankenship , Yen-Cheng Liu , Krishnakumar Ganapathy , Cesar Maldonado
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0813 , G06F12/0831 , G06F12/0884 , G06F2212/2542 , Y02D10/13
摘要： In an embodiment, a processor includes one or more cores, and a distributed caching home agent (including portions associated with each core). Each portion includes a cache controller to receive a read request for data and, responsive to the data not being present in a cache memory associated with the cache controller, to issue a memory request to a memory controller to request the data in parallel with communication of the memory request to a home agent, where the home agent is to receive the memory request from the cache controller and to reserve an entry for the memory request. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括一个或多个核心和分布式缓存归属代理（包括与每个核心相关联的部分）。每个部分包括高速缓存控制器，用于接收对数据的读取请求，并且响应于不存在于与高速缓存控制器相关联的高速缓冲存储器中的数据，向存储器控制器发出存储器请求以与对归属代理的存储器请求，其中归属代理将从高速缓存控制器接收存储器请求并且为存储器请求保留条目。描述和要求保护其他实施例。

57. 发明申请

US20140359230A1 PROTOCOL FOR CONFLICTING MEMORY TRANSACTIONS 有权
标题翻译：冲突内存交易协议
公开(公告)号：US20140359230A1
公开(公告)日：2014-12-04
申请号：US13997900
申请日：2011-12-20
申请人： Manoj K. Arora , Robert G. Blankenship , Rahul Pal , Dheemanth Nagaraj
发明人： Manoj K. Arora , Robert G. Blankenship , Rahul Pal , Dheemanth Nagaraj
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/0824 , G06F12/0828 , G06F12/0831 , G06F13/14 , G06F13/38
摘要： Embodiments of the invention describe a cache coherency protocol that eliminates the need for ordering between message classes and also eliminates home tracker preallocation. Embodiments of the invention describe a less complex conflict detection and resolution mechanism (at the home agent) without any performance degradation in form of bandwidth or latency compared to prior art solutions.Embodiments of the invention describe a home agent that may receive request messages, e.g., data ownership request messages and data request messages, which include issuance data indicating an order of the respective message issued. Said home agent may determine whether an early or late conflict exists based, at least in part, on a received conflict response message and the issuance data of a most recent completed transaction.
摘要翻译：本发明的实施例描述了高速缓存一致性协议，其消除了在消息类之间排序的需要，并且还消除了家庭跟踪器预分配。与现有技术的解决方案相比，本发明的实施例描述了一种不太复杂的冲突检测和解决机制（在归属代理），与带宽或延迟形式没有任何性能下降。本发明的实施例描述了可以接收诸如数据所有权请求消息和数据请求消息的请求消息的归属代理，其包括指示所发出的各个消息的顺序的发布数据。所述归属代理可以至少部分地基于接收到的冲突响应消息和最近完成的交易的发行数据来确定是否存在早期或晚期冲突。

58. 发明申请

US20140115420A1 HIGH PERFORMANCE INTERCONNECT LINK LAYER 有权
标题翻译：高性能互连链路层
公开(公告)号：US20140115420A1
公开(公告)日：2014-04-24
申请号：US13976947
申请日：2013-03-28
申请人： Jeff Willey , Robert G. Blankenship , Jeffrey C. Swanson , Robert J. Safranek
发明人： Jeff Willey , Robert G. Blankenship , Jeffrey C. Swanson , Robert J. Safranek
IPC分类号： H03M13/09
CPC分类号： G06F11/1004 , G06F13/4221 , G06F13/4282 , G06F2213/0026 , H03M13/09 , H04L12/4641
摘要： Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.
摘要翻译：识别事务数据，并且生成飞行以包括三个或更多个时隙和要用作两个或更多个时隙中的任何一个的扩展的浮动字段。在另一个方面，该方案包括要使用基于有效载荷生成的16位CRC值来编码的两个或更多个时隙，有效载荷和循环冗余校验（CRC）字段。至少部分地基于三个或更多个时隙，将闪存通过串行数据链路发送到用于处理的设备。

59. 发明申请

US20140112339A1 HIGH PERFORMANCE INTERCONNECT 有权
标题翻译：高性能互连
公开(公告)号：US20140112339A1
公开(公告)日：2014-04-24
申请号：US14060191
申请日：2013-10-22
申请人： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul C. Shah , Sitaraman V. Iyer , Bill Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
发明人： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul C. Shah , Sitaraman V. Iyer , Bill Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC分类号： H04L12/741
CPC分类号： G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/73 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4282 , G06F13/4286 , G06F13/4291 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L9/0662 , H04L12/4641 , H04L45/74 , H04L49/15 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/40 , Y02D10/44 , Y02D30/30
摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state
摘要翻译：物理层（PHY）耦合到将包括多个通道的串行差分链路。 PHY包括发射机和接收机，以耦合到车道数量的每个车道。耦合到每个通道的发射机被配置为将时钟嵌入到要在该通道上发送的数据，并且PHY周期性地发出阻塞链路状态（BLS）请求，以使代理进入BLS以阻止链路层飞行传输，持续时间 PHY在从包括带内复位，进入低功率状态的进入和进入部分宽度状态的组中选择的PHY相关联任务的持续时间期间利用串行差分链路

60. 发明授权

US07996572B2 Multi-node chipset lock flow with peer-to-peer non-posted I/O requests 有权
标题翻译：具有点对点非贴片I / O请求的多节点芯片组锁定流
公开(公告)号：US07996572B2
公开(公告)日：2011-08-09
申请号：US10859891
申请日：2004-06-02
申请人： Robert G. Blankenship , Robert J. Greiner , Herbert H. J. Hum , Kenneth C. Creta , Buderya S. Acharya
发明人： Robert G. Blankenship , Robert J. Greiner , Herbert H. J. Hum , Kenneth C. Creta , Buderya S. Acharya
IPC分类号： G06F3/00 , G06F7/38
CPC分类号： G06F13/387 , G06Q10/087
摘要： Systems and methods of managing transactions provide for receiving a first flush command at a first I/O hub, wherein the first flush command is dedicated to non-posted transactions. One embodiment further provides for halting an inbound ordering queue of the first I/O hub with regard to non-posted transactions in response to the first flush command and flushing a non-posted transaction from an outgoing buffer of the first I/O hub to a second I/O hub while the inbound ordering queue is halted with regard to non-posted transactions.
摘要翻译：管理事务的系统和方法提供在第一I / O集线器处接收第一冲洗命令，其中第一冲洗命令专用于未发布的事务。一个实施例进一步提供响应于第一冲洗命令而停止关于非发布的事务的第一I / O集线器的入站订购队列，并将未发布的事务从第一I / O集线器的输出缓冲器刷新到第二个I / O中枢，而对于未发布的事务，入站订购队列被停止。

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