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51. 发明授权

US07479994B2 Image sensor having resolution adjustment employing an analog column averaging/row averaging for high intensity light or row binning for low intensity light 有权
标题翻译：具有分辨率调整的图像传感器，采用模拟列平均/行平均用于低强度光的高强度光或行合并
公开(公告)号：US07479994B2
公开(公告)日：2009-01-20
申请号：US10999875
申请日：2004-11-30
申请人： Guang Yang , Taner Dosluoglu
发明人： Guang Yang , Taner Dosluoglu
IPC分类号： H04N5/217 , H04N3/14 , H04N5/335
CPC分类号： H04N9/045 , H04N5/347
摘要： A photo-sensor image resolution adjustment apparatus is in communication with an array of image photo-sensors that are organized in columns and rows and have multiple sensor types arranged in a pattern such as a Bayer pattern to detect light. The photo-sensor image resolution adjustment apparatus has a photo-sensor array decimation circuit to partition the array of image photo-sensors into a plurality of sub-groups. A column averaging circuit averages the light conversion electrical signals from common color photo-sensors within the sub-groups. A row averaging circuit averages the common color adjacent light conversion electrical signals from color adjacent rows within the sub-groups in high light intensity condition. In low light conditions, a row binning circuit integrates the common color adjacent light conversion electrical signals from color adjacent rows within the sub-groups.
摘要翻译：光传感器图像分辨率调节装置与以列和行组织的图像光传感器阵列通信，并且具有以诸如Bayer图案的图案排列以检测光的多个传感器类型。光传感器图像分辨率调节装置具有光传感器阵列抽取电路，以将图像光传感器阵列分割成多个子组。列平均电路对子组内常用彩色光电传感器的光转换电信号进行平均。行平均电路在高光强度条件下对来自子组内的颜色相邻行的相邻光转换电信号的常用颜色进行平均。在低光条件下，行分组电路将来自子组内的颜色相邻行的相邻光转换电信号的公共颜色相集成。

52. 发明申请

US20080129841A1 High performance imager IC with minimum peripheral circuits 有权
标题翻译：具有最小外设电路的高性能成像IC
公开(公告)号：US20080129841A1
公开(公告)日：2008-06-05
申请号：US11998960
申请日：2007-12-03
申请人： Taner Dosluoglu , Guang Yang , Peter Bartkovjak
发明人： Taner Dosluoglu , Guang Yang , Peter Bartkovjak
IPC分类号： H04N5/76 , H04N5/335
CPC分类号： H04N5/335
摘要： An imaging system provides a serial video signal that is indicative of the intensity of the light. The imaging system has an array of pixel image sensors arranged in rows and columns. A control circuit is in communication with the rows of the array and the plurality of column switches. The control circuit generates reset control signals, transfer gating signals, pixel image sensor initiation signals for each selected row for controlling resetting, integration of photoelectrons generated from the light impinging upon the array of pixel image sensors, charge transfer of the photoelectrons from the photosensing devices to the charge storage device, and to activate the photoelectron sensing devices on each row to generate output signals from each of the pixel image sensors on a selected row. The control circuit generates the column selection signals for transfer of the output signals from selected rows to form a serial video output signal.
摘要翻译：成像系统提供指示光强度的串行视频信号。成像系统具有以行和列排列的像素图像传感器阵列。控制电路与阵列的行和多个列开关连通。控制电路产生复位控制信号，传送门控信号，用于每个选定行的像素图像传感器起始信号，用于控制复位，从入射到像素图像传感器阵列上的光产生的光电子的积分，光电子从光敏器件的电荷转移并且激活每行上的光电子感测装置，以产生来自所选行上的每个像素图像传感器的输出信号。控制电路产生列选择信号，用于传送来自所选行的输出信号以形成串行视频输出信号。

53. 发明授权

US07247898B2 Self adjusting transfer gate APS 有权
标题翻译：自调节传输门APS
公开(公告)号：US07247898B2
公开(公告)日：2007-07-24
申请号：US11028772
申请日：2005-01-04
申请人： Taner Dosluoglu
发明人： Taner Dosluoglu
IPC分类号： H01L29/76
CPC分类号： H01L27/14632 , H01L27/14603 , H01L27/14609 , H01L27/14643 , H01L27/14654 , H01L31/112
摘要： An active pixel sensor circuit comprising a photodiode, a storage node, and a transfer gate between the photodiode and storage node, where the potential barrier between the photodiode and the storage region is maintained during charge accumulation, thereby preventing charge tunneling between the photodiode and the storage region. This is achieved by electrically connecting the transfer gate, which controls charge transfer between the photodiode and the storage region, to the storage region. Connecting the transfer gate to the storage region maintains the potential barrier between the photodiode and the storage region at a threshold voltage during the charge integration period which prevents charge tunneling between the photodiode and the storage node. The threshold voltage is determined by the implant levels used to form the active pixel sensor and can be optimized by using optimum implant levels. This prevention of charge tunneling between the photodiode and the storage node eliminates image lag.
摘要翻译：一种有源像素传感器电路，包括在光电二极管和存储节点之间的光电二极管，存储节点和传输门，其中在电荷累积期间保持光电二极管和存储区之间的势垒，由此防止光电二极管和存储区域。这通过将控制光电二极管和存储区域之间的电荷转移的传输门电连接到存储区域来实现。将传输栅极连接到存储区域在电荷积分期间在阈值电压下保持光电二极管和存储区域之间的势垒，从而防止光电二极管和存储节点之间的电荷隧穿。阈值电压由用于形成有源像素传感器的注入电平确定，并且可以通过使用最佳植入电平进行优化。这种防止光电二极管和存储节点之间的电荷隧道的消除消除了图像滞后。

54. 发明申请

US20060278905A1 CMOS pixel with dual gate PMOS 有权
标题翻译：具有双栅极PMOS的CMOS像素
公开(公告)号：US20060278905A1
公开(公告)日：2006-12-14
申请号：US11508354
申请日：2006-08-23
申请人： Taner Dosluoglu , Nathaniel McCaffrey
发明人： Taner Dosluoglu , Nathaniel McCaffrey
IPC分类号： H01L31/113
CPC分类号： H01L27/14609 , H01L27/14632 , H01L27/14643 , H01L31/112
摘要： A pixel circuit with a dual gate PMOS is formed by forming two P+ regions in an N− well. The N− well is in a P+ type substrate. The two P+ regions form the source and drain of a PMOS transistor. The PMOS transistors formed within the N− well will not affect the collection of the photo-generated charge as long as the source and drain potentials of the PMOS transistors are set at a lower potential than the N− well potential so that they remain reverse biased with respect to the N− well. One of the P+ regions used to form the source and drain regions can be used to reset the pixel after it has been read in preparation for the next cycle of accumulating photo-generated charge. The N− well forms a second gate for the dual gate PMOS transistor since the potential of the N− well 12 affects the conductivity of the channel of the PMOS transistor. The addition of two NMOS transistors enables the readout signal to be stored at the gate of one of the NMOS transistors thereby making a snapshot imager possible. The circuit can be expanded to form two PMOS transistors sharing a common drain in the N− well.
摘要翻译：具有双栅极PMOS的像素电路通过在N阱中形成两个P + +区形成。 N＆lt;＆gt;井是在P + +型衬底中。两个P + SUP区域形成PMOS晶体管的源极和漏极。形成在N阱内的PMOS晶体管不会影响光电荷的收集，只要PMOS晶体管的源极和漏极电位被设置在比N - 阱电位，使得它们相对于N 阱保持反向偏置。用于形成源极和漏极区域的一个P + SUP区域可用于在读取该像素以准备下一个累积光电荷循环之后复位像素。由于NΩ阱12的电位影响PMOS晶体管的沟道的导电性，因此N阱构成了双栅极PMOS晶体管的第二栅极。添加两个NMOS晶体管使读出信号能够存储在NMOS晶体管之一的栅极处，从而使快照成像器成为可能。该电路可以扩展以形成在N阱中共享一个共同漏极的两个PMOS晶体管。

55. 发明申请

US20060076472A1 Single chip stereo imaging system with dual array design 审中-公开
标题翻译：单芯片立体成像系统采用双阵列设计
公开(公告)号：US20060076472A1
公开(公告)日：2006-04-13
申请号：US10966124
申请日：2004-10-15
申请人： Taner Dosluoglu , Jurgen Friedel
发明人： Taner Dosluoglu , Jurgen Friedel
IPC分类号： H01L27/00
CPC分类号： H04N13/239
摘要： A stereo imaging chip is presented that contains two imaging arrays located at opposite edges of the chip. Support circuitry, including a computational unit, is located on the chip in areas not occupied by the imaging arrays. A FPGA located on the chip is used to provide instructions to the computational unit and allow updates. A stereo focusing unit on a single optical substrate focuses a distant object onto the two imaging arrays. The semiconductor process producing the chip provides accurate alignment of the two imaging arrays and the use of a single optical substrate to containing the stereo lens provides additional dimensional accuracy and stability to allow calculations of the distance to distant objects.
摘要翻译：呈现立体成像芯片，其包含位于芯片相对边缘处的两个成像阵列。包括计算单元的支持电路位于芯片上未被成像阵列占据的区域中。位于芯片上的FPGA用于向计算单元提供指令并允许更新。单个光学基板上的立体聚焦单元将远距离物体聚焦到两个成像阵列上。制造芯片的半导体工艺提供两个成像阵列的精确对准，并且使用单个光学基底来容纳立体透镜提供额外的尺寸精度和稳定性，以允许计算到远处物体的距离。

56. 发明授权

US06984812B2 Auto registered component RGB imaging method 失效
标题翻译：自动注册分量RGB成像方法
公开(公告)号：US06984812B2
公开(公告)日：2006-01-10
申请号：US10647719
申请日：2003-08-25
申请人： Nathaniel Joseph McCaffrey , Taner Dosluoglu
发明人： Nathaniel Joseph McCaffrey , Taner Dosluoglu
IPC分类号： H01L27/00
CPC分类号： H04N9/045 , H04N9/093 , H04N9/097 , H04N2209/045
摘要： A new electronic imaging system is achieved. The system comprises a sensor having a first color region, a second color region, and a third color region. A prism system comprises a first prism having a first index of refraction and overlying the first color region. The first prism directs incident light of the first color to the first color region of the sensor. A second prism has a second index of refraction and overlies the second color region. The second prism directs incident light of the second color to the second color region of the sensor. A third prism has a third index of refraction and overlies the third color region. The third prism directs incident light of the third color to the third color region of the sensor.
摘要翻译：实现了新的电子成像系统。该系统包括具有第一颜色区域，第二颜色区域和第三颜色区域的传感器。棱镜系统包括具有第一折射率并且覆盖第一颜色区域的第一棱镜。第一棱镜将第一颜色的入射光引导到传感器的第一颜色区域。第二棱镜具有第二折射率并且覆盖在第二颜色区域上。第二棱镜将第二颜色的入射光引导到传感器的第二颜色区域。第三棱镜具有第三折射率并且覆盖第三颜色区域。第三棱镜将第三颜色的入射光引导到传感器的第三颜色区域。

57. 发明授权

US06897519B1 Tunneling floating gate APS pixel 有权
标题翻译：隧道浮动APS像素
公开(公告)号：US06897519B1
公开(公告)日：2005-05-24
申请号：US10627796
申请日：2003-07-25
申请人： Taner Dosluoglu
发明人： Taner Dosluoglu
IPC分类号： H01L27/146 , H01L29/788 , H01L31/06 , H01L31/112
CPC分类号： H01L27/14603 , H01L27/14643 , H01L31/112
摘要： A floating gate pixel is described which is formed by forming an N well in a P type silicon substrate. A P well is formed in the N well A gate is formed over a thin gate oxide, about 25 Angstroms thickness, such that the gate is directly over part of the P well and part of the N well. A P+ contact in the P well allows connection to a reset voltage source, usually through a reset transistor, to reset the pixel. The pixel is reset by setting the potential between the P well and the substrate, which is usually held at ground potential. When the pixel is reset tunneling current through the thin gate oxide sets the voltage of the floating gate. During the charge integration cycle an input signal to the pixel, such as a light signal, changes the potential of the pixel. After the charge integration cycle the tunneling current through the gate oxide changes the potential of the floating gate by an amount related to the input signal to the pixel. The potential of the floating gate can then be read out to determine the input signal to the pixel. The pixel can also be embodied using a P well formed in an N type substrate, an N well formed in the P well, and an N+ contact formed in the N well.
摘要翻译：描述了通过在P型硅衬底中形成N阱形成的浮动栅极像素。在N阱中形成P阱A栅极形成在厚度约25埃的薄栅极氧化物上，使得栅极直接位于P阱的一部分和N阱的一部分上。 P阱中的P + SUPER接触允许连接到复位电压源，通常通过复位晶体管来复位像素。通过设置P阱和衬底之间的电位来复位像素，通常保持在地电位。当像素复位时，隧穿电流通过薄栅氧化层设置浮栅的电压。在电荷积分周期期间，诸如光信号的像素的输入信号改变像素的电位。在电荷积分周期之后，通过栅极氧化物的隧道电流将浮动栅极的电位改变与到像素的输入信号相关的量。然后可以读出浮动栅极的电位以确定到像素的输入信号。也可以使用在N型衬底中形成的P阱，在P阱中形成的N阱以及在N阱中形成的N + H接触来实现像素。

58. 发明授权

US06870209B2 CMOS pixel with dual gate PMOS 有权
标题翻译：具有双栅极PMOS的CMOS像素
公开(公告)号：US06870209B2
公开(公告)日：2005-03-22
申请号：US10339190
申请日：2003-01-09
申请人： Taner Dosluoglu , Nathaniel Joseph McCaffrey
发明人： Taner Dosluoglu , Nathaniel Joseph McCaffrey
IPC分类号： H01L21/8238 , H01L27/092 , H01L27/146 , H01L29/10 , H01L29/76 , H01L31/036 , H01L31/10 , H01L31/112 , H01L31/113
CPC分类号： H01L27/14609 , H01L27/14632 , H01L27/14643 , H01L31/112
摘要： A pixel circuit with a dual gate PMOS is formed by forming two P+ regions in an N− well. The N− well is in a P− type substrate. The two P+ regions form the source and drain of a PMOS transistor. The PMOS transistors formed within the N− well will not affect the collection of the photo-generated charge as long as the source and drain potentials of the PMOS transistors are set at a lower potential than the N− well potential so that they remain reverse biased with respect to the N− well. One of the P+ regions used to form the source and drain regions can be used to reset the pixel after it has been read in preparation for the next cycle of accumulating photo-generated charge. The N− well forms a second gate for the dual gate PMOS transistor since the potential of the N− well 12 affects the conductivity of the channel of the PMOS transistor. The addition of two NMOS transistors enables the readout signal to be stored at the gate of one of the NMOS transistors thereby making a snapshot imager possible. The circuit can be expanded to form two PMOS transistors sharing a common drain in the N− well.
摘要翻译：具有双栅极PMOS的像素电路通过在N阱中形成两个P +区而形成。 N型阱在P型衬底中。两个P +区形成PMOS晶体管的源极和漏极。形成在N阱中的PMOS晶体管不会影响光电荷的收集，只要PMOS晶体管的源极和漏极电位被设置在比N阱阱电势更低的电位，使得它们相对于N - 阱保持反向偏置。用于形成源极和漏极区域的一个P +区域可用于在读取像素以准备下一个积累光电荷的周期之后复位像素。由于N“阱12的电位影响PMOS晶体管的沟道的导电性，所以N”阱形成双栅极PMOS晶体管的第二栅极。添加两个NMOS晶体管使读出信号能够存储在NMOS晶体管之一的栅极处，从而使快照成像器成为可能。该电路可以扩展以形成在N阱中共享公共漏极的两个PMOS晶体管。

59. 发明申请

US20190393771A1 VOLTAGE CONTROLLED CURRENT INPUT AND TRANSIMPEDANCE REGULATOR 审中-公开
公开(公告)号：US20190393771A1
公开(公告)日：2019-12-26
申请号：US16451534
申请日：2019-06-25
申请人： Mykhaylo Teplechuk , Taner Dosluoglu
发明人： Mykhaylo Teplechuk , Taner Dosluoglu
IPC分类号： H02M1/088 , H02M3/158
摘要： A transimpedance regulator may include a switched capacitor converter, with a current input and a regulated voltage output. A DC-DC switching converter with an inductive component may be used as a current source for the switched capacitor converter. In some embodiments the DC-DC switching converter with an inductive component may be operated in a manner expected to provide optimum power efficiency, with the switching capacitor converter providing a desired regulated voltage output.

60. 发明授权

US09515553B2 Transient power control 有权
标题翻译：瞬态功率控制
公开(公告)号：US09515553B2
公开(公告)日：2016-12-06
申请号：US14602112
申请日：2015-01-21
申请人： Taner Dosluoglu , Hassan Ihs
发明人： Taner Dosluoglu , Hassan Ihs
IPC分类号： H02M3/158 , H02M1/36 , H02M3/156
CPC分类号： H02M3/158 , H02M1/32 , H02M1/36 , H02M2003/1566
摘要： Automatic transient control circuitry may be used to alleviate issues relating to large changes in power demands by a load in an integrated circuit. The transient control circuitry may inject current to or retract current from a load, for example charging or discharging a bypass capacitor associated with the load, when circuitry of the load is commanded to an operational state from a standby state or vice-versa, respectively.
摘要翻译：自动瞬态控制电路可用于减轻与集成电路中的负载对功率需求的巨大变化有关的问题。当负载的电路分别从待机状态或反之亦然地命令到操作状态时，瞬态控制电路可以将电流从负载注入或退出电流，例如充电或放电与负载相关联的旁路电容器。

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