专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US08904153B2 Vector loads with multiple vector elements from a same cache line in a scattered load operation 有权
标题翻译：在分散加载操作中，来自相同高速缓存行的多个向量元素的向量加载
公开(公告)号：US08904153B2
公开(公告)日：2014-12-02
申请号：US12876321
申请日：2010-09-07
申请人： Alexandre E. Eichenberger , Michael K. Gschwind , Valentina Salapura
发明人： Alexandre E. Eichenberger , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/345 , G06F9/30 , G06F9/38 , G06F15/80
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/3857 , G06F15/8069
摘要： Mechanisms for performing a scattered load operation are provided. With these mechanisms, an extended address is received in a cache memory of a processor. The extended address has a plurality of data element address portions that specify a plurality of data elements to be accessed using the single extended address. Each of the plurality of data element address portions is provided to corresponding data element selector logic units of the cache memory. Each data element selector logic unit in the cache memory selects a corresponding data element from a cache line buffer based on a corresponding data element address portion provided to the data element selector logic unit. Each data element selector logic unit outputs the corresponding data element for use by the processor.
摘要翻译：提供了执行分散加载操作的机构。利用这些机制，扩展地址被接收在处理器的高速缓冲存储器中。扩展地址具有多个数据元素地址部分，其指定使用单个扩展地址来访问的多个数据元素。多个数据元素地址部分中的每一个被提供给高速缓冲存储器的相应数据元素选择器逻辑单元。高速缓冲存储器中的每个数据元素选择器逻辑单元基于提供给数据元素选择器逻辑单元的相应数据元素地址部分从高速缓存行缓冲器中选择相应的数据元素。每个数据元素选择器逻辑单元输出相应的数据元素供处理器使用。

52. 发明授权

US08811422B2 Single chip protocol converter 有权
标题翻译：单芯片协议转换器
公开(公告)号：US08811422B2
公开(公告)日：2014-08-19
申请号：US13269065
申请日：2011-10-07
申请人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
发明人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
IPC分类号： H04J3/16 , G06F15/167 , H04L12/56 , G06F15/78
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译：一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行在单一集成电路芯片内。单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。

53. 发明授权

US08782164B2 Implementing asyncronous collective operations in a multi-node processing system 有权
标题翻译：在多节点处理系统中实现异步集体操作
公开(公告)号：US08782164B2
公开(公告)日：2014-07-15
申请号：US12697043
申请日：2010-01-29
申请人： Dong Chen , Noel A. Eisley , Philp Heidelberger , Sameer Kumar , Valentina Salapura , Burkhard Steinmacher-Burow
发明人： Dong Chen , Noel A. Eisley , Philp Heidelberger , Sameer Kumar , Valentina Salapura , Burkhard Steinmacher-Burow
IPC分类号： G06F15/16 , G06F12/00
CPC分类号： G06F15/16
摘要： A method, system, and computer program product are disclosed for implementing an asynchronous collective operation in a multi-node data processing system. In one embodiment, the method comprises sending data to a plurality of nodes in the data processing system, broadcasting a remote get to the plurality of nodes, and using this remote get to implement asynchronous collective operations on the data by the plurality of nodes. In one embodiment, each of the nodes performs only one task in the asynchronous operations, and each nodes sets up a base address table with an entry for a base address of a memory buffer associated with said each node. In another embodiment, each of the nodes performs a plurality of tasks in said collective operations, and each task of each node sets up a base address table with an entry for a base address of a memory buffer associated with the task.
摘要翻译：公开了一种在多节点数据处理系统中实现异步集体操作的方法，系统和计算机程序产品。在一个实施例中，该方法包括向数据处理系统中的多个节点发送数据，向多个节点广播远程获取，并且使用该远程获取来对多个节点对数据执行异步集合操作。在一个实施例中，每个节点在异步操作中仅执行一个任务，并且每个节点建立具有与所述每个节点相关联的存储器缓冲器的基地址的条目的基地址表。在另一实施例中，每个节点在所述集体操作中执行多个任务，并且每个节点的每个任务用与用于与任务相关联的存储器缓冲器的基地址的条目建立基地址表。

54. 发明申请

US20130262821A1 PERFORMING PREDECODE-TIME OPTIMIZED INSTRUCTIONS IN CONJUNCTION WITH PREDECODE TIME OPTIMIZED INSTRUCTION SEQUENCE CACHING 有权
标题翻译：与预定时间优化的指令序列缓存执行预定时间优化的指令
公开(公告)号：US20130262821A1
公开(公告)日：2013-10-03
申请号：US13432357
申请日：2012-03-28
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/382 , G06F9/3017 , G06F9/3808 , G06F9/384
摘要： A method for performing predecode-time optimized instructions in conjunction with predecode time optimized instruction sequence caching. The method includes receiving a first instruction of an instruction sequence and a second instruction of the instruction sequence and determining if the first instruction and the second instruction can be optimized. In response to the determining that the first instruction and second instruction can be optimized, the method includes, preforming a pre-decode optimization on the instruction sequence and generating a new second instruction, wherein the new second instruction is not dependent on a target operand of the first instruction and storing a pre-decoded first instruction and a pre-decoded new second instruction in an instruction cache. In response to determining that the first instruction and second instruction can not be optimized, the method includes, storing the pre-decoded first instruction and a pre-decoded second instruction in the instruction cache.
摘要翻译：一种执行预解码时间优化指令并结合预解码时间优化指令序列缓存的方法。该方法包括接收指令序列的第一指令和指令序列的第二指令，并且确定是否可以优化第一指令和第二指令。响应于确定可以优化第一指令和第二指令，该方法包括：对指令序列执行预解码优化并产生新的第二指令，其中新的第二指令不依赖于目标操作数所述第一指令并将预解码的第一指令和预解码的新的第二指令存储在指令高速缓存中。响应于确定第一指令和第二指令不能被优化，该方法包括：将预解码的第一指令和预解码的第二指令存储在指令高速缓存中。

55. 发明申请

US20130212139A1 MIXED PRECISION ESTIMATE INSTRUCTION COMPUTING NARROW PRECISION RESULT FOR WIDE PRECISION INPUTS 有权
标题翻译：混合精度估计指标计算精度高精度结果进行精确输入
公开(公告)号：US20130212139A1
公开(公告)日：2013-08-15
申请号：US13369470
申请日：2012-02-09
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F7/483 , G06F7/499 , G06F17/10
CPC分类号： G06F7/483 , G06F7/499 , G06F7/49905
摘要： A technique is provided for performing a mixed precision estimate. A processing circuit receives an input of a first precision having a wide precision value. The processing circuit computes an output in an output exponent range corresponding to a narrow precision value based on the input having the wide precision value.
摘要翻译：提供了一种用于执行混合精度估计的技术。处理电路接收具有宽精度值的第一精度的输入。处理电路基于宽精度值的输入，计算与窄精度值对应的输出指数范围内的输出。

56. 发明申请

US20130086362A1 Managing a Register Cache Based on an Architected Computer Instruction Set Having Operand First-Use Information 有权
标题翻译：基于具有操作数首次使用信息的建筑计算机指令集管理寄存器缓存
公开(公告)号：US20130086362A1
公开(公告)日：2013-04-04
申请号：US13251426
申请日：2011-10-03
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/312
CPC分类号： G06F9/30145 , G06F9/30 , G06F9/30185 , G06F9/34 , G06F9/3826 , G06F9/384
摘要： A prefix instruction is executed and passes operands to a net instruction without storing the operands in an architected resource such that the execution of the next instruction uses the operands provided by the prefix instruction to perform an operation, the operands may be prefix instruction immediate field or a target register of the prefix instruction execution.
摘要翻译：执行前缀指令并将操作数传递到网络指令而不将操作数存储在架构资源中，使得下一条指令的执行使用由前缀指令提供的操作数来执行操作，操作数可以是前缀指令立即字段或前缀指令执行的目标寄存器。

57. 发明申请

US20130073836A1 FINE-GRAINED INSTRUCTION ENABLEMENT AT SUB-FUNCTION GRANULARITY 有权
公开(公告)号：US20130073836A1
公开(公告)日：2013-03-21
申请号：US13234785
申请日：2011-09-16
申请人： Michael K. Gschwind , Brett Olsson , Valentina Salapura
发明人： Michael K. Gschwind , Brett Olsson , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/302
CPC分类号： G06F9/3013 , G06F9/30025 , G06F9/30036 , G06F9/30098 , G06F9/30105 , G06F9/30112 , G06F9/3012 , G06F9/3016 , G06F9/30189
摘要： Fine-grained enablement at sub-function granularity. An instruction encapsulates different sub-functions of a function, in which the sub-functions use different sets of registers of a composite register file, and therefore, different sets of functional units. At least one operand of the instruction specifies which set of registers, and therefore, which set of functional units, is to be used in performing the sub-function. The instruction can perform various functions (e.g., move, load, etc.) and a sub-function of the function specifies the type of function (e.g., move-floating point; move-vector; etc.).

58. 发明授权

US08255638B2 Snoop filter for filtering snoop requests 失效
标题翻译：用于过滤窥探请求的Snoop过滤器
公开(公告)号：US08255638B2
公开(公告)日：2012-08-28
申请号：US12113262
申请日：2008-05-01
申请人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk I. Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos M. Vranas
发明人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk I. Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos M. Vranas
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0822 , G06F12/0831 , G06F2212/507 , Y02D10/13
摘要： A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter device associated with each processing unit, each snoop filter device having a plurality of dedicated input ports for receiving snoop requests from dedicated memory writing sources in the multiprocessor computing environment. Each snoop filter device includes a plurality of parallel operating port snoop filters in correspondence with the plurality of dedicated input ports, each port snoop filter implementing one or more parallel operating sub-filter elements that are adapted to concurrently filter snoop requests received from respective dedicated memory writing sources and forward a subset of those requests to its associated processing unit.
摘要翻译：一种用于在具有多个处理单元的多处理器计算环境中支持高速缓存一致性的方法和装置，每个处理单元具有与其相关联并与之可操作地相连的一个或多个本地高速缓冲存储器。该方法包括提供与每个处理单元相关联的窥探过滤器设备，每个窥探过滤器设备具有多个专用输入端口，用于从多处理器计算环境中的专用存储器写入源接收窥探请求。每个窥探过滤器装置包括与多个专用输入端口相对应的多个并行操作端口窥探滤波器，每个端口窥探滤波器实现一个或多个并行操作子滤波器元件，其适于同时滤除从相应专用存储器接收的窥探请求写入源并将这些请求的子集转发到其相关联的处理单元。

59. 发明授权

US08230433B2 Shared performance monitor in a multiprocessor system 失效
标题翻译：多处理器系统中的共享性能监视器
公开(公告)号：US08230433B2
公开(公告)日：2012-07-24
申请号：US11768777
申请日：2007-06-26
申请人： George Chiu , Alan G. Gara , Valentina Salapura
发明人： George Chiu , Alan G. Gara , Valentina Salapura
IPC分类号： G06F9/46 , G06F11/00 , G06F9/00
CPC分类号： G06F11/348 , G06F11/3409 , G06F2201/86 , G06F2201/88 , Y02D10/34
摘要： A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU comprises: a plurality of performance counters each for counting signals representing occurrences of events from one or more the plurality of processor units in the multiprocessor system; and, a plurality of input devices for receiving the event signals from one or more processor devices of the plurality of processor units, the plurality of input devices programmable to select event signals for receipt by one or more of the plurality of performance counters for counting, wherein the PMU is shared between multiple processing units, or within a group of processors in the multiprocessing system. The PMU is further programmed to monitor event signals issued from non-processor devices.
摘要翻译：用于监视在多处理器系统中发生的事件的性能的性能监视单元（PMU）和方法。多处理器系统包括多个处理器设备单元，用于产生表示处理器设备中事件发生的信号的每个处理器设备，以及用于性能监控的单个共享计数器资源。性能监视器单元由多处理器系统中的所有处理器核共享。 PMU包括：多个性能计数器，每个用于对表示来自多处理器系统中的一个或多个处理器单元的事件进行计数的信号; 以及多个输入装置，用于从所述多个处理器单元中的一个或多个处理器装置接收事件信号，所述多个输入装置可编程以选择事件信号以供所述多个性能计数器中的一个或多个用于计数，其中PMU在多处理单元之间或多处理系统中的一组处理器内共享。 PMU进一步被编程为监视从非处理器设备发出的事件信号。

60. 发明申请

US20120082171A1 SINGLE CHIP PROTOCOL CONVERTER 有权
标题翻译：单芯片协议转换器
公开(公告)号：US20120082171A1
公开(公告)日：2012-04-05
申请号：US13269065
申请日：2011-10-07
申请人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
发明人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
IPC分类号： H04L12/00
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译：一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行在单一集成电路芯片内。单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式