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51. 发明授权

US08605485B2 Non-volatile semiconductor storage device and forming method 有权
标题翻译：非易失性半导体存储器件及其形成方法
公开(公告)号：US08605485B2
公开(公告)日：2013-12-10
申请号：US13350067
申请日：2012-01-13
申请人： Hiroshi Kanno , Takafumi Shimotori , Yoichi Minemura , Takahiko Sasaki , Takayuki Tsukamoto
发明人： Hiroshi Kanno , Takafumi Shimotori , Yoichi Minemura , Takahiko Sasaki , Takayuki Tsukamoto
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C13/0028 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0083
摘要： According to one embodiment, a control unit multiple-selects a first line for every N lines from a plurality of first lines. N is an integer greater than or equal to one. The control unit sets the multiple-selected first lines to a selection potential, and fixes potentials of non-selected first lines at least adjacent to the multiple-selected first lines at a first timing. The control unit causes the multiple-selected first lines to be in a floating state at a second timing after the first timing. The control unit selects one second line from the plurality of second lines and sets the one second line to a forming potential at a third timing after the second timing.
摘要翻译：根据一个实施例，控制单元从多条第一行为每N条线选择第一行。 N是大于或等于1的整数。控制单元将多个选择的第一行设置为选择电位，并且在第一定时将至少与多个选择的第一行相邻的未选择的第一行的电位进行固定。控制单元使第一定时后的第二定时使多选第一行处于浮动状态。控制单元从多条第二行中选择一条第二行，并在第二定时之后的第三定时将一条第二行设置成一个形成电位。

52. 发明授权

US08576606B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08576606B2
公开(公告)日：2013-11-05
申请号：US13052214
申请日：2011-03-21
申请人： Tetsuji Kunitake , Takashi Shigeoka , Takayuki Tsukamoto , Hironori Wakai , Hisashi Kato
发明人： Tetsuji Kunitake , Takashi Shigeoka , Takayuki Tsukamoto , Hironori Wakai , Hisashi Kato
IPC分类号： G11C11/00
CPC分类号： H01L27/24 , G11C8/08 , G11C13/0007 , G11C13/0023 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , H01L27/1021
摘要： A nonvolatile semiconductor memory device according to an embodiment herein includes a memory cell array. The memory cell array includes memory cells each provided between a first line and a second line and each including a variable resistor. A control circuit applies through the first and second lines a voltage necessary for a forming operation of the memory cell. A current limiting circuit limits a value of a current flowing across the memory cell during the forming operation to a certain limit value. The control circuit repeats an operation of applying the voltage by setting the limit value to a certain value and an operation of changing the limit value from the certain value, until forming of the memory cell is achieved.
摘要翻译：根据本文实施例的非易失性半导体存储器件包括存储单元阵列。存储单元阵列包括各自设置在第一线路和第二线路之间并且各自包括可变电阻器的存储器单元。控制电路通过第一和第二行施加存储单元的形成操作所需的电压。电流限制电路将在成形操作期间流过存储器单元的电流的值限制到某一极限值。控制电路重复通过将极限值设定为一定值来施加电压的操作和从该特定值改变极限值的操作，直到实现存储单元的形成。

53. 发明授权

US08319611B2 Radio frequency indentification tag 有权
标题翻译：射频识别标签
公开(公告)号：US08319611B2
公开(公告)日：2012-11-27
申请号：US12244842
申请日：2008-10-03
申请人： Takayuki Tsukamoto , Mutsuya Motojima
发明人： Takayuki Tsukamoto , Mutsuya Motojima
IPC分类号： H04Q5/22
CPC分类号： H04B5/02 , G06K19/0713 , G06K19/0723 , H04B5/0031 , H04B5/0037 , H04B5/0062 , H04Q2213/13095 , Y02D70/166
摘要： An ID tag has a stable internal supply voltage and extends the range of communication with the reader/writer during back scattering communication. An ASK-modulated signal pre-boost circuit to which antenna terminals are coupled is coupled in parallel with a rectifying circuit. In the ASK-modulated signal pre-boost circuit, a switch for back scattering, working as a modulator element, is provided. During back scattering communication, when a back scattering signal “1” is transmitted, only the current flowing in the signal receiving path of the modulation/demodulation unit is wasted by turning the switch for back scattering on. Additional current loss other than the loss for impedance matching can be prevented.
摘要翻译： ID标签具有稳定的内部电源电压，并且在后向散射通信期间扩展与读取器/写入器的通信范围。天线端子耦合到的ASK调制信号预升压电路与整流电路并联耦合。在ASK调制信号预升压电路中，提供了用作后向散射的开关，用作调制器元件。在背散射通信中，当发送背散射信号1时，仅通过转动用于背散射的开关来浪费在调制/解调单元的信号接收路径中流动的电流。可以防止除了阻抗匹配损失之外的附加电流损耗。

54. 发明授权

US08085577B2 Nonvolatile semiconductor memory device and method of data write/data erase therein 有权
标题翻译：非易失性半导体存储器件及其中的数据写入/数据擦除方法
公开(公告)号：US08085577B2
公开(公告)日：2011-12-27
申请号：US12713667
申请日：2010-02-26
申请人： Hiroshi Kanno , Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka
发明人： Hiroshi Kanno , Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka
IPC分类号： G11C11/00
CPC分类号： G11C5/025 , G11C13/0007 , G11C13/003 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0073 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76
摘要： A nonvolatile semiconductor memory device comprises: a plurality of first lines; a plurality of second lines; a plurality of memory cells each disposed at each of crossing-points of the first lines and the second lines and each comprising a variable resistor and a bi-directional diode; and a voltage control circuit configured to control a voltage of selected one of the first lines, unselected ones of the first lines, selected one of the second lines, and unselected ones of the second lines, respectively. The variable resistor is configured to change its resistance value depending on a polarity of a voltage applied thereto. The voltage control circuit is configured to apply a voltage pulse to the selected one of the first lines and to connect a capacitor of a certain capacitance to one end of the selected one of the second lines.
摘要翻译：非易失性半导体存储器件包括：多条第一线; 多条第二线; 多个存储单元，每个存储单元分别设置在第一线和第二线的交叉点的每一个处，并且每个存储单元包括可变电阻器和双向二极管; 以及电压控制电路，被配置为分别控制所选择的第一行，未选择的第一行，所选择的第二行和未选择的第二行中的一个的电压。可变电阻器被配置为根据施加到其的电压的极性来改变其电阻值。电压控制电路被配置为向所选择的第一线中的一个施加电压脉冲，并且将一定电容的电容器连接到所选择的一条第二线路的一端。

55. 发明授权

US07995382B2 Information recording and reproducing apparatus 有权
标题翻译：信息记录和再现装置
公开(公告)号：US07995382B2
公开(公告)日：2011-08-09
申请号：US12636646
申请日：2009-12-11
申请人： Takayuki Tsukamoto , Kohichi Kubo , Chikayoshi Kamata , Takahiro Hirai , Shinya Aoki , Toshiro Hiraoka
发明人： Takayuki Tsukamoto , Kohichi Kubo , Chikayoshi Kamata , Takahiro Hirai , Shinya Aoki , Toshiro Hiraoka
IPC分类号： G11C11/00
CPC分类号： H01L45/147 , B82Y10/00 , G11B9/04 , G11B9/149 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C16/3427 , G11C2213/53 , G11C2213/75 , H01L27/101 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/126 , H01L45/1625
摘要： An information recording and reproducing apparatus, includes: a recording layer including a first layer including a first compound, the first compound being a conjugated compound including at least two types of cation elements, at least one selected from the cation elements being a transition element having a d orbit incompletely filled by electrons, a shortest distance between adjacent cation elements being not more than 0.32 nm; a voltage application unit that applies a voltage to the recording layer, produces a phase change in the recording layer, and records information; an electrode layer that applies a voltage to the recording layer; and an orientation control layer provided between the recording layer and the electrode layer to control an orientation of the recording layer.
摘要翻译：一种信息记录和再现装置，包括：记录层，包括第一层，第一层包括第一化合物，第一化合物是包含至少两种阳离子元素的共轭化合物，选自阳离子元素中的至少一种是具有 ad轨道不完全填充电子，相邻阳离子元素之间的最短距离不大于0.32nm; 向记录层施加电压的电压施加单元，在记录层中产生相变，记录信息; 向记录层施加电压的电极层; 以及设置在记录层和电极层之间的取向控制层，以控制记录层的取向。

56. 发明授权

US07948790B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07948790B2
公开(公告)日：2011-05-24
申请号：US12558058
申请日：2009-09-11
申请人： Takayuki Tsukamoto , Reika Ichihara
发明人： Takayuki Tsukamoto , Reika Ichihara
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C13/0064 , G11C13/0069 , G11C16/3413 , G11C16/3463 , G11C2013/009 , G11C2211/5642 , G11C2213/31 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A memory cell arranged between first and second wirings includes a variable-resistor element. A controller controls a voltage applied between the first and second wirings. The controller performs a first operation that applies a first voltage between the first and second wirings to switch the variable-resistor element from a first state with a resistance value not less than a first resistance value, to a second state with a resistance value not more than a second resistance value smaller than the first resistance value. The second operation applies a second voltage smaller than the first voltage between the first and second wirings to switch the variable-resistor element from the second state to the first state. In the first operation, a verify voltage is applied between the first and second wirings. Based on the obtained signal, a third voltage smaller than the first voltage is applied between the first and second wirings.
摘要翻译：布置在第一和第二布线之间的存储单元包括可变电阻器元件。控制器控制施加在第一和第二布线之间的电压。控制器执行第一操作，其在第一和第二布线之间施加第一电压，以将具有不小于第一电阻值的电阻值的第一状态的可变电阻元件切换到具有不大于电阻值的第二状态比第一电阻值小的第二电阻值。第二操作施加小于第一和第二布线之间的第一电压的第二电压，以将可变电阻元件从第二状态切换到第一状态。在第一操作中，在第一和第二布线之间施加验证电压。基于获得的信号，在第一和第二布线之间施加小于第一电压的第三电压。

57. 发明申请

US20110069532A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110069532A1
公开(公告)日：2011-03-24
申请号：US12876637
申请日：2010-09-07
申请人： Reika ICHIHARA , Takayuki Tsukamoto , Hiroshi Kanno , Kenichi Murooka
发明人： Reika ICHIHARA , Takayuki Tsukamoto , Hiroshi Kanno , Kenichi Murooka
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0097 , G11C2213/13 , G11C2213/34 , G11C2213/72
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of first wirings, a plurality of second wirings intersecting the plurality of first wirings, and a plurality of memory cells provided at the intersections of the plurality of first and second wirings and each including a non-ohmic element and a variable resistance element connected in series. The control circuit selects one of the plurality of memory cells, generates an erasing pulse for erasing data from the selected memory cell, and supplies the erasing pulse to the selected memory cell. The control circuit executes data erase by applying a voltage of the erasing pulse to the non-ohmic element in the reverse bias direction.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括存储单元阵列和控制电路。存储单元阵列包括多个第一布线，与多条第一布线相交的多条第二布线，以及多个存储单元，设置在多个第一布线和第二布线的交点处，每个包括非欧姆元件和串联连接的可变电阻元件。控制电路选择多个存储单元中的一个，产生用于从所选存储单元擦除数据的擦除脉冲，并将擦除脉冲提供给所选存储单元。控制电路通过在反向偏置方向上向非欧姆元件施加擦除脉冲的电压来执行数据擦除。

58. 发明申请

US20110032745A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110032745A1
公开(公告)日：2011-02-10
申请号：US12846198
申请日：2010-07-29
申请人： Reika ICHIHARA , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue , Hiroshi Kanno
发明人： Reika ICHIHARA , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue , Hiroshi Kanno
IPC分类号： G11C11/00
CPC分类号： G11C13/0061 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C13/0097 , G11C2013/0092
摘要： A non-volatile semiconductor memory device according to an aspect of embodiments of the present invention includes a memory cell array including: multiple first wirings; multiple second wirings crossing the multiple first wirings; and multiple electrically rewritable memory cells respectively arranged at intersections of the first wirings and the second wirings, and each formed of a variable resistor which stores a resistance value as data in a non-volatile manner. The non-volatile semiconductor memory device according to an aspect of the embodiments of the present invention further includes a controller for selecting a given one of the memory cells, generating an erase pulse which is used for erasing data, and supplying the erase pulse to the selected memory cell. The erase pulse has a pulse width which is increased or decreased exponentially in accordance with an access path length to the selected memory cell.
摘要翻译：根据本发明的实施例的非易失性半导体存储器件包括：存储单元阵列，包括：多个第一布线; 多个第二布线穿过多个第一布线; 以及分别布置在第一布线和第二布线的交点处的多个电可重写存储器单元，并且每个由可变电阻器形成，其以非易失性方式存储电阻值作为数据。根据本发明实施例的一个方面的非易失性半导体存储器件还包括用于选择给定的一个存储单元的控制器，产生用于擦除数据的擦除脉冲，并将擦除脉冲提供给选择的存储单元。擦除脉冲具有根据到所选存储单元的访问路径长度指数地增加或减少的脉冲宽度。

59. 发明申请

US20110026294A1 INFORMATION RECORDING AND REPRODUCING DEVICE 有权
标题翻译：信息记录和复制设备
公开(公告)号：US20110026294A1
公开(公告)日：2011-02-03
申请号：US12886040
申请日：2010-09-20
申请人： Takayuki Tsukamoto , Takeshi Yamaguchi , Chikayoshi Kamata , Tsukasa Nakai , Takahiro Hirai , Shinya Aoki , Kohichi Kubo
发明人： Takayuki Tsukamoto , Takeshi Yamaguchi , Chikayoshi Kamata , Tsukasa Nakai , Takahiro Hirai , Shinya Aoki , Kohichi Kubo
IPC分类号： G11C5/06 , H01L45/00
CPC分类号： G11B9/04 , B82Y10/00 , G11B9/149 , G11B11/002 , G11B11/08 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C16/0483 , G11C2211/565 , G11C2213/32 , G11C2213/56 , G11C2213/71 , G11C2213/72 , G11C2213/75 , G11C2213/78 , G11C2213/79 , H01L27/101 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/144 , H01L45/147 , H01L45/16 , H01L45/1675
摘要： According to one embodiment, an information recording and reproducing device includes a first layer, a second layer and a recording layer. The recording layer is provided between the first and second layers and is capable of reversibly transitioning between a first state and a second state with a resistance higher than in the first state. One of the first and second layers includes a resistivity distribution layer perpendicular to a stacking direction of the first and second layers, and the recording layer. The resistivity distribution layer includes a low and a high resistivity portion. Resistivity of the high resistivity portion is higher than resistivity of the low resistivity portion. The low resistivity portion contains a transition element identical to a transition element contained in the high resistivity portion.
摘要翻译：根据一个实施例，信息记录和再现装置包括第一层，第二层和记录层。记录层设置在第一层和第二层之间，并且能够以比第一状态高的电阻在第一状态和第二状态之间可逆地转换。第一层和第二层之一包括垂直于第一层和第二层的层叠方向的电阻率分布层和记录层。电阻率分布层包括低电阻率部分和高电阻率部分。高电阻率部分的电阻率高于低电阻率部分的电阻率。低电阻率部分包含与包含在高电阻率部分中的过渡元素相同的过渡元件。

60. 发明申请

US20110024713A1 NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20110024713A1
公开(公告)日：2011-02-03
申请号：US12858975
申请日：2010-08-18
申请人： Chikayoshi KAMATA , Takayuki Tsukamoto , Kohichi Kubo , Shinya Aoki , Takahiro Hirai , Toshiro Hiraoka
发明人： Chikayoshi KAMATA , Takayuki Tsukamoto , Kohichi Kubo , Shinya Aoki , Takahiro Hirai , Toshiro Hiraoka
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/06 , G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/1233 , H01L45/1253 , H01L45/144 , H01L45/1625 , H01L45/1641 , H01L45/165 , H01L45/1658 , H01L45/1675 , Y10S257/92 , Y10S977/712 , Y10S977/734
摘要： According to one embodiment, a nonvolatile memory device includes a stacked body including a first layer, a second layer and a recording layer. The recording layer is provided between the first layer and the second layer. The recording layer is capable of reversibly changing between a first state and a second state having a resistance higher than a resistance in the first state by a current supplied via the first layer and the second layer. The recording layer includes a first portion and a second portion provided in a plane of a major surface of the recording layer. The second portion has a nitrogen amount higher than a nitrogen amount in the first portion.
摘要翻译：根据一个实施例，非易失性存储器件包括包括第一层，第二层和记录层的层叠体。记录层设置在第一层和第二层之间。记录层能够通过经由第一层和第二层提供的电流在具有高于第一状态的电阻的电阻的第一状态和第二状态之间可逆地改变。记录层包括设置在记录层的主表面的平面中的第一部分和第二部分。第二部分具有比第一部分中的氮量高的氮量。

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