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51. 发明申请

US20130076552A1 ANALOG-DIGITAL CONVERTER AND POWER SAVING METHOD THEREOF 失效
标题翻译：模拟数字转换器及其节能方法
公开(公告)号：US20130076552A1
公开(公告)日：2013-03-28
申请号：US13615052
申请日：2012-09-13
申请人： Jaewon NAM , Young Kyun Cho , Yil Suk Yang
发明人： Jaewon NAM , Young Kyun Cho , Yil Suk Yang
IPC分类号： H03M1/34
CPC分类号： H03M1/002 , H03M1/125 , H03M1/462
摘要： Disclosed is an analog-digital converter which includes a pre-amplifier configured to output a comparison result between a sampled analog input signal and a reference signal and to control a power supply operation in response to a power control signal; a digital signal processor configured to generate a digital signal based on the comparison result; a power controller configured to generate an amplifier operation clock signal for controlling the pre-amplifier; and a counter configured to count the number of falling edges of the amplifier operation clock signal and to detect a power interruption point of time of the pre-amplifier according to the counted falling edge number. The power controller generates the power control signal for interrupting a power to be supplied to the pre-amplifier when the power interruption point of time of the pre-amplifier is detected.
摘要翻译：公开了一种模拟数字转换器，其包括：前置放大器，其被配置为输出采样的模拟输入信号和参考信号之间的比较结果，并且响应于功率控制信号来控制电源操作; 配置为基于所述比较结果生成数字信号的数字信号处理器; 功率控制器，被配置为产生用于控制前置放大器的放大器操作时钟信号; 以及计数器，被配置为对放大器操作时钟信号的下降沿的数量进行计数，并根据计数的下降沿数检测前置放大器的电源中断时间点。当检测到前置放大器的电源中断时间点时，功率控制器产生用于中断提供给前置放大器的电力的功率控制信号。

52. 发明申请

US20130033241A1 DC-DC CONVERTER CAPABLE OF CONFIGURING TOPOLOGY 有权
标题翻译： DC-DC转换器，可配置拓扑
公开(公告)号：US20130033241A1
公开(公告)日：2013-02-07
申请号：US13541108
申请日：2012-07-03
申请人： Sewan HEO , Yil Suk YANG , Jong Kee KWON
发明人： Sewan HEO , Yil Suk YANG , Jong Kee KWON
IPC分类号： G05F1/00
CPC分类号： H02M3/1582
摘要： Disclosed is a DC-DC converter including: a switch unit controlling a flow of a current based on a buck-boost topology; a short circuit unit short circuited or opened according to an external setting to change a topology of the switch unit; an inductor storing a current induced by the switch unit; a topology selecting unit selecting a topology in response to an external input signal and generating a signal corresponding to the selected topology; a pulse width modulating unit generating a signal for determining an operation time of the switch unit; a reverse flow detecting unit detecting a reverse flow of a current flowing through the switch unit to generate a signal; and a switch control unit controlling the switch unit in response to signals of the topology selecting unit, the pulse width modulating unit and the reverse flow detecting unit.
摘要翻译：公开了一种DC-DC转换器，包括：开关单元，其控制基于降压 - 升压拓扑的电流; 短路单元根据外部设置短路或断开，以改变开关单元的拓扑; 存储由所述开关单元感应的电流的电感器; 拓扑选择单元响应于外部输入信号选择拓扑并产生对应于所选拓扑的信号; 脉冲宽度调制单元，生成用于确定开关单元的操作时间的信号; 检测流过所述开关单元的电流的反向流以产生信号的逆流检测单元; 以及开关控制单元，其响应于拓扑选择单元，脉冲宽度调制单元和反向流检测单元的信号来控制开关单元。

53. 发明申请

US20120161736A1 APPARATUS AND METHOD FOR INITIALIZING DC-DC CONVERTER 审中-公开
标题翻译：用于初始化DC-DC转换器的装置和方法
公开(公告)号：US20120161736A1
公开(公告)日：2012-06-28
申请号：US13311582
申请日：2011-12-06
申请人： Sewan Heo , Yil Suk Yang , JongDae Kim
发明人： Sewan Heo , Yil Suk Yang , JongDae Kim
IPC分类号： G05F1/46
CPC分类号： H02M1/36
摘要： The present disclosure relates to an apparatus and method for initializing a DC-DC converter, and can stabilize an output voltage in an initial state, and prevent malfunction of a system control through initialization and high-efficiency DC-DC converters, by converting a variable voltage into a predetermined constant voltage and generating a reset signal for initializing a constant-voltage circuit so as to initialize the DC-DC converter and a control unit composed of the constant-voltage circuit, if the converted voltage reaches a target voltage, in an initialization DC-DC interval, and then converting the variable voltage into the predetermined constant voltage and outputting the converted voltage, in a high-efficiency DC-DC interval.
摘要翻译：本发明涉及一种用于初始化DC-DC转换器的装置和方法，并且可以在初始状态下稳定输出电压，并且通过初始化和高效率DC-DC转换器来防止系统控制的故障，通过将变量产生一个预定的恒定电压并产生一个复位信号，用于初始化恒压电路，以初始化DC-DC转换器;以及一个由恒压电路组成的控制单元，如果转换的电压达到目标电压，则在初始化DC-DC间隔，然后将可变电压转换成预定的恒定电压并输出转换后的电压。

54. 发明申请

US20120150776A1 ADAPTIVE MULTIMEDIA PROCESSOR AND ADAPTIVE DATA PROCESSING METHOD 审中-公开
标题翻译：自适应多媒体处理器和自适应数据处理方法
公开(公告)号：US20120150776A1
公开(公告)日：2012-06-14
申请号：US13287142
申请日：2011-11-02
申请人： Yil Suk YANG , Jongdae KIM , Jung Hee SUK , Sewan HEO
发明人： Yil Suk YANG , Jongdae KIM , Jung Hee SUK , Sewan HEO
IPC分类号： G06F15/18
CPC分类号： H04N19/40 , H04N19/61
摘要： Disclosed is a structure of an adaptive multimedia processor and a method for implementing an adaptive data processing algorithm. The adaptive multimedia processor includes a bit stream analyzer for analyzing bit stream information of multimedia data, and a bit stream learning device for converting multimedia data having a format which cannot be reproduced in a device, to multimedia data having a format which can be reproduced in a device, through an execution of a learning algorithm, based on an analysis by the bit stream analyzer.
摘要翻译：公开了自适应多媒体处理器的结构和实现自适应数据处理算法的方法。自适应多媒体处理器包括用于分析多媒体数据的比特流信息的比特流分析器和用于将具有不能在设备中再现的格式的多媒体数据转换为具有可以再现的格式的多媒体数据的比特流学习装置基于比特流分析器的分析，通过执行学习算法来实现该设备。

55. 发明授权

US07769981B2 Row of floating point accumulators coupled to respective PEs in uppermost row of PE array for performing addition operation 有权
标题翻译：耦合到PE阵列的最上排中的相应PE的浮点累加器的行，用于执行附加操作
公开(公告)号：US07769981B2
公开(公告)日：2010-08-03
申请号：US12045844
申请日：2008-03-11
申请人： Chun Gi Lyuh , Yil Suk Yang , Se Wan Heo , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim , Ki Chul Kim , Se Hoon Yoo
发明人： Chun Gi Lyuh , Yil Suk Yang , Se Wan Heo , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim , Ki Chul Kim , Se Hoon Yoo
IPC分类号： G06F15/80
CPC分类号： G06F15/8007
摘要： Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.
摘要翻译：提供了一种用于支持浮点运算的并行处理器。并行处理器具有灵活的结构，便于开发涉及多媒体计算的并行算法，需要较低的硬件成本，并且消耗低功耗。为了支持浮点运算，并行处理器使用浮点累加器和浮点乘法的标志。使用并行处理器，可以以低成本在三维（3D）图形处理中处理几何变换操作。此外，可以通过分区单指令多数据（SIMD）方法和有条件执行指令的方法来最小化用于指令的总线宽度的成本。

56. 发明授权

US07482997B2 Voltage/current driven active matrix organic electroluminescent pixel circuit and display device 有权
标题翻译：电压/电流驱动有源矩阵有机电致发光像素电路和显示装置
公开(公告)号：US07482997B2
公开(公告)日：2009-01-27
申请号：US11197013
申请日：2005-08-04
申请人： Yil Suk Yang , Dae Woo Lee , Jong Dae Kim
发明人： Yil Suk Yang , Dae Woo Lee , Jong Dae Kim
IPC分类号： G09G3/00
CPC分类号： G09G3/3266 , G09G3/325 , G09G3/3258 , G09G2300/0842
摘要： Provided is a voltage/current driven active matrix organic electroluminescent (EL) pixel circuit. In particular, a voltage/current driven active matrix organic EL pixel circuit capable of driving organic ELs by a voltage programming method and a current programming method using one pixel circuit and an organic EL display device that uses such a pixel circuit are provided. The voltage/current driven active matrix organic EL pixel circuit can be used for a voltage driven active matrix organic EL and a current driven active matrix organic EL by programming such that the flexibility and applicability of the pixel circuit and the driving circuit are excellent.
摘要翻译：提供电压/电流驱动的有源矩阵有机电致发光（EL）像素电路。特别地，提供了能够通过电压编程方法驱动有机EL的电压/电流驱动的有源矩阵有机EL像素电路和使用一个像素电路的当前编程方法和使用这种像素电路的有机EL显示装置。电压/电流驱动的有源矩阵有机EL像素电路可以通过编程使用于电压驱动的有源矩阵有机EL和电流驱动的有源矩阵有机EL，使得像素电路和驱动电路的灵活性和适用性非常优异。

57. 发明授权

US07461235B2 Energy-efficient parallel data path architecture for selectively powering processing units and register files based on instruction type 有权
标题翻译：节能并行数据通道架构，可根据指令类型有选择地为处理单元供电并注册文件
公开(公告)号：US07461235B2
公开(公告)日：2008-12-02
申请号：US11144703
申请日：2005-06-06
申请人： Yil Suk Yang , Tae Moon Roh , Dae Woo Lee , Sang Heung Lee , Jong Dae Kim
发明人： Yil Suk Yang , Tae Moon Roh , Dae Woo Lee , Sang Heung Lee , Jong Dae Kim
IPC分类号： G06F15/76 , G06F1/32
CPC分类号： G06F9/3885 , G06F1/32 , G06F1/3287 , G06F9/30141 , G06F9/30156 , G06F9/3822 , G06F9/3824 , Y02D10/171
摘要： Provided is a parallel data path architecture for high energy efficiency. In this architecture, a plurality of parallel process units and a plurality of function units of the process units are controlled by instructions and processed in parallel to improve performance. Also, since only necessary process units and function units are enabled, power dissipation is reduced to enhance energy efficiency. Further, by use of a simple instruction format, hardware can be programmed as the parallel data path architecture for high energy efficiency, which satisfies both excellent performance and low power dissipation, thus elevating hardware flexibility.
摘要翻译：提供了一种用于高能效的并行数据路径架构。在该架构中，处理单元的多个并行处理单元和多个功能单元由指令控制并且并行处理以提高性能。此外，由于只需要必要的处理单元和功能单元，所以功耗降低以提高能量效率。此外，通过使用简单的指令格式，可以将硬件编程为用于高能量效率的并行数据路径体系结构，其既能满足优异性能又具有低功耗，从而提高硬件灵活性。

58. 发明授权

US07420403B2 Latch circuit and flip-flop 有权
标题翻译：锁存电路和触发器
公开(公告)号：US07420403B2
公开(公告)日：2008-09-02
申请号：US11520165
申请日：2006-09-13
申请人： Yil Suk Yang , Jong Dae Kim , Tae Moon Roh , Dae Woo Lee
发明人： Yil Suk Yang , Jong Dae Kim , Tae Moon Roh , Dae Woo Lee
IPC分类号： H03K3/00
CPC分类号： H03K19/0013 , H03K3/356156 , H03K3/356182
摘要： A high-reliability, multi-threshold complementary metal oxide semiconductor (CMOS) latch circuit is presented that uses both low and high threshold inverters. The multi-threshold latch circuit includes: a low threshold forward clock inverter inverting an input-terminal logic state and applying the inverted logic state to an output-terminal logic state when a clock is in a first logic state; and a high threshold backward clock inverter forming a circular latch structure together with the forward clock inverter, and inverting an input-terminal logic state and applying the inverted logic state to an output logic state when the clock is in a second logic state.
摘要翻译：提出了一种高可靠性，多阈值互补金属氧化物半导体（CMOS）锁存电路，其使用低和高阈值逆变器。多阈值锁存电路包括：当门限处于第一逻辑状态时，低阈值正向时钟反相器反相输入端逻辑状态并将反相逻辑状态施加到输出端逻辑状态; 以及高阈值反向时钟反相器，与正向时钟反相器一起形成圆形锁存结构，并且在时钟处于第二逻辑状态时反相输入端逻辑状态并将反相逻辑状态应用于输出逻辑状态。

59. 发明授权

US07335945B2 Multi-gate MOS transistor and method of manufacturing the same 有权
标题翻译：多栅极MOS晶体管及其制造方法
公开(公告)号：US07335945B2
公开(公告)日：2008-02-26
申请号：US11012695
申请日：2004-12-16
申请人： Dae Woo Lee , Tae Moon Roh , Sung Ku Kwon , Il Yong Park , Yil Suk Yang , Byoung Gon Yu , Jong Dae Kim
发明人： Dae Woo Lee , Tae Moon Roh , Sung Ku Kwon , Il Yong Park , Yil Suk Yang , Byoung Gon Yu , Jong Dae Kim
IPC分类号： H01L29/78 , H01L21/8234
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/42392 , H01L29/66795 , H01L29/78645
摘要： Provided are a multi-gate MOS transistor and a method of manufacturing the same. Two silicon fins are vertically stacked on a silicon on insulator (SOI) substrate, and four side surfaces of an upper silicon fin and three side surfaces of a lower silicon fin are used as a channel. Therefore, a channel width is increased, so that current driving capability of a device is improved, and high performance nano-level semiconductor IC and highly integrated memory IC can be manufactured through the optimization and stability of a process.
摘要翻译：提供一种多栅极MOS晶体管及其制造方法。垂直堆叠在硅绝缘体（SOI）基板上的两个硅散热片，上硅片的四个侧表面和下硅片的三个侧表面用作通道。因此，通道宽度增加，从而提高了器件的电流驱动能力，并且可以通过工艺的优化和稳定性来制造高性能纳米级半导体IC和高度集成的存储器IC。

60. 发明申请

US20070150763A1 Highly energy-efficient processor employing dynamic voltage scaling 有权
标题翻译：采用动态电压调节的高能效处理器
公开(公告)号：US20070150763A1
公开(公告)日：2007-06-28
申请号：US11520177
申请日：2006-09-13
申请人： Yil Suk Yang , Jong Dae Kim , Soon Il Yeo , Chun Gi Lyuh
发明人： Yil Suk Yang , Jong Dae Kim , Soon Il Yeo , Chun Gi Lyuh
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3287 , G06F1/3293 , G06F1/3296 , Y02D10/122 , Y02D10/171 , Y02D10/172 , Y02D50/20
摘要： Provided is a highly energy-efficient processor architecture. The architecture employs 2-stage dynamic voltage scaling (DVS) and a sleep mode for high energy efficiency, dynamically controls the power supply voltage and activation of an embedded processor with instructions, and thus can prevent performance deterioration while reducing power consumption.A highly energy-efficient processor employing the processor architecture includes: a function unit block for performing an operation according to instructions input from the outside; at least one peripheral unit block for performing data communication with an external device; an instruction decoder for interpreting the input instructions and determining operation modes of the function unit block and peripheral unit block required for executing the interpreted instructions; a function unit block driver for applying a different power supply voltage according to the operation mode of the function unit block to the function unit block; and a peripheral unit block driver for applying a different power supply voltage according to the operation mode of the peripheral unit block to the peripheral unit block.
摘要翻译：提供了一种高能效的处理器架构。该架构采用2级动态电压调节（DVS）和睡眠模式以实现高能效，通过指令动态控制电源电压和嵌入式处理器的激活，从而可以在降低功耗的同时防止性能下降。采用该处理器架构的高能效处理器包括：功能单元块，用于根据从外部输入的指令进行操作; 用于与外部设备进行数据通信的至少一个外围单元块; 用于解释输入指令并确定执行解释指令所需的功能单元块和外围单元块的操作模式的指令解码器; 功能单元块驱动器，用于根据功能单元块的操作模式将不同的电源电压施加到功能单元块; 以及外围单元块驱动器，用于根据外围单元块的操作模式向外围单元块施加不同的电源电压。

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