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51. 发明申请

US20120037913A1 THIN-FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20120037913A1
公开(公告)日：2012-02-16
申请号：US13167668
申请日：2011-06-23
申请人： O-Sung SEO , Seong-Hun KIM , Yang-Ho BAE , Jean-Ho SONG
发明人： O-Sung SEO , Seong-Hun KIM , Yang-Ho BAE , Jean-Ho SONG
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78618 , H01L29/458 , H01L29/66765
摘要： A thin-film transistor (TFT) and a method of manufacturing the same are disclosed herein. The TFT may include a gate electrode disposed on an insulating substrate, an insulating layer disposed on the insulating substrate and the gate electrode, an active layer pattern disposed on the insulating layer to overlap the gate electrode, a source electrode disposed on the insulating layer and at least part of which overlaps the active layer pattern, and a drain electrode which is separated from the source electrode and at least part of which overlaps the active layer pattern. A first ohmic contact layer pattern may be disposed between the active layer pattern and the source electrode and between the active layer pattern and the drain electrode. The first ohmic contact layer may have higher nitrogen content on its surface than in other portions of the first ohmic contact layer.
摘要翻译：本文公开了一种薄膜晶体管（TFT）及其制造方法。 TFT可以包括设置在绝缘基板上的栅电极，设置在绝缘基板上的绝缘层和栅电极，设置在绝缘层上的与栅电极重叠的有源层图案，设置在绝缘层上的源电极和其至少一部分与有源层图案重叠，以及与源电极分离并且其至少一部分与有源层图案重叠的漏电极。可以在有源层图案和源电极之间以及有源层图案和漏电极之间设置第一欧姆接触层图案。第一欧姆接触层在其表面上可以具有比在第一欧姆接触层的其它部分更高的氮含量。

52. 发明申请

US20110133193A1 THIN FILM TRANSISTOR SUBSTRATE AND THE METHOD THEREOF 有权
标题翻译：薄膜晶体管基板及其方法
公开(公告)号：US20110133193A1
公开(公告)日：2011-06-09
申请号：US12844356
申请日：2010-07-27
申请人： Jean-Ho SONG , Shin-Il Choi , Sun-Young Hong , Shi-Yul Kim , Ki-Yeup Lee , Jae-Hyoung Youn , Sung-Ryul Kim , O-Sung Seo , Yang-Ho Bae , Jong-Hyun Choung , Dong-Ju Yang , Bong-Kyun Kim , Hwa-Yeul Oh , Pil-Soon Hong , Byeong-Beom Kim , Je-Hyeong Park , Yu-Gwang Jeong , Jong-In Kim , Nam-Seok Suh
发明人： Jean-Ho SONG , Shin-Il Choi , Sun-Young Hong , Shi-Yul Kim , Ki-Yeup Lee , Jae-Hyoung Youn , Sung-Ryul Kim , O-Sung Seo , Yang-Ho Bae , Jong-Hyun Choung , Dong-Ju Yang , Bong-Kyun Kim , Hwa-Yeul Oh , Pil-Soon Hong , Byeong-Beom Kim , Je-Hyeong Park , Yu-Gwang Jeong , Jong-In Kim , Nam-Seok Suh
IPC分类号： H01L27/12 , H01L29/786 , H01L21/336
CPC分类号： H01L27/124 , H01L27/12 , H01L27/1214 , H01L27/1288 , H01L29/42368 , H01L29/458 , H01L29/78669
摘要： A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.
摘要翻译：薄膜晶体管阵列面板包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，设置在半导体层上的数据线和漏极，钝化层覆盖数据线和漏电极，并且具有露出漏电极的一部分的接触孔，以及通过接触孔与漏电极电连接的像素电极。数据线和漏极各自具有包括钛的下层和铜的上层的双层，下层比上层宽，下层具有暴露的区域。栅极绝缘层可以具有台阶形状。

53. 发明授权

US07741641B2 TFT substrate and display device having the same 失效
标题翻译： TFT基板和具有该TFT基板的显示装置
公开(公告)号：US07741641B2
公开(公告)日：2010-06-22
申请号：US11371057
申请日：2006-03-08
申请人： Yang-Ho Bae , Chang-Oh Jeong , Min-Seok Oh , Je-Hun Lee , Beom-Seok Cho
发明人： Yang-Ho Bae , Chang-Oh Jeong , Min-Seok Oh , Je-Hun Lee , Beom-Seok Cho
IPC分类号： H01L29/43 , H01L29/786
CPC分类号： H01L29/4908 , H01L27/124 , H01L29/458
摘要： A TFT substrate includes a base substrate, a gate wiring formed on the base substrate, a gate insulation layer, an activation layer, an oxidation-blocking layer, a data wiring, a protection layer and a pixel electrode. The gate wiring includes a gate line and a gate electrode. The gate insulation layer is formed on the base substrate to cover the gate wiring. The activation layer is formed on the gate insulation layer. The oxidation-blocking layer is formed on the activation layer. The data wiring includes a data line, a source electrode and a drain electrode. The source and drain electrodes are disposed on the oxidation-blocking layer therefore lowering the on-current (“Ion”) for turning on the TFT and increasing the off-current (“Ioff”) for turning off the TFT due to the oxidation-blocking layer.
摘要翻译： TFT基板包括基底基板，形成在基底基板上的栅极布线，栅极绝缘层，激活层，氧化阻挡层，数据布线，保护层和像素电极。栅极布线包括栅极线和栅电极。栅极绝缘层形成在基底基板上以覆盖栅极布线。活化层形成在栅绝缘层上。氧化阻挡层形成在活化层上。数据线包括数据线，源电极和漏电极。源电极和漏电极设置在氧化阻挡层上，因此降低用于导通TFT的导通电流（“Ion”），并且由于氧化阻挡层而增加关闭TFT的截止电流（“Ioff”），阻挡层。

54. 发明申请

US20090286386A1 WIRE STRUCTURE, METHOD OF FORMING WIRE, THIN FILM TRANSISTOR SUBSTRATE, AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE 有权
标题翻译：线形结构，形成线，薄膜晶体管衬底的方法和制造薄膜晶体管衬底的方法
公开(公告)号：US20090286386A1
公开(公告)日：2009-11-19
申请号：US12509290
申请日：2009-07-24
申请人： JE-HUN LEE , Chang-oh Jeong , Beom-seok Cho , Yang-ho Bae
发明人： JE-HUN LEE , Chang-oh Jeong , Beom-seok Cho , Yang-ho Bae
IPC分类号： H01L21/28
CPC分类号： H01L29/4908 , G02F2001/13629 , G02F2001/136295 , H01L23/53238 , H01L27/12 , H01L27/124 , H01L29/458 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Provided are a wire structure, a method of forming a wire, a thin film transistor (TFT) substrate, and a method of manufacturing the TFT substrate. The wire structure includes a barrier layer disposed on a lower structure, a copper conductive layer comprising copper or copper alloy disposed on the barrier layer, an intermediate layer comprising copper nitride disposed on the copper conductive layer, and a capping layer disposed on the intermediate layer.
摘要翻译：提供一种线结构，形成线的方法，薄膜晶体管（TFT）基板以及制造TFT基板的方法。导线结构包括设置在下部结构上的阻挡层，设置在阻挡层上的包含铜或铜合金的铜导电层，设置在铜导电层上的包含氮化铜的中间层和设置在中间层上的覆盖层。

55. 发明授权

US07619254B2 Thin film transistor array panel including layered line structure and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板包括分层线结构及其制造方法
公开(公告)号：US07619254B2
公开(公告)日：2009-11-17
申请号：US11228852
申请日：2005-09-16
申请人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
发明人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
IPC分类号： H01L27/14 , H01L29/04 , H01L29/15 , H01L31/036
CPC分类号： H01L27/1214 , H01L27/1225 , H01L27/124
摘要： The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).
摘要翻译：本发明提供一种薄膜晶体管阵列板，其包括绝缘基板; 形成在所述绝缘基板上的栅极线; 栅极绝缘层，形成在栅极线上; 漏电极和数据线，其具有形成在所述栅极绝缘层上的源电极，所述漏电极与所述源电极相邻，其间具有间隙; 以及耦合到所述漏电极的像素电极，其中所述栅极线，所述数据线和所述漏电极中的至少一个包括包括导电氧化物的第一导电层和包含铜（Cu）的第二导电层。

56. 发明授权

US07586197B2 Wire structure, method of forming wire, thin film transistor substrate, and method of manufacturing thin film transistor substrate 失效
标题翻译：导线结构，导线形成方法，薄膜晶体管基板以及制造薄膜晶体管基板的方法
公开(公告)号：US07586197B2
公开(公告)日：2009-09-08
申请号：US11474918
申请日：2006-06-24
申请人： Je-hun Lee , Chang-oh Jeong , Beom-seok Cho , Yang-ho Bae
发明人： Je-hun Lee , Chang-oh Jeong , Beom-seok Cho , Yang-ho Bae
IPC分类号： H01L23/48
CPC分类号： H01L29/4908 , G02F2001/13629 , G02F2001/136295 , H01L23/53238 , H01L27/12 , H01L27/124 , H01L29/458 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Provided are a wire structure, a method of forming a wire, a thin film transistor (TFT) substrate, and a method of manufacturing the TFT substrate. The wire structure includes a barrier layer disposed on a lower structure, a copper conductive layer comprising copper or copper alloy disposed on the barrier layer, an intermediate layer comprising copper nitride disposed on the copper conductive layer, and a capping layer disposed on the intermediate layer.
摘要翻译：提供一种线结构，形成线的方法，薄膜晶体管（TFT）基板以及制造TFT基板的方法。导线结构包括设置在下部结构上的阻挡层，设置在阻挡层上的包含铜或铜合金的铜导电层，设置在铜导电层上的包含氮化铜的中间层和设置在中间层上的覆盖层。

57. 发明授权

US07550768B2 Thin film transistor array panel and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07550768B2
公开(公告)日：2009-06-23
申请号：US11944130
申请日：2007-11-21
申请人： Beom-Seok Cho , Yang-Ho Bae , Je-Hun Lee , Chang-Oh Jeong
发明人： Beom-Seok Cho , Yang-Ho Bae , Je-Hun Lee , Chang-Oh Jeong
IPC分类号： H01L29/04 , H01L29/10 , H01L31/036 , H01L31/0376 , H01L31/20 , H01L29/76 , H01L31/112 , H01L29/15
CPC分类号： G02F1/136286 , G02F2001/13629 , G02F2001/136295 , H01L27/3276 , Y10S438/924
摘要： The present invention provides a TFT array panel and a manufacturing method of the same, which has signal lines including a lower layer of an Al containing metal and an upper layer of a molybdenum alloy (Mo-alloy) comprising molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti). Accordingly, undercut, overhang, and mouse bites which may arise in an etching process, are prevented, and TFT array panels that have signal lines having low resistivity and good contact characteristics are provided.
摘要翻译：本发明提供一种TFT阵列面板及其制造方法，其特征在于，具有含有Al的金属的下层和包含钼（Mo）的钼合金（Mo合金）的上层的信号线，至少包括铌（Nb），钒（V）和钛（Ti）之一。因此，防止在蚀刻工艺中可能出现的底切，突出和小鼠咬合，并且提供具有低电阻率和良好接触特性的信号线的TFT阵列面板。

58. 发明申请

US20090121228A1 ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：阵列基板及其制造方法
公开(公告)号：US20090121228A1
公开(公告)日：2009-05-14
申请号：US12269748
申请日：2008-11-12
申请人： Jang-Soo Kim , Hong-Long Ning , Bong-Kyun Kim , Hong-Sick Park , Shi-Yul Kim , Chang-Oh Jeong , Sang-Gab Kim , Jae-Hyoung Youn , Woo-Geun Lee , Yang-Ho Bae , Pil-Sang Yun , Jong-Hyun Choung , Sun-Young Hong , Ki-Won Kim , Byeong-Jin Lee , Yopung-Wook Lee , Jong-In Kim , Byeong-Beom Kim , Nam-Seok Suh
发明人： Jang-Soo Kim , Hong-Long Ning , Bong-Kyun Kim , Hong-Sick Park , Shi-Yul Kim , Chang-Oh Jeong , Sang-Gab Kim , Jae-Hyoung Youn , Woo-Geun Lee , Yang-Ho Bae , Pil-Sang Yun , Jong-Hyun Choung , Sun-Young Hong , Ki-Won Kim , Byeong-Jin Lee , Yopung-Wook Lee , Jong-In Kim , Byeong-Beom Kim , Nam-Seok Suh
IPC分类号： H01L29/04 , H01L21/336
CPC分类号： G02F1/13458 , G02F1/136286 , G02F2001/136295 , H01L27/1218 , H01L27/124 , H01L27/1288
摘要： A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.
摘要翻译：栅极线包括形成在基底基板上的第一籽晶层和形成在第一籽晶层上的第一金属层。在基底基板上形成第一绝缘层。在基底基板上形成第二绝缘层。这里，在与栅极线交叉的方向上通过第二绝缘层形成线沟槽。数据线包括形成在线沟槽下方的第二晶种层和形成在线沟槽中的第二金属层。像素电极形成在基底基板的像素区域中。因此，使用绝缘层形成预定深度的沟槽，并且通过电镀方法形成金属层，从而可以形成具有足够厚度的金属线。

59. 发明申请

US20080166827A1 THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20080166827A1
公开(公告)日：2008-07-10
申请号：US11944083
申请日：2007-11-21
申请人： Beom-Seok Cho , Yang-Ho Bae , Je-Hun Lee , Chang-Oh Jeong
发明人： Beom-Seok Cho , Yang-Ho Bae , Je-Hun Lee , Chang-Oh Jeong
IPC分类号： H01L21/70
CPC分类号： G02F1/136286 , G02F2001/13629 , G02F2001/136295 , H01L27/3276 , Y10S438/924
摘要： The present invention provides a TFT array panel and a manufacturing method of the same, which has signal lines including a lower layer of an Al containing metal and an upper layer of a molybdenum alloy (Mo-alloy) comprising molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti). Accordingly, undercut, overhang, and mouse bites which may arise in an etching process, are prevented, and TFT array panels that have signal lines having low resistivity and good contact characteristics are provided.
摘要翻译：本发明提供一种TFT阵列面板及其制造方法，其特征在于，具有含有Al的金属的下层和包含钼（Mo）的钼合金（Mo合金）的上层的信号线，至少包括铌（Nb），钒（V）和钛（Ti）之一。因此，防止在蚀刻工艺中可能出现的底切，突出和小鼠咬合，并且提供具有低电阻率和良好接触特性的信号线的TFT阵列面板。

60. 发明申请

US20070279544A1 Wiring for display device and thin film transistor array panel including the same and method for manufacturing thereof 审中-公开
标题翻译：显示装置和薄膜晶体管阵列面板的布线及其制造方法
公开(公告)号：US20070279544A1
公开(公告)日：2007-12-06
申请号：US11445047
申请日：2006-05-31
申请人： Yang-Ho Bae , Soon-Kwon Lim , Chang-Oh Jeong
发明人： Yang-Ho Bae , Soon-Kwon Lim , Chang-Oh Jeong
IPC分类号： G02F1/136
CPC分类号： G02F1/1345 , B82Y20/00 , G02F2202/36
摘要： The present invention provides a manufacturing method of a thin film transistor array panel comprising forming a gate line on a substrate, forming a gate insulating layer and a semiconductor layer on the gate line in sequence, forming a data line having a source electrode and a drain electrode on the gate insulating layer and the semiconductor layer, and forming a pixel electrode connected to the drain electrode. At least one of the formation of the gate line and the formation of the data line includes a step of forming a slurry layer which is a mixture of conductor particles and a solvent, patterning the slurry layer by using a shaping mold with a prescribed pattern, and removing the shaping mold.
摘要翻译：本发明提供一种薄膜晶体管阵列板的制造方法，包括在基板上形成栅极线，在栅极线上依次形成栅极绝缘层和半导体层，形成具有源极和漏极的数据线栅极绝缘层和半导体层上的电极，并形成连接到漏电极的像素电极。栅极线的形成和数据线的形成中的至少一个包括形成作为导体颗粒和溶剂的混合物的浆料层的步骤，通过使用具有规定图案的成形模具对浆料层进行图案化，并移除成型模具。

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