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    • 51. 发明授权
    • Lateral bipolar transistor
    • 侧面双极晶体管
    • US06653714B2
    • 2003-11-25
    • US10300440
    • 2002-11-20
    • Toshinobu MatsunoTakeshi FukudaKatsunori NishiiKaoru InoueDaisuke Ueda
    • Toshinobu MatsunoTakeshi FukudaKatsunori NishiiKaoru InoueDaisuke Ueda
    • H01L27082
    • H01L29/66242H01L29/7317
    • A lateral bipolar transistor includes: a substrate; a first insulative region formed on the substrate; a first semiconductor region of a first conductivity type selectively formed on the first insulative region; a second insulative region formed so as to substantially cover the first semiconductor region; and a second semiconductor region of a second conductivity type different from the first conductivity type, a second semiconductor region being selectively formed, wherein: the second insulative region has a first opening which reaches a surface of the first semiconductor region, and the first semiconductor region has a second opening which reaches the underlying first insulative region, the second opening being provided in a position corresponding to the first opening of the second insulative region; the second semiconductor region is formed so as to fill the first opening and the second opening, thereby functioning as a base region; a lower portion of the second semiconductor region which at least fills the second opening is formed by lateral growth from a face of the first semiconductor region defining a side wall of the second opening; and the first semiconductor region includes an emitter region and a collector region formed therein.
    • 横向双极晶体管包括:衬底; 形成在所述基板上的第一绝缘区域; 选择性地形成在所述第一绝缘区域上的第一导电类型的第一半导体区域; 形成为基本上覆盖所述第一半导体区域的第二绝缘区域; 以及与第一导电类型不同的第二导电类型的第二半导体区域,选择性地形成第二半导体区域,其中:第二绝缘区域具有到达第一半导体区域的表面的第一开口,第一半导体区域 具有到达下面的第一绝缘区域的第二开口,第二开口设置在与第二绝缘区域的第一开口对应的位置; 第二半导体区域形成为填充第一开口和第二开口,从而起基底区域的作用; 至少填充第二开口的第二半导体区域的下部通过从限定第二开口的侧壁的第一半导体区域的表面横向生长形成; 并且第一半导体区域包括形成在其中的发射极区域和集电极区域。
    • 52. 发明授权
    • Lateral bipolar transistor and method for producing the same
    • 侧面双极晶体管及其制造方法
    • US06503808B1
    • 2003-01-07
    • US09687251
    • 2000-10-13
    • Toshinobu MatsunoTakeshi FukudaKatsunori NishiiKaoru InoueDaisuke Ueda
    • Toshinobu MatsunoTakeshi FukudaKatsunori NishiiKaoru InoueDaisuke Ueda
    • H01L21331
    • H01L29/66242H01L29/7317
    • A lateral bipolar transistor includes: a substrate; a first insulative region formed on the substrate; a first semiconductor region of a first conductivity type selectively formed on the first insulative region; a second insulative region formed so as to substantially cover the first semiconductor region; and a second semiconductor region of a second conductivity type different from the first conductivity type, a second semiconductor region being selectively formed, wherein: the second insulative region has a first opening which reaches a surface of the first semiconductor region, and the first semiconductor region has a second opening which reaches the underlying first insulative region, the second opening being provided in a position corresponding to the first opening of the second insulative region; the second semiconductor region is formed so as to fill the first opening and the second opening, thereby functioning as a bass region; a lower portion of the second semiconductor region which at least fills the second opening is formed by lateral growth from a face of the first semiconductor region defining a side wall of the second opening; and the first semiconductor region includes an emitter region and a collector region formed therein.
    • 横向双极晶体管包括:衬底; 形成在所述基板上的第一绝缘区域; 选择性地形成在所述第一绝缘区域上的第一导电类型的第一半导体区域; 形成为基本上覆盖所述第一半导体区域的第二绝缘区域; 以及与第一导电类型不同的第二导电类型的第二半导体区域,选择性地形成第二半导体区域,其中:第二绝缘区域具有到达第一半导体区域的表面的第一开口,第一半导体区域 具有到达下面的第一绝缘区域的第二开口,第二开口设置在与第二绝缘区域的第一开口对应的位置; 第二半导体区域形成为填充第一开口和第二开口,从而起低音区域的作用; 至少填充第二开口的第二半导体区域的下部通过从限定第二开口的侧壁的第一半导体区域的表面横向生长形成; 并且第一半导体区域包括形成在其中的发射极区域和集电极区域。
    • 53. 发明授权
    • Electrostatic breakdown protection for a semiconductor device
    • 半导体器件的静电击穿保护
    • US6072350A
    • 2000-06-06
    • US335725
    • 1999-06-18
    • Takeshi Fukuda
    • Takeshi Fukuda
    • H01L21/822H01L27/02H01L27/04H03K5/08
    • H01L27/0255H01L27/0259
    • A SUB wiring provided outside of a common discharge line formed on outer periphery of a chip in parallel to the latter. To the common discharge line, only voltage clamping elements and diode elements as electrostatic protection elements are connected. The common discharge line is in floating condition for rising withstanding voltage. On the other hand, to the SUB wiring, additional circuits, such as BBG circuit and so forth, consisting of transistors are connected to connect the latter to the substrate. With these two wirings, the width of the common discharge line can be made narrower to limit an increase of a chip area. By this, it is possible to improve resistance to electrostatic breakdown without increasing chip area.
    • 设置在与芯片的外周平行的芯片的外周上形成的公共放电线的外侧的SUB布线。 对于公共放电线,仅连接作为静电保护元件的电压钳位元件和二极管元件。 普通放电线处于浮动状态,以提高耐压。 另一方面,对于SUB布线,由晶体管构成的诸如BBG电路等的附加电路被连接以将后者连接到基板。 通过这两条布线,可以使公共放电线的宽度变窄以限制芯片面积的增加。 由此,可以在不增加芯片面积的情况下提高抗静电电击。
    • 56. 发明授权
    • Semiconductor memory device having dummy digit lines
    • 具有虚拟数字线的半导体存储器件
    • US5483495A
    • 1996-01-09
    • US285291
    • 1994-08-03
    • Takeshi Fukuda
    • Takeshi Fukuda
    • G11C11/401G11C7/10G11C7/18H01L21/8242H01L27/108G11C7/02
    • G11C7/1075G11C7/18
    • A semiconductor memory device as a video memory is disclosed. The video memory includes a first memory cell array plate having a plurality of first pairs of digit lines and a plurality of second pairs of digit lines, a plurality of first sense amplifiers arranged along one side of the first array plate and provided for the first pairs of digit lines, a plurality of second sense amplifiers arranged along an opposite side of the first array plate and provided for the second pairs of digit lines, a second memory cell array plate having a plurality of third pairs of digit lines, and a plurality of third sense amplifier provided for the third pairs of digit lines. A plurality of pairs of dummy digit lines are further provided in the second memory cell array plate so that the first and second cell array plates has the pairs of digit lines equal in number to each other.
    • 公开了一种作为视频存储器的半导体存储器件。 视频存储器包括具有多个第一对数字线和多个第二对数字线的第一存储单元阵列板,多个第一读出放大器,沿第一阵列板的一侧布置并且为第一对配置 数字线的多个第二读出放大器,沿着第一阵列板的相对侧布置并提供用于第二对数字线的多个第二读出放大器,具有多个第三对数字线的第二存储单元阵列板,以及多个第 为第三对数字线提供第三感测放大器。 在第二存储单元阵列板中进一步设置多对虚拟数字线,使得第一和第二单元阵列板具有彼此数量相等的数字线对。
    • 58. 发明授权
    • Semiconductor memory apparatus
    • 半导体存储装置
    • US5315138A
    • 1994-05-24
    • US826419
    • 1992-01-27
    • Takeshi Fukuda
    • Takeshi Fukuda
    • G11C5/02G11C11/4097H01L29/92
    • G11C5/025G11C11/4097Y10S257/922
    • A semiconductor memory apparatus according to the present invention consists of memory cell forming regions, each formed in a rectangular plane form, a plurality of bit line pairs connected to a plurality of memory cells arranged and formed in these memory cell forming regions, and first and second peripheral circuits formed outside said memory cell forming regions, wherein said first and second peripheral circuits are formed and arranged symmetrically with respect to the point of intersection of two centerlines connecting the middle points of two opposite ones of the four sides of each of said memory cell forming regions, and said bit line pairs are connected to the first and second peripheral circuits. This configuration makes it possible to match the constituent elements of the peripheral circuits with each other and balance the bit line pairs, and thereby to prevent the drop in writing or reading rate and erroneous operations, to which semiconductor memory apparatuses according to the prior art are susceptible.
    • 根据本发明的半导体存储装置由以矩形平面形式形成的存储单元形成区域,与在这些存储单元形成区域中布置和形成的多个存储单元连接的多个位线对构成,第一和 形成在所述存储单元形成区域之外的第二外围电路,其中所述第一和第二外围电路相对于连接每个所述存储器的四个相反侧的两个中间点的两个中心线的交点形成和布置 单元形成区域和所述位线对连接到第一和第二外围电路。 这种配置使得可以将外围电路的组成元件彼此匹配并平衡位线对,从而防止写入或读取速率下降以及错误操作,根据现有技术的半导体存储器件是 易感。