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51. 发明授权

US4912425A Operational amplifier circuit having stable operating point 失效
标题翻译：运算放大器电路具有稳定的工作点
公开(公告)号：US4912425A
公开(公告)日：1990-03-27
申请号：US275311
申请日：1988-11-23
申请人： Osamu Kobayashi , Kunihiko Gotoh
发明人： Osamu Kobayashi , Kunihiko Gotoh
IPC分类号： H03F3/345 , H03F1/30 , H03F3/34
CPC分类号： H03F1/308
摘要： An operational amplifier circuit comprises a differential amplifier circuit for generating an output voltage in response to the difference in potential between two input signals, a level shift circuit for shifting the output voltage of the differential amplifier circuit, a push-pull output circuit which operates in response to the output voltages of the differential amplifier circuit and the level shift circuit, and a bias circuit for generating a bias voltage in response to a power supply voltage to control the level shift circuit. The output voltage of the level shift circuit is not affected by fluctuations of the power supply voltage.

52. 发明授权

US08629797B2 Switched capacitor circuit and stage circuit for AD converter 有权
标题翻译：用于AD转换器的开关电容电路和电路电路
公开(公告)号：US08629797B2
公开(公告)日：2014-01-14
申请号：US13411018
申请日：2012-03-02
申请人： Kunihiko Gotoh
发明人： Kunihiko Gotoh
IPC分类号： H03M1/12
CPC分类号： H03M1/06 , H03M1/162 , H03M1/168
摘要： A switched capacitor circuit, which is operable in two or more kinds of operation modes including a first and second operation modes, includes an amplifier and two or more internal capacitors with switches for controlling connection/disconnection of the capacitor. In the first operation mode that precedes the second operation mode, the switched capacitor circuit generates the first analog output voltage by using the first internal capacitor connected between an input terminal and output terminal of the amplifier by using its switches, the other internal capacitances connected between an input terminal of the amplifier and each analog input voltage supply by using its switches. In the second operation mode, the switched capacitor circuit generates the second analog output voltage with larger feedback factor of the amplifier than it in the first operation mode, by removing some of the internal capacitors, except the first internal capacitor, from the first operation mode.
摘要翻译：可以在包括第一和第二操作模式的两种或多种操作模式中操作的开关电容器电路包括放大器和具有用于控制电容器的连接/断开的开关的两个或更多个内部电容器。在第二操作模式之前的第一操作模式中，开关电容器电路通过使用通过使用其开关连接在放大器的输入端子和输出端子之间的第一内部电容器来产生第一模拟输出电压，其他内部电容连接在放大器的输入端和使用其开关的每个模拟输入电压电源。在第二操作模式中，通过从第一操作模式除去第一内部电容器之外的一些内部电容器，除了第一操作模式之外，开关电容器电路产生具有比第一操作模式更大的反馈系数的第二模拟输出电压。

53. 发明授权

US07986258B2 Analog-digital conversion cell and analog-digital converter 失效
标题翻译：模拟数字转换单元和模拟数字转换器
公开(公告)号：US07986258B2
公开(公告)日：2011-07-26
申请号：US12698853
申请日：2010-02-02
申请人： Kunihiko Gotoh , Takeshi Takayama
发明人： Kunihiko Gotoh , Takeshi Takayama
IPC分类号： H03M1/12
CPC分类号： H03M1/0695 , H03M1/44
摘要： There is provided an analog-digital conversion cell being an analog-digital conversion cell that performs an N-bit analog-digital conversion (where N is a natural number) and including: a comparison circuit (202) comparing an analog input signal VI based on a plurality of reference voltages and outputting a first digital code DA selected from Q digital codes (where Q is a natural number equal to or more than 2N+1 and equal to or less than 2N+1−1) in accordance with a size of the analog input signal VI; a first logic operation circuit (203) outputting a second digital code DB selected from Q digital codes, which is expressed by DB=DA×KA+DB0 where a constant KA is a decimal number satisfying a condition of 1
摘要翻译：提供了一个模拟数字转换单元，其是执行N位模数转换（其中N是自然数）的模拟数字转换单元，包括：比较电路（202），用于比较模拟输入信号VI 在多个参考电压上输出从Q个数字码（其中Q是等于或大于2N + 1且等于或小于2N + 1-1的自然数）选择的第一数字码DA，根据大小的模拟输入信号VI; 输出选自Q数字代码的第二数字代码DB的第一逻辑运算电路（203），其由DB = DA×KA + DB0表示，其中常数KA是满足1

54. 发明申请

US20100013540A1 REFERENCE VOLTAGE GENERATING CIRCUIT 有权
标题翻译：参考电压发生电路
公开(公告)号：US20100013540A1
公开(公告)日：2010-01-21
申请号：US12566240
申请日：2009-09-24
申请人： Toshiharu TAKARAMOTO , Kunihiko Gotoh
发明人： Toshiharu TAKARAMOTO , Kunihiko Gotoh
IPC分类号： G06G7/18
CPC分类号： G05F3/30
摘要： There is provided a reference voltage generating circuit including: a first PN junction element (PN1) whose forward voltage is a first voltage V1; a second PN junction element (PN2) having a current density different from the first PN junction element and whose forward voltage is a second voltage V2 higher than the first voltage V1; and generating circuits (101 to 103) inputting the first voltage V1 and the second voltage V2 and generating a reference voltage expressed by A2×V2+A3×(A2×V2−A1×V1) in which A1, A2, and A3 are set to be coefficients, and in which A1 and A2 are different values.
摘要翻译：提供了一种参考电压产生电路，包括：第一PN结元件（PN1），其正向电压是第一电压V1; 具有不同于第一PN结元件的电流密度并且其正向电压是比第一电压V1高的第二电压V2的第二PN结元件（PN2）; 以及生成电路（101〜103），输入第一电压V1和第二电压V2，并生成由A2，V2，A3x（A2xV2-A1xV1）表示的基准电压，其中A1，A2和A3被设定为系数，其中 A1和A2是不同的值。

55. 发明申请

US20070045652A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20070045652A1
公开(公告)日：2007-03-01
申请号：US11362182
申请日：2006-02-27
申请人： Hajime Kurata , Kunihiko Gotoh
发明人： Hajime Kurata , Kunihiko Gotoh
IPC分类号： H01L33/00
CPC分类号： H01L27/0688 , H01L27/0802 , H01L27/0805 , H01L28/20 , H01L28/55 , H01L28/65
摘要： A semiconductor device is provided that includes a semiconductor substrate, a first resistance element on a semiconductor substrate, a capacitance element over the first resistance element, and an insulating layer between the first resistance element and the capacitance element.
摘要翻译：提供一种半导体器件，其包括半导体衬底，半导体衬底上的第一电阻元件，第一电阻元件上的电容元件以及第一电阻元件和电容元件之间的绝缘层。

56. 发明申请

US20060076837A1 Rectifier circuit 有权
标题翻译：整流电路
公开(公告)号：US20060076837A1
公开(公告)日：2006-04-13
申请号：US11062831
申请日：2005-02-23
申请人： Kunihiko Gotoh , Daisuke Yamazaki
发明人： Kunihiko Gotoh , Daisuke Yamazaki
IPC分类号： H03K3/00
CPC分类号： H03K17/302 , H02M7/217 , H03K17/063
摘要： Disclosed is a rectifier circuit that realizes a low threshold voltage without using a process step to enable reduction in cost and in variation of devices. An NMOS transistor has a threshold voltage. In the transistor, a voltage to be rectified is inputted to a second node, and a rectified voltage is outputted to a first node. A threshold voltage generator is connected to a gate of the transistor and the first node. The generator generates a voltage and outputs it to the gate of the transistor. The voltage is a voltage which is elevated by the threshold voltage with respect to a voltage of the first node and is decreased by a microvoltage sufficiently small with respect to the threshold voltage. Thus, when the voltage of the second node is decreased by the microvoltage or more with respect to that of the first node, the transistor is turned on.
摘要翻译：公开了一种整流电路，其实现低阈值电压，而不使用处理步骤来实现成本降低和设备变化。 NMOS晶体管具有阈值电压。在晶体管中，要整流的电压被输入到第二节点，并且将整流电压输出到第一节点。阈值电压发生器连接到晶体管和第一节点的栅极。发生器产生电压并将其输出到晶体管的栅极。电压是相对于第一节点的电压升高阈值电压的电压，并且相对于阈值电压减小足够小的微电压。因此，当第二节点的电压相对于第一节点的电压降低了微电压或更多时，晶体管导通。

57. 发明授权

US06998917B2 Common-mode feedback circuit and differential operational amplifier circuit having stable operation and low power consumption 失效
标题翻译：共模反馈电路和差分运算放大器电路，运算稳定，功耗低
公开(公告)号：US06998917B2
公开(公告)日：2006-02-14
申请号：US10777133
申请日：2004-02-13
申请人： Masahiro Kudo , Kunihiko Gotoh
发明人： Masahiro Kudo , Kunihiko Gotoh
IPC分类号： H03F3/45
CPC分类号： H03F3/45192 , H03F3/45659 , H03F3/45937 , H03F2203/45418
摘要： A common-mode feedback circuit outputs a control voltage to define a common-mode operating point of a fully differential amplifier. The common-mode feedback circuit has a voltage dividing circuit and a differential amplifier. The voltage dividing circuit divides a voltage across two output ends of the fully differential amplifier. The differential amplifier receives an output voltage of the voltage dividing circuit and a reference voltage, and an output voltage of the differential amplifier is supplied as the control voltage to the fully differential amplifier.
摘要翻译：共模反馈电路输出控制电压以定义全差分放大器的共模工作点。共模反馈电路具有分压电路和差分放大器。分压电路将全差分放大器的两个输出端分压。差分放大器接收分压电路的输出电压和参考电压，并将差分放大器的输出电压作为控制电压提供给全差分放大器。

58. 发明授权

US06740929B2 Semiconductor device and method for testing semiconductor device 有权
标题翻译：半导体器件和半导体器件测试方法
公开(公告)号：US06740929B2
公开(公告)日：2004-05-25
申请号：US10320420
申请日：2002-12-17
申请人： Makoto Koga , Kunihiko Gotoh , Kenichi Matsumaru , Mitsuya Kawata
发明人： Makoto Koga , Kunihiko Gotoh , Kenichi Matsumaru , Mitsuya Kawata
IPC分类号： H01L2900
CPC分类号： G11C29/26 , G11C8/12
摘要： A semiconductor device having at least three independently accessible memories, with at least one of the memories having a different memory capacity than the others. Separate selection signals are provided to the memories so that they can be independently activated. This allows the memories to be separately tested. When testing the semiconductor device, the memories are tested serially, except for the memory with the largest capacity, since this memory also has the longest test time. The memory with the longest test time is tested in parallel with the serially tested memories. This reduces the current that must be supplied by a test device to the semiconductor device during testing.
摘要翻译：具有至少三个可独立存取存储器的半导体器件，其中至少一个存储器具有与其它存储器不同的存储器容量。将独立的选择信号提供给存储器，使得它们可以被独立地激活。这允许记忆分开测试。当测试半导体器件时，除了具有最大容量的存储器之外，连续测试存储器，因为该存储器也具有最长的测试时间。具有最长测试时间的存储器与串行测试的存储器并行测试。这在测试期间将测试装置必须提供的电流减少到半导体器件。

59. 发明授权

US06646860B2 Capacitor and method for fabricating the same 有权
标题翻译：电容器及其制造方法
公开(公告)号：US06646860B2
公开(公告)日：2003-11-11
申请号：US10102798
申请日：2002-03-22
申请人： Toshiharu Takaramoto , Kunihiko Gotoh
发明人： Toshiharu Takaramoto , Kunihiko Gotoh
IPC分类号： H01G4228
CPC分类号： H01L27/0805 , H01L23/5222 , H01L28/40 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The capacitor comprises a lower layer electrode 22 formed on a substrate 10 with an inter-layer insulation film 12 therebetween; an upper layer electrode 24 opposed to the lower layer electrode 22 with an inter-layer insulation film 12 therebetween, a lower interconnection layer 14 formed between the substrate 10 and the lower layer electrode 22, and electrically connected to the upper layer electrode 24, whereby the parasitic capacitance, which is a cause for lower capacitor accuracy, useless power consumption, etc. can be drastically decreased, and external noises can be shielded off.
摘要翻译：电容器包括形成在基板10上的下层电极22，其间具有层间绝缘膜12; 与下层电极22相对的上层电极24，其间具有层间绝缘膜12，形成在基板10和下层电极22之间并与上层电极24电连接的下部布线层14，由此可以大大降低电容器精度降低，无用功耗等原因的寄生电容，能够遮蔽外部噪声。

60. 发明授权

US06307427B1 Filter characteristic regulating apparatus and regulating method therefor 失效
标题翻译：过滤特性调节装置及其调节方法
公开(公告)号：US06307427B1
公开(公告)日：2001-10-23
申请号：US09362707
申请日：1999-07-29
申请人： Hiroshi Yamazaki , Kazuaki Oishi , Kunihiko Gotoh
发明人： Hiroshi Yamazaki , Kazuaki Oishi , Kunihiko Gotoh
IPC分类号： H03K500
CPC分类号： H03L7/0805 , H03H11/04 , H03J7/02
摘要： A filter characteristic regulating apparatus for regulating a characteristic frequency of a filter device capable of regulating a characteristic frequency includes a measuring signal generator for generating a measuring signal having a known cycle of a response waveform when inputted to a filter device having a desired characteristic frequency, a selector for selecting and inputting this measuring signal to the filter device when the filter device is not used, a response waveform cycle measuring instrument for measuring the cycle of the response waveform of the input measuring signal to the filter device, and a controller for comparing the cycle of the response waveform measured by the response waveform cycle measuring instrument with a known response waveform cycle, and regulating the characteristic frequency of the filter device to a desired value on the basis of the comparison result. Because the measuring signal having a known cycle of the response waveform when inputted to the filter device is used in this way, the filter characteristic can be regulated without executing a complicated operation at the time of regulation. Therefore, this filter characteristic regulating apparatus can be assembled with the filter device in one semiconductor device.
摘要翻译：用于调节能够调节特征频率的滤波器的特征频率的滤波器特性调节装置包括：测量信号发生器，用于产生具有响应波形的已知周期的测量信号，该输入具有期望特性频率的滤波器装置，用于当不使用过滤装置时将该测量信号选择并输入到过滤装置的选择器，用于测量输入到过滤装置的测量信号的响应波形的周期的响应波形周期测量装置，以及用于比较由具有已知响应波形周期的响应波形周期测量仪测量的响应波形的周期，并且基于比较结果将滤波器件的特征频率调节到期望值。由于以这种方式使用具有响应波形的已知周期的测量信号，所以可以调节滤波器特性，而不会在调节时执行复杂的操作。因此，该滤波器特性调节装置可以与一个半导体装置中的过滤装置组装。

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