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51. 发明授权

US08900426B2 Double-layer shutter sputtering apparatus 有权
标题翻译：双层快门溅射装置
公开(公告)号：US08900426B2
公开(公告)日：2014-12-02
申请号：US13316927
申请日：2011-12-12
申请人： Shuji Nomura , Ayumu Miyoshi , Hiroshi Miki
发明人： Shuji Nomura , Ayumu Miyoshi , Hiroshi Miki
IPC分类号： C23C14/54 , C23C14/34
CPC分类号： C23C14/3464
摘要： A sputtering apparatus including a target holder configured to hold at least two targets; a substrate holder configured to hold a substrate; a first shutter plate arranged between the target holder and the substrate holder, the first shutter plate having at least two holes and being capable of rotating around an axis; a second shutter plate arranged between the first shutter plate and the substrate holder, the second shutter plate having at least two holes and being capable of rotating around the axis; wherein the first and second shutter plates are rotated such that paths are simultaneously created between the at least two targets and the substrate through the at least two holes of the rotated first shutter plate and the at least two holes of the rotated second shutter plate, and a film is formed on the substrate by co-sputtering of the at least two targets.
摘要翻译：一种溅射装置，包括被配置为保持至少两个靶的目标支架; 衬底保持器，其构造成保持衬底; 布置在所述目标保持器和所述基板保持器之间的第一挡板，所述第一挡板具有至少两个孔并且能够绕轴线旋转; 布置在所述第一活门板和所述衬底支架之间的第二活门板，所述第二活门板具有至少两个孔并能绕所述轴线旋转; 其中所述第一和第二快门板旋转，使得通过旋转的第一快门板的至少两个孔和旋转的第二快门板的至少两个孔同时在至少两个目标和基板之间产生通路，以及通过共溅射至少两个靶，在衬底上形成膜。

52. 发明申请

US20110022339A1 Method of Extracting A Time Constant From Complex Random Telegraph Signals 有权
标题翻译：从复杂随机电报信号中提取时间常数的方法
公开(公告)号：US20110022339A1
公开(公告)日：2011-01-27
申请号：US12506646
申请日：2009-07-21
申请人： Hiroshi MIKI
发明人： Hiroshi MIKI
IPC分类号： G06F17/18 , G01R13/00 , G06F19/00
CPC分类号： G01R31/275 , G01R31/2621 , G01R31/2626 , G01R31/2894
摘要： A method and apparatus for extracting a time constant from a time series of values of a signal that varies in accordance with multiple charge carrier trap defects that cause Random Telegraph Noise (RTN), using transition-based assignment of states.
摘要翻译：一种从基于过渡的状态分配的时间序列中提取时间常数的方法和装置，该时间常数是根据导致随机电报噪声（RTN）的多个电荷载流子陷阱缺陷而变化的信号值。

53. 发明授权

US07728376B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07728376B2
公开(公告)日：2010-06-01
申请号：US11723683
申请日：2007-03-21
申请人： Yuichi Matsui , Hiroshi Miki
发明人： Yuichi Matsui , Hiroshi Miki
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/10852 , H01L21/02175 , H01L21/022 , H01L21/02271 , H01L21/31641 , H01L21/31645 , H01L27/10814 , H01L27/10894 , H01L28/91
摘要： HfO2 films and ZrO2 films are currently being developed for use as capacitor dielectric films in 85 nm technology node DRAM. However, these films will be difficult to use in 65 nm technology node or later DRAM, since they have a relative dielectric constant of only 20-25. The dielectric constant of such films may be increased by stabilizing their cubic phase. However, this results in an increase in the leakage current along the crystal grain boundaries, which makes it difficult to use these films as capacitor dielectric films. To overcome this problem, the present invention dopes a base material of HfO2 or ZrO2 with an oxide of an element having a large ion radius, such as Y or La, to increase the oxygen coordination number of the base material and thereby increase its relative dielectric constant to 30 or higher even when the base material is in its amorphous state. Thus, the present invention provides dielectric films that can be used to form DRAM capacitors that meet the 65 nm technology node or later.
摘要翻译：目前，HfO2薄膜和ZrO2薄膜正在开发中用作85纳米技术节点DRAM中的电容器介质薄膜。然而，这些膜将难以在65nm技术节点或之后的DRAM中使用，因为它们的相对介电常数只有20-25。这些膜的介电常数可以通过稳定它们的立方相来增加。然而，这导致沿着晶粒边界的漏电流的增加，这使得难以将这些膜用作电容器电介质膜。为了克服这个问题，本发明通过具有大离子半径的元素的氧化物如Y或La掺杂HfO 2或ZrO 2的基材，以增加基材的氧配位数，从而增加其相对电介质即使当基材处于其非晶态时，其也恒定在30或更高。因此，本发明提供可用于形成满足65nm技术节点或更高版本的DRAM电容器的电介质膜。

54. 发明授权

US07709315B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07709315B2
公开(公告)日：2010-05-04
申请号：US11773842
申请日：2007-07-05
申请人： Naoki Tega , Hiroshi Miki , Yasuhiro Shimamoto , Digh Hisamoto , Tetsuya Ishimaru
发明人： Naoki Tega , Hiroshi Miki , Yasuhiro Shimamoto , Digh Hisamoto , Tetsuya Ishimaru
IPC分类号： H01L21/8238
CPC分类号： H01L29/792 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L27/11573 , H01L29/42324 , H01L29/4234 , H01L29/42344 , H01L29/66833
摘要： An interface between a bottom oxide film and a silicon nitride film in a neighborhood of a bottom part of a select gate is located at a position as high as or higher than that of an interface between a silicon substrate (p-type well) and a gate insulating film (d≧0) Further, the gate insulating film and the bottom oxide film are successively and smoothly jointed in the neighborhood of the bottom part of the select gate. By this configuration, localization in a distribution of electrons injected into the silicon nitride film in the writing is mitigated and electrons to be left unerased by hot-hole erasing are reduced. Therefore, not only the increase ratio of the electrons left unerased in the writing can be reduced, but also the problem in which the threshold voltage does not decrease to the predetermined voltage in the deletion can be suppressed.
摘要翻译：在选择栅极的底部附近的底部氧化物膜和氮化硅膜之间的界面位于硅衬底（p型阱）和硅衬底（p型阱）之间的界面的高度或更高的位置栅极绝缘膜（d≥0）此外，栅极绝缘膜和底部氧化物膜在选择栅极的底部附近依次平滑地接合。通过这种配置，减轻了在写入中注入到氮化硅膜中的电子分布中的定位，并且减少了通过热孔擦除而未被消除的电子。因此，不仅可以减少在写入时未加电的电子的增加比例，还可以抑制在删除中阈值电压不降低到预定电压的问题。

55. 发明授权

US07364965B2 Semiconductor device and method of fabrication 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07364965B2
公开(公告)日：2008-04-29
申请号：US10986497
申请日：2004-11-12
申请人： Osamu Tonomura , Hiroshi Miki , Yuichi Matsui , Tomoko Sekiguchi , Kikuo Watanabe
发明人： Osamu Tonomura , Hiroshi Miki , Yuichi Matsui , Tomoko Sekiguchi , Kikuo Watanabe
IPC分类号： H01L21/8242
CPC分类号： H01L21/02178 , H01L21/02181 , H01L21/02197 , H01L21/0228 , H01L21/02282 , H01L21/02337 , H01L21/02356 , H01L21/3141 , H01L21/3162 , H01L21/31645 , H01L27/1085 , H01L27/10855 , H01L28/65
摘要： A semiconductor device having a DRAM has a capacitor in which a dielectric film and an upper electrode are laminated on a lower electrode comprising a polysilicone, in which a natural oxide film oxidized by oxygen in the atmosphere grows to at least 1.5 nm on the surface of a lower electrode of the capacitor. Further, in forming the dielectric film, the dioxide film further grows in the case of using an oxidative raw material. This brings forth a reduction in capacitance, and an increase of a leakage current is caused.Therefore, after a dielectric film having a reduction property has been formed, the reduction property is promoted by a heat treatment to thereby reduce a dioxide film and realize making the dioxide film on the lower electrode surface thinner.
摘要翻译：具有DRAM的半导体器件具有电容器，其中电介质膜和上电极层压在包含聚硅氧烷的下电极上，其中在大气中的氧气氧化的天然氧化物膜在其表面上生长至少至少1.5nm 电容器的下电极。此外，在形成电介质膜时，在使用氧化性原料的情况下，二氧化硅膜进一步生长。这导致电容的减小，并且引起漏电流的增加。因此，在形成具有还原性的电介质膜之后，通过热处理促进还原性能，从而减少二氧化膜，实现使下电极表面上的二氧化物膜更薄。

56. 发明申请

US20060125048A1 Integrated semiconductor device and method of manufacturing the same 审中-公开
标题翻译：集成半导体器件及其制造方法
公开(公告)号：US20060125048A1
公开(公告)日：2006-06-15
申请号：US11196421
申请日：2005-08-04
申请人： Hiroshi Miki
发明人： Hiroshi Miki
IPC分类号： H01L29/00
CPC分类号： H01L21/022 , H01L21/02178 , H01L21/02183 , H01L21/02266 , H01L21/02271 , H01L21/02274 , H01L21/0228 , H01L21/31604 , H01L21/31616 , H01L21/76838 , H01L27/0805 , H01L28/56 , H01L28/90
摘要： An integrated semiconductor device comprising an analog integrated circuit or mixed signal integrated circuit having a capacitor, wherein the dielectric film of the capacitor is a laminated film consisting of a first dielectric film essentially composed of aluminum oxide and a second dielectric film essentially composed of crystallized niobium oxide. This integrated semiconductor device is small in size and has a low temperature coefficient and high reliability. The niobium oxide is crystallized to increase its dielectric constant and reduce its loss. To reduce the temperature coefficient, the film thickness ratio of the aluminum oxide layer to the niobium oxide layer is set to 0.2 to 1, preferably 0.4 to 0.7.
摘要翻译：一种集成半导体器件，包括具有电容器的模拟集成电路或混合信号集成电路，其中电容器的电介质膜是由基本上由氧化铝组成的第一电介质膜和基本上由结晶铌组成的第二电介质膜构成的层压膜氧化物。该集成半导体器件尺寸小，温度系数低，可靠性高。氧化铌结晶以增加其介电常数并降低其损耗。为了降低温度系数，将氧化铝层与氧化铌层的膜厚比设定为0.2〜1，优选为0.4〜0.7。

57. 发明授权

US06818523B2 Semiconductor storage device manufacturing method which forms a hydrogen diffusion inhibiting layer 失效
标题翻译：形成氢扩散抑制层的半导体存储装置的制造方法
公开(公告)号：US06818523B2
公开(公告)日：2004-11-16
申请号：US10602644
申请日：2003-06-25
申请人： Hiroshi Miki , Keiko Kushida , Yasuhiro Shimamoto , Shinichiro Takatani , Yoshihisa Fujisaki , Hiromi Nakai
发明人： Hiroshi Miki , Keiko Kushida , Yasuhiro Shimamoto , Shinichiro Takatani , Yoshihisa Fujisaki , Hiromi Nakai
IPC分类号： Y01L2120
CPC分类号： H01L28/75 , H01L28/55 , H01L28/57 , H01L28/60
摘要： A method for forming a semiconductor storage device includes steps of forming a memory cell transistor, forming a first plug connected to the memory cell transistor, forming a second plug of a hydrogen diffusion inhibiting layer, forming capacitor electrodes and a capacitor insulator between the capacitor electrodes and forming a hydrogen adsorption inhibiting layer.
摘要翻译：一种形成半导体存储装置的方法，包括：形成存储单元晶体管，形成连接到存储单元晶体管的第一插头，形成氢扩散抑制层的第二插头，在电容器电极之间形成电容器电极和电容器绝缘体并形成氢吸附抑制层。

58. 发明授权

US06740901B2 Production of semiconductor integrated circuit 失效
标题翻译：生产半导体集成电路
公开(公告)号：US06740901B2
公开(公告)日：2004-05-25
申请号：US10307354
申请日：2002-12-02
申请人： Hiroshi Miki , Yasuhiro Shimamoto , Masahiko Hiratani , Tomoyuki Hamada
发明人： Hiroshi Miki , Yasuhiro Shimamoto , Masahiko Hiratani , Tomoyuki Hamada
IPC分类号： H01L27108
CPC分类号： H01L28/84 , H01L27/10814 , H01L28/91
摘要： A semiconductor integrated circuit in which the storage capacitor has an increased capacitance and a decreased leakage current. The storage capacitor is formed by the steps of: forming a polysilicon bottom electrode having semispherical silicon crystals formed thereon; performing plasma nitriding on the surface of said bottom electrode at a temperature lower than 550° C., thereby forming a film of silicon nitride having a film thickness smaller than 1.5 nm; and depositing a film of amorphous tantalum pentoxide and then crystallizing said amorphous tantalum pentoxide. The silicon nitride film has improved resistance to oxidation and also has a reduced leakage current. As a result, the polysilicon bottom electrode becomes resistant to oxidation and the storage capacitor increases in capacitance and decreases in leakage current.
摘要翻译：一种半导体集成电路，其中存储电容器具有增加的电容和减小的漏电流。存储电容器通过以下步骤形成：形成其上形成有半球形硅晶体的多晶硅底电极; 在低于550℃的温度下在所述底部电极的表面上进行等离子体氮化，从而形成膜厚度小于1.5nm的氮化硅膜; 并沉积无定形钽五氧化物膜，然后使所述无定形五氧化钽结晶。氮化硅膜具有改善的抗氧化性，并且还具有减小的漏电流。结果，多晶硅底部电极变得耐氧化，并且存储电容器增加电容并且减小漏电流。

59. 发明授权

US06693792B2 Semiconductor integrated circuits and fabricating method thereof 失效
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06693792B2
公开(公告)日：2004-02-17
申请号：US10411282
申请日：2003-04-11
申请人： Yasuhiro Shimamoto , Hiroshi Miki , Masahiko Hiratani
发明人： Yasuhiro Shimamoto , Hiroshi Miki , Masahiko Hiratani
IPC分类号： H01G406
CPC分类号： H01L28/40 , H01L21/31604 , H01L27/10814 , H01L28/56 , H01L28/84 , H01L28/90
摘要： A capacitor having an equivalent thickness of 3.0 nm or less, with a sufficient static capacitance and less leakage current in a reduced size, constituted by stacking an interfacial film 21 having a physical thickness of 2.5 nm or more for suppressing tunnel leakage current and a high dielectric film 22 comprising tantalum pentaoxide on lower electrode 19, 20 comprising rugged polycrystal silicon film, the interfacial film 21 comprising a nitride film formed by an LPCVD method, for example, from Al2O3, a mixed phase of Al2O3 and SiO2, ZrSiO4, HfSiO4, a mixed phase of Y2O3 and SiO2, and a mixed phase of La2O3 and SiO2.
摘要翻译：具有3.0nm以下的等效厚度的电容器，具有足够的静电容量和较小的漏电流，通过堆叠具有2.5nm或更大的物理厚度的界面膜21来构成，用于抑制隧道漏电流和高介电膜22包括在下电极19上的五氧化钽，20，包括粗糙多晶硅膜，界面膜21包括通过LPCVD法形成的氮化物膜，例如Al2O3，Al2O3和SiO2的混合相，ZrSiO4，HfSiO4， Y2O3和SiO2的混合相以及La2O3和SiO2的混合相。

60. 发明授权

US06396092B1 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06396092B1
公开(公告)日：2002-05-28
申请号：US09381396
申请日：1999-09-20
申请人： Shinichiro Takatani , Hiroshi Miki , Keiko Kushida , Yoshihisa Fujisaki , Kazuyoshi Torii
发明人： Shinichiro Takatani , Hiroshi Miki , Keiko Kushida , Yoshihisa Fujisaki , Kazuyoshi Torii
IPC分类号： H01L2906
CPC分类号： H01L28/55 , H01L28/60
摘要： A semiconductor device includes a capacitor having a lower electrode (102), a high-dielectric-constant or ferroelectric thin film (103), and an upper electrode (104) which are subsequently stacked. An impurity having an action of suppressing the catalytic activity of a metal or a conductive oxide constituting the electrode is added to the upper electrode (104). The addition of the impurity is effective to prevent inconveniences such as a reduction in capacitance, an insulation failure, and the peeling of the electrode due to hydrogen heat-treatment performed after formation of the upper electrode (104), and to improve the long-term reliability.
摘要翻译：半导体器件包括随后堆叠的具有下电极（102），高介电常数或铁电薄膜（103）和上电极（104）的电容器。具有抑制构成电极的金属或导电氧化物的催化活性的作用的杂质被添加到上电极（104）。杂质的添加对于防止在形成上电极（104）之后进行的氢热处理等电容的减少，绝缘失效以及电极的剥离等不良情况是有效的，长期可靠性。

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