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51. 发明授权

US07487480B1 Method for estimating aggregate leakage of transistors 失效
标题翻译：估计晶体管漏电的方法
公开(公告)号：US07487480B1
公开(公告)日：2009-02-03
申请号：US12118857
申请日：2008-05-12
申请人： Bhavna Agrawal , David J. Hathaway , Peng Peng
发明人： Bhavna Agrawal , David J. Hathaway , Peng Peng
IPC分类号： G06F17/50 , G06F17/17 , G06F17/11
CPC分类号： G06F17/5036
摘要： A method of estimating a leakage for a plurality of transistors in an integrated circuit that accounts for narrow channel effects includes determining an expected total leaking transistor width for the collection; determining an expected total number of leaking transistors for the collection; determining an average width of a leaking transistor from the expected total leaking transistor width and expected total number of leaking transistors; estimating a leakage for a transistor of the average width; and determining the estimated leakage for the collection of transistors by multiplying the leakage for a transistor of the average width by the expected total number of leaking transistors for the collection.
摘要翻译：估计考虑窄通道效应的集成电路中的多个晶体管的泄漏的方法包括确定用于采集的预期的总泄漏晶体管宽度; 确定用于收集的泄漏晶体管的预期总数; 从预期的总泄漏晶体管宽度和预期的泄漏晶体管总数确定泄漏晶体管的平均宽度; 估计平均宽度的晶体管的泄漏; 并且通过将用于平均宽度的晶体管的泄漏乘以用于集合的预期泄漏晶体管总数来确定用于收集晶体管的估计泄漏。

52. 发明申请

US20080195993A1 Method of Generating Wiring Routes with Matching Delay in the Presence of Process Variation 有权
标题翻译：在过程变化存在下生成具有匹配延迟的接线路由的方法
公开(公告)号：US20080195993A1
公开(公告)日：2008-08-14
申请号：US12107158
申请日：2008-04-22
申请人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.
摘要翻译：电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且在第一布线路径和第二布线路径横越的各布线层内。此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。

53. 发明申请

US20080134117A1 SYSTEM AND METHOD FOR EFFICIENT ANALYSIS OF POINT-TO-POINT DELAY CONSTRAINTS IN STATIC TIMING 失效
标题翻译：点对点延迟约束在静态时序中有效分析的系统与方法
公开(公告)号：US20080134117A1
公开(公告)日：2008-06-05
申请号：US11565803
申请日：2006-12-01
申请人： Kerim Kalafala , Revanta Banerji , David J. Hathaway , Jessica Sheridan , Chandramouli Visweswariah
发明人： Kerim Kalafala , Revanta Banerji , David J. Hathaway , Jessica Sheridan , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and a system for conducting a static timing analysis on a circuit having a plurality of point-to-point delay constraints between two points of the circuit, in which two conservative and two optimistic user defined tests are derived for all types of the point-to-point delay constraints. The method shows that when a conservative test is performed without introducing any special tags, then it is found that the point-to-point constraint is satisfied. On the other hand, when the optimistic test fails without any special tags, it is determined that the point-to-point constraint is bound to fail if special tags are introduced, in which case, they are to be introduced only when an exact slack is desired. Finally, for anything in between, a real analysis with special tags or path tracing is required. Based on the topology of the graph, arrival time based tests may be tighter in some situations, while the required arrival time based tests, may be tighter in others.
摘要翻译：一种用于在电路的两个点之间具有多个点到点延迟约束的电路上执行静态时序分析的方法和系统，其中针对所有类型的点导出两个保守和两个乐观用户定义的测试到点延迟约束。该方法表明，当进行保守测试而不引入任何特殊标签时，发现点对点约束得到满足。另一方面，当乐观测试失败而没有任何特殊标签时，如果引入特殊标签，则确定点对点约束必然会失败，在这种情况下，仅当确切的松弛时才引入它们是希望的。最后，对于两者之间的任何东西，需要使用特殊标签或路径跟踪进行真正的分析。基于图形的拓扑结构，在某些情况下，基于到达时间的测试可能更紧密，而所需到达时间的测试可能在其他情况下更严格。

54. 发明申请

US20070277131A1 METHOD FOR A FAST INCREMENTAL CALCULATION OF THE IMPACT OF COUPLED NOISE ON TIMING 有权
标题翻译：快速计算耦合噪声对时序影响的方法
公开(公告)号：US20070277131A1
公开(公告)日：2007-11-29
申请号：US11420529
申请日：2006-05-26
申请人： Gregory M. Schaeffer , Alexander J. Suess , David J. Hathaway
发明人： Gregory M. Schaeffer , Alexander J. Suess , David J. Hathaway
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036
摘要： A method for incrementally calculating the impact of coupling noise on the timing of an integrated circuit (IC) having a plurality of logic stages by performing an initial timing analysis on the IC to provide a first determination of the impact of coupling noise on the timing. One or more design changes to the IC are then performed. In response to the design change, the impact of the coupling noise to the timing is calculated on the logic stage where the change was made and on the logic stages downstream thereof. The results of the calculations are then inputted to a timing analysis tool to adjust the delay and slew of each logic stage where the design change was made and to the logic stages downstream thereof.
摘要翻译：一种用于通过对IC执行初始定时分析来递增地计算耦合噪声对具有多个逻辑级的集成电路（IC）的定时的影响的方法，以提供耦合噪声对定时的影响的第一确定。然后执行对IC的一个或多个设计更改。响应于设计变化，耦合噪声对定时的影响是在进行改变的逻辑阶段和下游的逻辑级上计算的。然后将计算结果输入到定时分析工具，以调整进行设计更改的每个逻辑级的延迟和转换以及其下游的逻辑级。

55. 发明授权

US07142991B2 Voltage dependent parameter analysis 有权
标题翻译：电压相关参数分析
公开(公告)号：US07142991B2
公开(公告)日：2006-11-28
申请号：US11095327
申请日：2005-03-31
申请人： David J. Hathaway , Douglas W. Stout , Ivan L. Wemple
发明人： David J. Hathaway , Douglas W. Stout , Ivan L. Wemple
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of, and a system for, determining an extreme value of a voltage dependent parameter of an integrated circuit design is provided. The method includes determining a plurality of current waveforms, each of the plurality of waveforms corresponding to one of a plurality of aggressor objects in the design of the integrated circuit; applying each of the plurality of current waveforms to a subset of the plurality of power bus nodes, the subset of the plurality of power bus nodes being designed to supply power to a corresponding one of the plurality of aggressor objects; determining a plurality of voltage waveforms, each of the plurality of voltage waveforms being at one of the plurality of power bus nodes and corresponding to one of the plurality of current waveforms; using the plurality of voltage waveforms to determine the extreme value.
摘要翻译：提供了一种用于确定集成电路设计的电压相关参数的极值的方法和系统。所述方法包括确定多个电流波形，所述多个波形中的每一个对应于所述集成电路的设计中的多个侵略对象中的一个; 将所述多个电流波形中的每一个应用于所述多个电力总线节点的子集，所述多个电力总线节点的子集被设计为向所述多个侵权者对象中的相应一个提供电力; 确定多个电压波形，所述多个电压波形中的每一个在所述多个电力总线节点中的一个处并且对应于所述多个电流波形中的一个; 使用多个电压波形来确定极值。

56. 发明授权

US06986090B2 Method for reducing switching activity during a scan operation with limited impact on the test coverage of an integrated circuit 失效
公开(公告)号：US06986090B2
公开(公告)日：2006-01-10
申请号：US10078876
申请日：2002-02-20
申请人： David J. Hathaway , Brion L. Keller
发明人： David J. Hathaway , Brion L. Keller
IPC分类号： G01R31/28
CPC分类号： G01R31/318536 , G01R31/318583
摘要： A method for reducing the switching activity during both scan-in and scan-out operations of an integrated circuit with reduced detrimental effect on test pattern effectiveness and test time is described. The method makes use of a sample set of patterns to determine the probabilities of same and opposite relationships between stimulus and result values, and uses these probabilities to determine memory element pair compatibilities. Scan chains are ordered preferentially by connecting adjacently compatible memory elements, and inversions are inserted between selected memory element pairs based on those probabilities. Unspecified stimulus bits are filled in to reduce the switching activity based on the scan chain ordering and inversions.

57. 发明授权

US06751744B1 Method of integrated circuit design checking using progressive individual network analysis 有权
标题翻译：集成电路设计检查方法采用渐进式单独网络分析
公开(公告)号：US06751744B1
公开(公告)日：2004-06-15
申请号：US09475799
申请日：1999-12-30
申请人： Robert J. Allen , John M. Cohn , David J. Hathaway
发明人： Robert J. Allen , John M. Cohn , David J. Hathaway
IPC分类号： G06F112
CPC分类号： G06F17/504 , G06F2217/78
摘要： A method for checking integrated circuit designs comprising the steps of calculating a first performance parameter by analyzing the network's sensitivity to a signal applied to the network; comparing the first performance parameter to one or more rules to determine a first pass condition and writing the value of first performance parameter to a netlist file in response to a pass to the first pass condition; followed by calculating a second performance parameter based on a first network model to determine a second pass condition in response to a fail to said first pass condition and writing the second performance parameter to the netlist file in response to a pass to said second pass condition or writing an error flag to the netlist file in response to a fail to said second pass condition is disclosed. The method, at each step, decides if a quick to calculate parameter provides sufficient design margin or if a more accurate but longer to calculate parameter is required.
摘要翻译：一种用于检查集成电路设计的方法，包括以下步骤：通过分析网络对施加到网络的信号的灵敏度来计算第一性能参数; 将所述第一性能参数与一个或多个规则进行比较以确定第一通过条件，并响应于所述第一通过条件的传递将所述第一性能参数的值写入网表文件; 随后基于第一网络模型计算第二性能参数，以响应于所述第一通过条件的失败来确定第二通过条件，并响应于所述第二通过条件的通过将所述第二性能参数写入所述网表文件，或公开了响应于所述第二通过条件的失败向网表文件写入错误标志。该方法在每个步骤中决定快速计算参数是否提供足够的设计余量，或者是否需要更准确但更长的计算参数。

58. 发明授权

US06687883B2 System and method for inserting leakage reduction control in logic circuits 有权
标题翻译：用于在逻辑电路中插入泄漏减少控制的系统和方法
公开(公告)号：US06687883B2
公开(公告)日：2004-02-03
申请号：US09750969
申请日：2000-12-28
申请人： John M. Cohn , Alvar A. Dean , David J. Hathaway , Sebastian T. Ventrone
发明人： John M. Cohn , Alvar A. Dean , David J. Hathaway , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F1/3243 , G06F1/3203 , Y02D10/152 , Y02D50/20
摘要： A method for reducing leakage power of a logic network comprising the steps of: using (observability) don't care information to identify “sleep states” for individual nets; determining based on probabilistic analysis at least one net in which expected power consumption will be reduced by forcing a net to a particular value during at least a portion of a “sleep state”; and forcing the determined net to the determined value determined portion of that “sleep state”.
摘要翻译：一种用于减少逻辑网络的泄漏功率的方法，包括以下步骤：使用（可观察性）不关心信息以识别各个网络的“睡眠状态”; 基于概率分析确定至少一个网络，其中通过在“睡眠状态”的至少一部分期间将网络强制为特定值来减少预期功率消耗; 并将所确定的网络强制为所述“睡眠状态”的确定值确定部分。

59. 发明申请

US20120124534A1 System and Method for Performing Static Timing Analysis in the Presence of Correlations Between Asserted Arrival Times 失效
标题翻译：在断定到达时间之间相关性的情况下执行静态时序分析的系统和方法
公开(公告)号：US20120124534A1
公开(公告)日：2012-05-17
申请号：US12944059
申请日：2010-11-11
申请人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Jeffrey G. Hemmett , Peihua Qi , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Jeffrey G. Hemmett , Peihua Qi , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F2217/84
摘要： A method of applying common path credit in a static timing analysis in the presence of correlations between asserted arrival times, comprising the steps of using a computer, identifying one or more pairs of asserted arrival times for which one or more correlations exist; propagating to each of the one or more pairs of asserted arrival times a timing value dependent on the one or more correlations; and performing a subsequent common path pessimism removal analysis for at least one test during which a timing value dependent on the one or more correlations between asserted arrival times is used to compute an adjusted test slack.
摘要翻译：一种在断言到达时间之间的相关性存在的静态时序分析中应用公共路径信用的方法，包括以下步骤：使用计算机识别存在一个或多个相关性的一个或多个断言到达时间对; 将所述一个或多个断言到达时间对中的每一个传播到取决于所述一个或多个相关性的定时值; 以及对至少一个测试执行随后的公共路径悲观消除分析，在该测试期间，使用取决于所述到达时间之间的一个或多个相关性的定时值来计算经调整的测试松弛。

60. 发明授权

US07962874B2 Method and system for evaluating timing in an integrated circuit 有权
标题翻译：用于评估集成电路中的定时的方法和系统
公开(公告)号：US07962874B2
公开(公告)日：2011-06-14
申请号：US12183549
申请日：2008-07-31
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G01R31/3016
摘要： Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.
摘要翻译：用于分析集成电路中的定时并减少静态时序分析（STA）中定时松弛计算中的悲观情况的方法。该方法涉及分组和消除在早期和晚期电路路径中具有类似延迟的元件的延迟贡献。使用具有不同延迟的元件的延迟贡献来计算调整的定时松弛。在一些实施例中，具有不同延迟的元件的延迟贡献是根和平方。本发明的实施例提供了用于减少由于基于单元和线依赖的延迟引起的悲观的方法。在本发明的实施例中考虑的延迟可以包括由于路径中的元件的位置而导致的延迟。

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