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51. 发明申请

US20110078418A1 Support for Non-Local Returns in Parallel Thread SIMD Engine 有权
标题翻译：支持并行线程SIMD引擎中的非本地返回
公开(公告)号：US20110078418A1
公开(公告)日：2011-03-31
申请号：US12881065
申请日：2010-09-13
申请人： Guillermo Juan Rozas , Brett W. Coon
发明人： Guillermo Juan Rozas , Brett W. Coon
IPC分类号： G06F9/38
CPC分类号： G06F9/30058 , G06F9/3851
摘要： One embodiment of the present invention sets forth a method for executing a non-local return instruction in a parallel thread processor. The method comprises the steps of receiving, within the thread group, a first long jump instruction and, in response, popping a first token from the execution stack. The method also comprises determining whether the first token is a first long jump token that was pushed onto the execution stack when a first push instruction associated with the first long jump instruction was executed, and when the first token is the first long jump token, jumping to the second instruction based on the address specified by the first long jump token, or, when the first token is not the first long jump token, disabling the active thread until the first long jump token is popped from the execution stack.
摘要翻译：本发明的一个实施例提出了一种用于在并行线程处理器中执行非本地返回指令的方法。该方法包括以下步骤：在线程组内接收第一长跳转指令，作为响应，从执行堆栈中弹出第一个令牌。该方法还包括当与第一长跳转指令相关联的第一推送指令被执行时，确定第一令牌是否是被推送到执行堆栈上的第一长跳转令牌，以及当第一令牌是第一长跳转令牌时，跳转基于由第一长跳转令牌指定的地址到第二指令，或者当第一令牌不是第一长跳转令牌时，禁用活动线程，直到从执行堆栈弹出第一个长跳转令牌。

52. 发明申请

US20110078406A1 Unified Addressing and Instructions for Accessing Parallel Memory Spaces 有权
标题翻译：统一寻址和访问并行内存空间的说明
公开(公告)号：US20110078406A1
公开(公告)日：2011-03-31
申请号：US12567637
申请日：2009-09-25
申请人： John R. Nickolls , Brett W. Coon , Ian A. Buck , Robert Steven Glanville
发明人： John R. Nickolls , Brett W. Coon , Ian A. Buck , Robert Steven Glanville
IPC分类号： G06F12/10
CPC分类号： G06F12/1054 , G06F12/0284 , G06F12/109 , G06F13/404 , G06F2212/302 , G06F2212/656
摘要： One embodiment of the present invention sets forth a technique for unifying the addressing of multiple distinct parallel memory spaces into a single address space for a thread. A unified memory space address is converted into an address that accesses one of the parallel memory spaces for that thread. A single type of load or store instruction may be used that specifies the unified memory space address for a thread instead of using a different type of load or store instruction to access each of the distinct parallel memory spaces.
摘要翻译：本发明的一个实施例提出了一种用于将多个不同的并行存储器空间的寻址统一为用于线程的单个地址空间的技术。统一的存储空间地址被转换为访问该线程的并行存储器空间之一的地址。可以使用单一类型的加载或存储指令，其指定线程的统一存储器空间地址，而不是使用不同类型的加载或存储指令来访问每个不同的并行存储器空间。

53. 发明申请

US20110072244A1 Credit-Based Streaming Multiprocessor Warp Scheduling 有权
标题翻译：基于信用流的多处理器整流器调度
公开(公告)号：US20110072244A1
公开(公告)日：2011-03-24
申请号：US12885299
申请日：2010-09-17
申请人： John Erik Lindholm , Brett W. Coon , Jered Wierzbicki , Robert J. Stoll , Stuart F. Oberman
发明人： John Erik Lindholm , Brett W. Coon , Jered Wierzbicki , Robert J. Stoll , Stuart F. Oberman
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/3851 , G06F9/3836 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： One embodiment of the present invention sets forth a technique for ensuring cache access instructions are scheduled for execution in a multi-threaded system to improve cache locality and system performance. A credit-based technique may be used to control instruction by instruction scheduling for each warp in a group so that the group of warps is processed uniformly. A credit is computed for each warp and the credit contributes to a weight for each warp. The weight is used to select instructions for the warps that are issued for execution.
摘要翻译：本发明的一个实施例提出了一种用于确保高速缓存访问指令被调度用于在多线程系统中执行以提高高速缓存位置和系统性能的技术。可以使用基于信用的技术来对组中的每个翘曲的指令调度来控制指令，使得一组经线被均匀地处理。对每个经纱计算信用额度，并且信用额度有助于每个经线的权重。权重用于选择要执行的经线的指令。

54. 发明授权

US07864185B1 Register based queuing for texture requests 有权
标题翻译：基于注册排队的纹理请求
公开(公告)号：US07864185B1
公开(公告)日：2011-01-04
申请号：US12256848
申请日：2008-10-23
申请人： John Erik Lindholm , John R. Nickolls , Simon S. Moy , Brett W. Coon
发明人： John Erik Lindholm , John R. Nickolls , Simon S. Moy , Brett W. Coon
IPC分类号： G06T11/40 , G06T15/00 , G06T15/20 , G06T1/00
CPC分类号： G06T11/60 , G09G5/363
摘要： A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.
摘要翻译：图形处理单元可以排队大量纹理请求，以平衡纹理请求的可变性，而不需要大的纹理请求缓冲区。专用纹理请求缓冲区排队相对较小的纹理命令和参数。另外，对于每个排队的纹理命令，通常比纹理命令大得多的一组相关的纹理参数存储在通用寄存器中。纹理单元从纹理请求缓冲区中检索纹理命令，然后从相应的通用寄存器获取相关的纹理参数。纹理参数可以存储在指定为由纹理单元计算的最终纹理值的目的地的通用寄存器中。因为当纹理命令排队时，必须为目标寄存器分配最终纹理值，所以将纹理参数存储在该寄存器中不消耗任何其他寄存器。

55. 发明授权

US07805573B1 Multi-threaded stack cache 有权
标题翻译：多线程堆栈缓存
公开(公告)号：US07805573B1
公开(公告)日：2010-09-28
申请号：US11313448
申请日：2005-12-20
申请人： Brett W. Coon
发明人： Brett W. Coon
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0875 , G06F12/0842
摘要： Systems and methods for storing stack data for multi-threaded processing in a specialized cache reduce on-chip memory requirements while maintaining low access latency. An on-chip stack cache is used store a predetermined number of stack entries for a thread. When additional entries are needed for the thread, entries stored in the stack cache are spilled, i.e., moved, to remote memory. As entries are popped off the on-chip stack cache, spilled entries are restored from the remote memory. The spilling and restoring processes may be performed while the on-chip stack cache is accessed. Therefore, a large stack size is supported using a smaller amount of die area than that needed to store the entire large stack on-chip. The large stack may be accessed without incurring the latency of reading and writing to remote memory since the stack cache is preemptively spilled and restored.
摘要翻译：用于在专用高速缓存中存储用于多线程处理的堆栈数据的系统和方法降低了片上存储器需求，同时保持低访问延迟。使用片上堆栈高速缓存来存储线程的预定数量的堆栈条目。当线程需要额外的条目时，存储在堆栈高速缓存中的条目将被溢出，即移动到远程存储器。当条目从片上堆栈高速缓存中弹出时，从远程存储器恢复溢出的条目。可以在访问片上堆栈高速缓存时执行溢出和恢复过程。因此，使用比存储芯片上整个大堆栈所需的更小的管芯面积来支持大的堆叠尺寸。可以访问大堆栈，而不会导致读取和写入远程内存的延迟，因为堆栈高速缓存被抢先溢出并恢复。

56. 发明授权

US07711990B1 Apparatus and method for debugging a graphics processing unit in response to a debug instruction 有权
标题翻译：响应于调试指令调试图形处理单元的装置和方法
公开(公告)号：US07711990B1
公开(公告)日：2010-05-04
申请号：US11302952
申请日：2005-12-13
申请人： John R. Nickolls , Roger L. Allen , Brian K. Cabral , Brett W. Coon , Robert C. Keller
发明人： John R. Nickolls , Roger L. Allen , Brian K. Cabral , Brett W. Coon , Robert C. Keller
IPC分类号： G06F11/00
CPC分类号： G06F11/3648
摘要： A system includes a graphics processing unit with a processor responsive to a debug instruction that initiates the storage of execution state information. A memory stores the execution state information. A central processing unit executes a debugging program to analyze the execution state information.
摘要翻译：系统包括具有处理器的图形处理单元，该处理器响应于启动执行状态信息的存储的调试指令。存储器存储执行状态信息。中央处理单元执行调试程序以分析执行状态信息。

57. 发明授权

US07634621B1 Register file allocation 有权
标题翻译：注册文件分配
公开(公告)号：US07634621B1
公开(公告)日：2009-12-15
申请号：US11556677
申请日：2006-11-03
申请人： Brett W. Coon , John Erik Lindholm , Gary Tarolli , Svetoslav D. Tzvetkov , John R. Nickolls , Ming Y. Siu
发明人： Brett W. Coon , John Erik Lindholm , Gary Tarolli , Svetoslav D. Tzvetkov , John R. Nickolls , Ming Y. Siu
IPC分类号： G06F12/00
CPC分类号： G06F9/3012 , G06F9/30123 , G06F9/3824 , G06F9/3851 , G06F9/3885 , G06F12/0223 , Y02D10/13
摘要： Circuits, methods, and apparatus that provide the die area and power savings of a single-ported memory with the performance advantages of a multiported memory. One example provides register allocation methods for storing data in a multiple-bank register file. In a thin register allocation method, data for a process is stored in a single bank. In this way, different processes use different banks to avoid conflicts. In a fat register allocation method, processes store data in each bank. In this way, if one process uses a large number of registers, those registers are spread among the banks, avoiding a situation where one bank is filled and other processes are forced to share a reduced number of banks. In a hybrid register allocation method, processes store data in more than one bank, but fewer than all the banks. Each of these methods may be combined in varying ways.
摘要翻译：提供具有多端口存储器性能优势的单端口存储器的管芯面积和功率节省的电路，方法和装置。一个示例提供用于将数据存储在多存储器寄存器文件中的寄存器分配方法。在一个薄的寄存器分配方法中，一个进程的数据被存储在一个单独的存储单元中。以这种方式，不同的流程使用不同的银行来避免冲突。在胖寄存器分配方法中，处理将数据存储在每个存储区中。这样一来，如果一个进程使用大量的寄存器，这些寄存器就会在银行之间传播，避免了一个银行被填满的情况，而其他进程被迫分担一个数量减少的银行。在混合寄存器分配方法中，处理将数据存储在多个银行中，但少于所有银行。这些方法中的每一种可以以不同的方式组合。

58. 发明申请

US20090240860A1 Lock Mechanism to Enable Atomic Updates to Shared Memory 有权
标题翻译：锁定机制来启用共享内存的原子更新
公开(公告)号：US20090240860A1
公开(公告)日：2009-09-24
申请号：US12054267
申请日：2008-03-24
申请人： Brett W. Coon , John R. Nickolls , Lars Nyland , Peter C. Mills
发明人： Brett W. Coon , John R. Nickolls , Lars Nyland , Peter C. Mills
IPC分类号： G06F12/14
CPC分类号： G06F12/084 , G06F9/3004 , G06F9/30087 , G06F9/30185 , G06F9/526 , G06F2209/521
摘要： A system and method for locking and unlocking access to a shared memory for atomic operations provides immediate feedback indicating whether or not the lock was successful. Read data is returned to the requestor with the lock status. The lock status may be changed concurrently when locking during a read or unlocking during a write. Therefore, it is not necessary to check the lock status as a separate transaction prior to or during a read-modify-write operation. Additionally, a lock or unlock may be explicitly specified for each atomic memory operation. Therefore, lock operations are not performed for operations that do not modify the contents of a memory location.
摘要翻译：用于锁定和解锁对原子操作的共享存储器的访问的系统和方法提供指示锁是否成功的即时反馈。读取数据将返回给具有锁定状态的请求者。在写入期间在读取或解锁期间锁定时，锁定状态可能会同时更改。因此，在读取 - 修改 - 写入操作之前或期间，不必将锁定状态检查为单独的事务。另外，可以为每个原子存储器操作明确地指定锁定或解锁。因此，对于不修改内存位置的内容的操作，不执行锁定操作。

59. 发明授权

US07543136B1 System and method for managing divergent threads using synchronization tokens and program instructions that include set-synchronization bits 有权
标题翻译：用于使用包括设置同步位的同步令牌和程序指令来管理发散线程的系统和方法
公开(公告)号：US07543136B1
公开(公告)日：2009-06-02
申请号：US11180499
申请日：2005-07-13
申请人： Brett W. Coon , John Erik Lindholm
发明人： Brett W. Coon , John Erik Lindholm
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3851 , G06F9/30181 , G06F9/322
摘要： One embodiment of a computing system configured to manage divergent threads in a thread group includes a stack configured to store at least one token and a multithreaded processing unit. The multithreaded processing unit is configured to perform the steps of fetching a program instruction, determining that the program instruction is a branch instruction, determining that the program instruction is not a return or break instruction, determining whether the program instruction includes a set-synchronization bit, and updating an active program counter, where the manner in which the active program counter is updated depends on a branch instruction type.
摘要翻译：被配置为管理线程组中的发散线程的计算系统的一个实施例包括配置成存储至少一个令牌和多线程处理单元的堆栈。多线程处理单元被配置为执行获取程序指令，确定程序指令是分支指令，确定程序指令不是返回或中断指令的步骤，确定程序指令是否包括设置同步位并且更新活动程序计数器，其中活动程序计数器的更新方式取决于分支指令类型。

60. 发明申请

US20080143730A1 HIERARCHICAL PROCESSOR ARRAY 有权
标题翻译：分层处理器阵列
公开(公告)号：US20080143730A1
公开(公告)日：2008-06-19
申请号：US11933993
申请日：2007-11-01
申请人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
发明人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
IPC分类号： G06F15/00
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06F9/5044 , G06T15/005
摘要： Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.
摘要翻译：为分级处理器提供了设备和方法。所述处理器在第一级别包括多个类似结构的第一级组件，其中所述多个类似结构的第一级组件中的每一个包括能够执行多类图形操作的至少一个组合功能模块，每个组件与不同阶段的图形处理相关联的多类图形操作。处理器在第二层次上包括定位在多个类似结构的第一级组件中的每一个内的多个类似结构的第二级组件，其中多个类似结构的第二级组件中的每一个能够执行不同的来自多类图形操作的操作，其中每个第一级组件适于将工作分配到定位在第一级组件内的多个相似结构的第二级组件。

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