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51. 发明授权

US07710209B2 Digital pulse frequency/pulse amplitude (DPFM/DPAM) controller for low-power switching-power supplies 有权
标题翻译：用于低功耗开关电源的数字脉冲频率/脉冲幅度（DPFM / DPAM）控制器
公开(公告)号：US07710209B2
公开(公告)日：2010-05-04
申请号：US12034573
申请日：2008-02-20
申请人： Aleksandar Prodić , Kun Wang , Amir Parayandeh
发明人： Aleksandar Prodić , Kun Wang , Amir Parayandeh
IPC分类号： H03K3/03
CPC分类号： H03K5/1515 , H02M3/156 , H03K9/02 , H03K9/06
摘要： A digital controller for dc-dc switching converters can operate under light load conditions. The controller can be suitable for the use in switch-mode power supplies providing regulated output voltage for handheld devices and other low-power electronics. To create long time intervals, compared to the propagation time of digital logic a DPFM/DPAM can use a ring oscillator with two sets of delay cells and two signals racing around the ring.
摘要翻译：用于dc-dc开关转换器的数字控制器可在轻负载条件下工作。该控制器适用于开关模式电源，为手持设备和其他低功耗电子设备提供稳定的输出电压。为了创建长时间间隔，与数字逻辑的传播时间相比，DPFM / DPAM可以使用具有两组延迟单元的环形振荡器和围绕环路的两个信号。

52. 发明申请

US20100066579A1 GRAY CODE CURRENT MODE ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：灰色代码电流模式模拟到数字转换器
公开(公告)号：US20100066579A1
公开(公告)日：2010-03-18
申请号：US12212039
申请日：2008-09-17
申请人： Richard W. Randlett
发明人： Richard W. Randlett
IPC分类号： H03M1/12
CPC分类号： H03M1/447 , H03M1/0682 , H03M7/16
摘要： One embodiment of the present invention is a Gray code current-mode analog to digital (ADC) converter using a Gray code current-mode ADC building block. The Gray code current-mode ADC building block can produce a Gray code bit and a current output that is sent to a next Gray code ADC building block. In one embodiment, the Gray code current-mode ADC building block does not use a voltage comparator in a signal path of the current output. In one embodiment, an 8 bit analog-to-digital converter can have a 65 ns conversion time and consume only 10 mW of power with a single +5.0V supply.
摘要翻译：本发明的一个实施例是使用格雷码电流模式ADC构建块的格雷码电流模式模数（ADC）转换器。格雷码电流模式ADC构建块可以产生一个格雷码位和一个电流输出，发送到下一个格雷码ADC构建块。在一个实施例中，格雷码电流模式ADC构建块在电流输出的信号路径中不使用电压比较器。在一个实施例中，8位模数转换器可以具有65ns的转换时间，并且在单个+ 5.0V电源下仅消耗10mW的功率。

53. 发明授权

US07652604B2 Programmable analog-to-digital converter for low-power DC-DC SMPS 有权
标题翻译：用于低功率DC-DC SMPS的可编程模数转换器
公开(公告)号：US07652604B2
公开(公告)日：2010-01-26
申请号：US11773330
申请日：2007-07-03
申请人： Amir Parayandeh , Aleksandar Prodic
发明人： Amir Parayandeh , Aleksandar Prodic
IPC分类号： H03M3/00
CPC分类号： H03K7/08 , H02M3/157 , H03M1/502
摘要： A voltage-to-time based windowed analog-to-digital converter (ADC) can have programmable reference voltage, conversion time, and accuracy of voltage regulation. The ADC can be fully implemented on a small silicon area and is suitable for implementation in various integrated digital controllers for high-frequency low-power switch-mode power supplies (SMPS). The programmable characteristics can be achieved through the utilization of the inherent averaging effect of the delay line or of the other voltage-to-time conversion structures and through the adjustments of delay cells' propagation times or the effective voltage-to-time conversion ratio in alternative structures.
摘要翻译：基于电压 - 时间的窗口模数转换器（ADC）可以具有可编程参考电压，转换时间和电压调节精度。 ADC可以在小型硅片上完全实现，适用于高频低功耗开关电源（SMPS）的各种集成数字控制器。可编程特性可以通过利用延迟线或其他电压 - 时间转换结构的固有平均效应，并通过调整延迟单元的传播时间或有效的电压 - 时间转换比来实现替代结构。

54. 发明申请

US20090231029A1 COMBINATION OFFSET VOLTAGE AND BIAS CURRENT AUTO-ZERO CIRCUIT 有权
标题翻译：组合偏置电压和偏置电流自动调零电路
公开(公告)号：US20090231029A1
公开(公告)日：2009-09-17
申请号：US12127912
申请日：2008-05-28
申请人： Richard W. Randlett
发明人： Richard W. Randlett
IPC分类号： H03F1/02 , H03F3/08
CPC分类号： H03F3/087 , H03F3/45475 , H03F2203/45136 , H03F2203/45528 , H03F2203/45534 , H03F2203/45616
摘要： A circuit with an input acquisition loop and an output acquisition loop is used to compensate for the input offset voltage and bias current errors of an operational amplifier.
摘要翻译：具有输入采集环路和输出采集环路的电路用于补偿运算放大器的输入失调电压和偏置电流误差。

55. 发明授权

US07590130B2 Communications system with first and second scan tables 有权
标题翻译：具有第一和第二扫描表的通信系统
公开(公告)号：US07590130B2
公开(公告)日：2009-09-15
申请号：US11020874
申请日：2004-12-22
申请人： Russell Homer , Khai Hoan Duong
发明人： Russell Homer , Khai Hoan Duong
IPC分类号： H04L12/40
CPC分类号： H04J3/08 , H04L12/433 , H04L47/50 , H04L47/525
摘要： A communications system comprising a first stage including a first scan table and a second stage including a second scan table. The first stage is configured to select a first channel identification from the first scan table and provide data from a channel identified by the first channel identification. The second stage is configured to receive the data and select a second channel identification from the second scan table to provide the received data at essentially a data rate of the channel on a synchronous network.
摘要翻译：一种通信系统，包括包括第一扫描表的第一级和包括第二扫描表的第二级。第一级被配置为从第一扫描表中选择第一信道标识，并从由第一信道标识识别的信道提供数据。第二级被配置为从第二扫描表接收数据并选择第二信道标识，以基本上在同步网络上的信道的数据速率提供接收的数据。

56. 发明申请

US20090180227A1 AUTO-DETECTING CMOS INPUT CIRCUIT FOR SINGLE-VOLTAGE-SUPPLY CMOS 有权
标题翻译：自动检测用于单电压CMOS的CMOS输入电路
公开(公告)号：US20090180227A1
公开(公告)日：2009-07-16
申请号：US12014072
申请日：2008-01-14
申请人： Hung Pham Le
发明人： Hung Pham Le
IPC分类号： H02H9/04
CPC分类号： H03K19/018521
摘要： An auto-detecting input circuit is operative to sustain relatively high voltages applied to an input pad and generate corresponding signal levels at a native supply voltage range. The input circuit includes floating wells, corresponding bias selectors, and input biasing transistors to ensure that no gate oxide exposed to external voltages sustains a voltage greater than a predefined value. Bias selectors select an available highest voltage to reverse bias corresponding floating wells and ensure transistors are not electrically overstressed. As input-related terminals experience switching related voltages, the bias selectors select alternate terminals to continue selection of the highest voltage available and provide correct reverse biasing conditions. A resistor and clamp generate translated output voltage levels limited to the native supply voltage range. A latch is triggered by a first input signal excursion above the native supply voltage. The latch output enables pull-down transistors to provide a correct low-level output signal.
摘要翻译：自动检测输入电路用于维持施加到输入焊盘的相对较高的电压，并在原始电源电压范围内产生相应的信号电平。输入电路包括浮置阱，对应的偏置选择器和输入偏置晶体管，以确保不暴露于外部电压的栅极氧化物保持大于预定值的电压。偏置选择器选择一个可用的最高电压来反向偏置相应的浮动阱，并确保晶体管不是电过压。随着输入相关终端经历切换相关电压，偏置选择器选择备用端子以继续选择可用的最高电压并提供正确的反向偏置条件。电阻和钳位电压产生转换后的输出电压电平，限制到本机电源电压范围。锁存器由在本地电源电压之上的第一输入信号偏移触发。锁存器输出使得下拉晶体管能够提供正确的低电平输出信号。

57. 发明授权

US07457335B2 Fast loop laser diode driver 失效
标题翻译：快速环路激光二极管驱动器
公开(公告)号：US07457335B2
公开(公告)日：2008-11-25
申请号：US11356598
申请日：2006-02-17
申请人： Richard Randlett
发明人： Richard Randlett
IPC分类号： H01S3/00
CPC分类号： H01S5/042
摘要： A laser diode driver circuit can comprise fast loop portion and a closed-loop portion. The closed-loop driver portion can provide a part of the current for a laser diode. The closed-loop drive portion output can be independent of a photodetector. The fast-loop driver portion can provide a second part of the current for the laser diode. The fast-loop driver portion can use the output of the photodiode to determine the output of the fast-loop driver portion.
摘要翻译：激光二极管驱动器电路可以包括快速环路部分和闭环部分。闭环驱动器部分可以为激光二极管提供一部分电流。闭环驱动部分输出可以独立于光电检测器。快速回路驱动器部分可以为激光二极管提供电流的第二部分。快速循环驱动器部分可以使用光电二极管的输出来确定快速循环驱动器部分的输出。

58. 发明授权

US07441039B2 Method and apparatus for adapting mac and network processor core to packet format changes and for mapping RPR architecture over spatial reuse architecture 有权
标题翻译：用于使mac和网络处理器核心适应分组格式变化并用于通过空间重用体系结构映射RPR架构的方法和装置
公开(公告)号：US07441039B2
公开(公告)日：2008-10-21
申请号：US10729335
申请日：2003-12-04
申请人： Sanjay Bhardwaj
发明人： Sanjay Bhardwaj
IPC分类号： G06F15/16
CPC分类号： H04L12/437 , H04L12/462 , H04L69/08
摘要： A data communications device that can operate in accordance with two or more protocols having different data formats and error-protection schemes. The protocol-dependent aspects of the device are handled by a peripheral portion of the device, allowing a substantially protocol-independent core portion that is insulated from protocol changes. Translation and/or adaptation mechanisms in the peripheral portion of the device allow the device to handle changes in data format and/or pipeline changes such as error protection without affecting the core portion of the device. A device and method are provided for inter-operating with both the Spatial Reuse Protocol (SRP) and the Resilient Packet Ring (RPR) architectures.
摘要翻译：一种数据通信设备，其可以根据具有不同数据格式和错误保护方案的两个或多个协议进行操作。设备的协议相关方面由设备的外围部分处理，允许与协议绝缘的基本上协议无关的核心部分改变。设备的外围部分中的翻译和/或适应机制允许设备处理数据格式和/或流水线改变的变化，例如错误保护，而不影响设备的核心部分。提供了一种与空间重用协议（SRP）和弹性分组环（RPR）架构相互操作的设备和方法。

59. 发明授权

US07091754B2 CMOS LvPECL driver with output level control 失效
标题翻译： CMOS LvPECL驱动器，具有输出电平控制
公开(公告)号：US07091754B2
公开(公告)日：2006-08-15
申请号：US10879475
申请日：2004-06-28
申请人： Timothy Lu , Vincent S. Tso
发明人： Timothy Lu , Vincent S. Tso
IPC分类号： H03K3/00
CPC分类号： H03K19/018528 , H03K5/2481
摘要： A differential output driver includes an output block, a replication block, and a feedback control block. Each of the output and replication blocks further includes a preamplifier and a source-follower stage. The preamplifier of the output block receives a differential input voltage and generates a first differential voltage. The source-follower stage of the output block receives the first differential voltage and generates a differential output voltage. The preamplifier of the replication block receives first and second supply voltages and generates a second differential voltage. The source-follower stage of the output block receives the second differential voltage and generates a third differential voltage. The feedback control block receives the third differential voltage and generates a differential control voltage applied to the output block. The generated differential output voltage stays within predefined limits, such as those defined by the LvPECL standard.
摘要翻译：差分输出驱动器包括输出块，复制块和反馈控制块。每个输出和复制块还包括前置放大器和源极跟随器级。输出块的前置放大器接收差分输入电压并产生第一差分电压。输出块的源极跟随器级接收第一差分电压并产生差分输出电压。复制块的前置放大器接收第一和第二电源电压并产生第二差分电压。输出块的源极跟随器级接收第二差分电压并产生第三差分电压。反馈控制块接收第三差分电压并产生施加到输出块的差分控制电压。产生的差分输出电压保持在预定义的限制内，例如由LvPECL标准定义的限制。

60. 发明授权

US07078958B2 CMOS bandgap reference with low voltage operation 失效
标题翻译： CMOS带隙参考低电压工作
公开(公告)号：US07078958B2
公开(公告)日：2006-07-18
申请号：US10364278
申请日：2003-02-10
申请人： Richard Leigh Gower , Bhupendra Kumar Ahuja
发明人： Richard Leigh Gower , Bhupendra Kumar Ahuja
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F3/30
摘要： A bandgap reference voltage generator includes, in part, a first closed-loop circuit having a first operational amplifier and adapted to generate a first current with a positive temperature coefficient and a second closed-loop circuit having a second operational amplifier and adapted to generate a second current with a negative temperature coefficient. The bandgap reference voltage generator is further adapted to include a multitude of output stages. Each output stage may be independently scaled to sum any selected multiple of the first current to any selected multiple of the second current to generate an output voltage having either a nearly zero, a positive or a negative temperature coefficient. For example, the first output stage may be scaled to generate a reference output voltage with a nearly zero temperature coefficient. Similarly, the second output stage may be scaled to generate a reference output voltage with a negative temperature coefficient.
摘要翻译：带隙参考电压发生器部分地包括具有第一运算放大器并适于产生具有正温度系数的第一电流的第一闭环电路和具有第二运算放大器的第二闭环电路，并且适于产生具有负温度系数的第二电流。带隙参考电压发生器还适于包括多个输出级。每个输出级可以被独立地缩放以将第一电流的任何选定倍数与第二电流的任何选定倍数相加以产生具有接近零，正或负温度系数的输出电压。例如，可以缩放第一输出级以产生具有接近零温度系数的参考输出电压。类似地，第二输出级可以被缩放以产生具有负温度系数的参考输出电压。

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