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41. 发明授权

US07548176B2 Data coding buffer for electrical computers and digital data processing systems 有权
标题翻译：电子计算机和数字数据处理系统的数据编码缓冲器
公开(公告)号：US07548176B2
公开(公告)日：2009-06-16
申请号：US11777144
申请日：2007-07-12
申请人： Donald Martin Monro
发明人： Donald Martin Monro
IPC分类号： H03M7/02
CPC分类号： H03M7/02
摘要： A method of buffering includes determining, based at least in part on a radix of a data symbol, a number of discrete values resulting from coding the data symbol into a buffer. The number of discrete values is compared with a buffer capacity of the buffer. The buffer is scaled based at least in part on the radix of the data symbol if the number of discrete values does not exceed the buffer capacity of the buffer. The data symbol is coded into the scaled buffer if the number of discrete values does not exceed the buffer capacity of the buffer.
摘要翻译：缓冲的方法包括至少部分地基于数据符号的基数来确定由将数据符号编码到缓冲器中而产生的离散值的数量。将离散值的数量与缓冲器的缓冲器容量进行比较。如果离散值的数量不超过缓冲器的缓冲器容量，则缓冲器至少部分地基于数据符号的基数进行缩放。如果离散值的数量不超过缓冲器的缓冲器容量，则数据符号被编码到缩放缓冲器中。

42. 发明授权

US07030789B1 Techniques for applying modulation constraints to data using periodically changing symbol mappings 有权
标题翻译：使用周期性变化的符号映射对数据应用调制约束的技术
公开(公告)号：US07030789B1
公开(公告)日：2006-04-18
申请号：US11002970
申请日：2004-12-01
申请人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Richard Leo Galbraith , Thomas Mittelholzer , Travis Oenning
发明人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Richard Leo Galbraith , Thomas Mittelholzer , Travis Oenning
IPC分类号： H03M7/02
CPC分类号： H03M7/04 , G06F11/08 , G11B20/1426 , G11B2020/1473 , H03M5/145 , H03M7/06 , H03M13/31
摘要： Techniques are provided for applying modulation constraints to data by using periodically changing symbol mappings to replace certain prohibited error prone data patterns. Initially, user data in a first base is mapped to integers of a second base using a base conversion technique. The integers in the second base correspond to symbols. Subsequently, periodically changing symbol mappings are performed during which prohibited symbols generated during base conversion are mapped to permitted symbols. The periodically changing symbol mappings occur in multiple phases, and the prohibited symbols are different in each phase. The resulting data is processed by a precoder in some embodiments.
摘要翻译：提供了通过使用周期性变化的符号映射来替代某些禁止的易错数据模式来向数据应用调制约束的技术。最初，使用基本转换技术将第一基站中的用户数据映射到第二基站的整数。第二个碱基中的整数对应于符号。随后，执行周期性地改变的符号映射，其中在基本转换期间产生的禁止符号被映射到允许的符号。周期性变化的符号映射发生在多个阶段，禁止符号在每个阶段都不同。在一些实施例中，所生成的数据由预编码器处理。

43. 发明申请

US20050286642A1 Voltage level coding system and method 有权
标题翻译：电压电平编码系统及方法
公开(公告)号：US20050286642A1
公开(公告)日：2005-12-29
申请号：US11066831
申请日：2005-02-24
申请人： Jin-Hyun Kim
发明人： Jin-Hyun Kim
IPC分类号： H03M7/00 , H03M7/02 , H04B14/04 , H04L25/49
CPC分类号： H04L25/4917 , H04B14/04
摘要： We describe a voltage level coding system and method. The voltage level coding system includes a level encoder having an input to receive data segments coded using a first code and an output to supply second data codes indicating one of 2N plus at least one additional voltage level to which each data segment is assigned. A converter converts the second data codes into such voltage levels. A controller output supplies the voltage levels. A method for coding digital data includes determining a first data transition, generating a code that includes at least one additional level that minimizes data skew in the first data transition, and coding the first data transition with the additional level in the code.
摘要翻译：我们描述一个电压电平编码系统和方法。电压电平编码系统包括电平编码器，该电平编码器具有用于接收使用第一码编码的数据段的输入端和输出端，以提供指示其中之一至少一个附加电压电平的第二数据码，分配每个数据段。 A转换器将第二数据代码转换成这样的电压电平。控制器输出提供电压电平。一种用于对数字数据进行编码的方法包括：确定第一数据转换，生成包括至少一个使第一数据转换中的数据偏移最小化的附加电平的代码，以及用代码中的附加电平对第一数据转换进行编码。

44. 发明授权

US06842125B2 Unipolar electrical to CSRZ optical converter 失效
标题翻译：单极电气到CSRZ光转换器
公开(公告)号：US06842125B2
公开(公告)日：2005-01-11
申请号：US10435981
申请日：2003-05-12
申请人： John C. Mauro , Salvatore Morasca , Valerio Pruneri , Srikanth Raghavan
发明人： John C. Mauro , Salvatore Morasca , Valerio Pruneri , Srikanth Raghavan
IPC分类号： H03M7/02 , H04B10/155 , H03M7/12
CPC分类号： H04J14/08 , H03M7/02 , H04B10/505 , H04B10/508
摘要： A conversion method for converting a unipolar voltage data stream into a carrier-suppressed return-to-zero (CSRZ) optical data stream includes modulating a continuous optical wave with an encoded nonreturn-to-zero (NRZ) voltage data stream for providing a CSRZ optical data stream of full-width at half-maximum (FWHM) pulse width less than one-half of the transition time of the encoded nonreturn-to-zero (NRZ) voltage data stream between logical states for a reduced pulse width. The modulating circuit is either a duobinary modulator driven with a swing of ±2Vπ or an optical time domain multiplexed plurality of nonreturn-to-zero (NRZ) modulators with phase shifting and differential encoding.
摘要翻译：将单极性电压数据流转换为载波抑制归零（CSRZ）光数据流的转换方法包括用编码的非归零（NRZ）电压数据流调制连续光波，以提供CSRZ 半宽度（FWHM）脉冲宽度的光学数据流小于在减小的脉冲宽度的逻辑状态之间编码的非返回到零（NRZ）电压数据流的转换时间的一半。调制电路是以±2Vpi的摆幅驱动的双二进制调制器或具有相移和差分编码的光时域多路复用多个非归零（NRZ）调制器。

45. 发明授权

US5974183A Method for video compression using temporal weighting 失效
标题翻译：使用时间加权的视频压缩方法
公开(公告)号：US5974183A
公开(公告)日：1999-10-26
申请号：US658589
申请日：1996-06-05
申请人： James Hedley Wilkinson
发明人： James Hedley Wilkinson
IPC分类号： H04N7/32 , G06T9/00 , H03M7/02 , H03M7/30 , H04N7/26 , H04N7/46 , G06K9/36 , G06K9/46
CPC分类号： H04N19/186 , H04N19/577 , H04N19/587 , H04N19/61 , H04N19/63
摘要： Decoder reconstruction error is estimated so as to provide compensation at the encoder which equalizes the errors over different frames, since the errors created by some frames are lower than those created by other frames. The compensation is provided by means of temporal weighting applied in the form of temporal bands each associated with specific numbered frames within a frame group. The technique can be applied to a logarithmic temporal decimation frame structure in which one frame within a group of 2.sup.n frames is an `I` frame and the remaining frames are `B` frames.
摘要翻译：估计解码器重构误差，以便在编码器处提供均衡不同帧上的错误的补偿，因为由一些帧产生的错误低于由其他帧创建的错误。通过以帧组内的特定编号帧相关联的时间频带的形式施加的时间加权来提供补偿。该技术可以应用于对数时间抽取帧结构，其中一组2n帧内的一帧是“I”帧，其余帧是“B”帧。

46. 发明授权

US5825311A Vector coding method, encoder using the same and decoder therefor 失效
标题翻译：矢量编码方法，使用相同编码器及其解码器
公开(公告)号：US5825311A
公开(公告)日：1998-10-20
申请号：US793133
申请日：1997-04-23
申请人： Akitoshi Kataoka , Jotaro Ikedo
发明人： Akitoshi Kataoka , Jotaro Ikedo
IPC分类号： G10L15/02 , G06T9/00 , G10L19/00 , G10L19/12 , H03M7/02 , H03M7/30 , G10L9/18
CPC分类号： H03M7/02 , G06T9/008 , G10L19/00 , G10L19/005 , H03M7/3082
摘要： Representative vectors z.sub.1i and z.sub.2j are selected from codebooks CB1 and CB1, respetively, and multiplied by weighting coefficient vectors w.sub.1 and w.sub.2 of the same number of dimensions as those of the representative vectors, whereby weighted representative vectors z.sub.1i w.sub.1 and z.sub.2j w.sub.2 are generated. These weighted representative vectors are vector combined into a combined vector y.sub.ij, and a combination of the representative vectors is selected by a control part in such a manner as to minimize the distance between the combined vector y.sub.ij and an input vector X. The weighting coefficient vectors w.sub.1 and w.sub.2 each have a maximum component in a different dimension and are selected so that the sum of diagonal matrixes W.sub.1 and W.sub.2 using components of the weighting coefficient vectors as their diagonal elements becomes a constant multiple of the unit matrix.
摘要翻译： PCT No.PCT / JP95 / 01989 Sec。 371日期1997年4月23日 102（e）日期1997年4月23日PCT提交1995年9月29日PCT公布。公开号WO96 / 11468 PCT 日期1996年4月18日代表矢量z1i和z2j从码本CB1和CB1中分别选择，并乘以与代表矢量相同维数的加权系数向量w1和w2，由此加权代表向量z1iw1和z2jw2是生成。这些加权代表矢量是矢量组合成组合矢量yij，并且控制部分选择代表矢量的组合，以使组合矢量yij和输入矢量X之间的距离最小化。加权系数矢量 w1和w2各自具有不同维度的最大分量，并且被选择为使得使用加权系数向量的分量作为对角元素的对角矩阵W1和W2的和变为单位矩阵的常数倍数。

47. 发明授权

US5019819A Digital-to-analog conversion circuit 失效
标题翻译：数模转换电路
公开(公告)号：US5019819A
公开(公告)日：1991-05-28
申请号：US514859
申请日：1990-04-26
申请人： Shigenobu Kimura
发明人： Shigenobu Kimura
IPC分类号： H03M1/08 , H03M3/02 , H03M7/02
CPC分类号： H03M7/02 , H03M3/368 , H03M3/502
摘要： A digital-to-analog conversion circuit capable of preventing a noise produced in a digital system from mixing in an analog output has an input circuit receiving a pulse-code modulated digital signal, a conversion circuit such as a noise shaping circuit for converting the pulse-code modulated digital signal to a pulse wave signal containing analog amplitude information in a time axis direction, a buffer circuit including an electrically insulated coupling circuit such as an optical coupling circuit for transmitting output of the conversion circuit, and an analog output circuit including an analog low-pass filter for delivering out output of the buffer circuit therethrough. A noise generated in a digital system is intercepted by the buffer circuit and is not transmitted further so that mixing of the noise in the analog output circuit is prevented.
摘要翻译：能够防止在数字系统中产生的噪声在模拟输出中混合的数模转换电路具有接收脉冲编码调制数字信号的输入电路，诸如噪声整形电路的转换电路，用于将脉冲编码调制数字信号到包含时间轴方向上的模拟幅度信息的脉波信号，缓冲电路包括电耦合电路，例如用于传输转换电路的输出的光耦合电路，以及模拟输出电路，包括：模拟低通滤波器，用于输出缓冲电路的输出。在数字系统中产生的噪声被缓冲电路截取，不会进一步传输，从而防止模拟输出电路中的噪声混合。

48. 发明授权

US4611233A Digital non-addition mixing apparatus for video signals 失效
标题翻译：用于视频信号的数字非加混合装置
公开(公告)号：US4611233A
公开(公告)日：1986-09-09
申请号：US497899
申请日：1983-03-25
申请人： Takao Tanno
发明人： Takao Tanno
IPC分类号： H03M7/02 , G06F7/00 , G06F7/02 , H04N5/265 , H04N5/14
CPC分类号： H04N5/265
摘要： A plurality of decoders receive digital video data represented by a binary code. The decoders send over a plurality of output lines, the number of which corresponds to the maximum values expressed by the binary code. The decoders provide an output to one of the plurality of output lines in accordance with the binary code. A wired-OR network connects the plurality of output lines with each other. A priority encoder receives signals on the plurality of output lines which are derived from the wired-OR network and encodes them into a binary code in accordance with the one output corresponding to the largest value.
摘要翻译：多个解码器接收由二进制码表示的数字视频数据。解码器通过多个输出线发送，其数量对应于由二进制码表示的最大值。解码器根据二进制码向多条输出线之一提供输出。有线网络将多个输出线彼此连接。优先编码器从多个输出线上接收信号，这些信号是从有线或非网络导出的，并根据对应于最大值的一个输出将它们编码为二进制码。

49. 发明授权

US4547765A Method and circuit arrangement for transliteration of code words 失效
标题翻译：代码字音译的方法和电路布置
公开(公告)号：US4547765A
公开(公告)日：1985-10-15
申请号：US527988
申请日：1983-08-31
申请人： Frithjof Von Sichart , Klaus Wiedeburg
发明人： Frithjof Von Sichart , Klaus Wiedeburg
IPC分类号： H03M5/04 , G06F7/00 , H03M7/00 , H03M7/02 , H04B14/04 , H03K13/24
CPC分类号： G06F7/00 , H03M7/50
摘要： For transliterating code words of a code having m-place code words into the corresponding code words of a different code likewise having m-place code words, individual bits of the code word to be translitereated are forwarded during serial input into a m-place shift register or during the serial output therefrom. These bits are forwarded non-negated or negated from register stage to register stage over a respective forwarding circuit depending upon the measure or criterion of coincidence or non-coincidence between the code word to be transliterated and the code words of the different code. This occurs in such manner that the traversing bits experience a respective negation in front of and after a register stage whose position within the shift register corresponds to the position of non-coinciding bits within the two code words.
摘要翻译：为了将具有m位代码字的代码的代码字译码为同样具有m位代码字的不同代码的相应代码字，则将要翻译的代码字的各个位在串行输入期间转发到m位移注册或在其串行输出期间。这些位根据要音译的代码字和不同代码的代码字之间的一致性或不一致性的度量或标准，通过相应的转发电路从寄存器级非寄存器级或非寄存器级转发到寄存器级。这以这样的方式发生，使得遍历位在寄存器阶段之前和之后经历相应的否定，其中移位寄存器内的位置对应于两个码字内的非重合位的位置。

50. 发明授权

US4369434A Enciphering/deciphering system 失效
标题翻译：加密/解密系统
公开(公告)号：US4369434A
公开(公告)日：1983-01-18
申请号：US215493
申请日：1980-12-11
申请人： Kurt H. Mueller
发明人： Kurt H. Mueller
IPC分类号： H03M7/02 , G09C1/00 , H04L9/06 , H04L9/12 , H04L9/14 , H03K13/00
CPC分类号： H04L9/12 , H04L9/0662
摘要： The enciphering section of an enciphering/deciphering system includes a random number generator, a primary code memory and a multiplex unit in addition to the actual enciphering unit. The deciphering section includes a deciphering unit, a primary code memory and a demultiplex unit. At the beginning of each transmission, and after disturbances, the enciphering and deciphering sections are first synchronized by means of a synchronization sequence. Then a random address is produced by the random number generator for a primary code, and a randomly determined auxiliary code is also selected. The address and the auxiliary code are then transmitted and the primary and auxiliary codes are loaded into the enciphering and deciphering units. The randomly controlled, statistical selection of the primary code simplifies the code management and thus the operation of the system.
摘要翻译：加密/解密系统的加密部分除了实际加密单元之外还包括随机数发生器，主代码存储器和复用单元。解密部分包括解密单元，主代码存储器和解复用单元。在每次传输开始时，在干扰之后，加密和解密部分首先通过同步序列进行同步。然后随机数生成器产生一个主代码的随机地址，并且还选择随机确定的辅助代码。然后发送地址和辅助代码，并将主代码和辅助代码加载到加密和解密单元中。随机控制的主代码的统计选择简化了代码管理，从而简化了系统的运行。

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