专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US09009208B2 Floating-point adder 有权
标题翻译：浮点加法器
公开(公告)号：US09009208B2
公开(公告)日：2015-04-14
申请号：US13536113
申请日：2012-06-28
申请人： Jorn Nystad
发明人： Jorn Nystad
IPC分类号： G06F7/42 , G06F7/485 , G06F7/499
CPC分类号： G06F7/485 , G06F7/49942
摘要： Floating point adder circuitry 16, 18, 20 is provided with far-path circuitry 18 and near-path circuitry 20. The far-path circuitry utilises a count of trailing zeros TZ and a difference in the input operand exponents to form respective suffix values which are concatenated with the mantissas of the input addends and serve when summed to generate a carry out taking the place of a conventionally calculated sticky bit. Within the near-path, minimum value circuitry 46 is used to calculate the lower of a leading zeros count of the intermediate mantissa produced in a subtraction and the larger of the input operand exponent values such that a left shift applied to the intermediate mantissa value is not able to produce a invalid floating point result due to applying a left shift to remove leading zeros that is too larger and accordingly corresponds to an exponent which cannot be validly represented.
摘要翻译：浮点加法器电路16,18,20设置有远程路径电路18和近路径电路20.远路电路利用尾随零TZ的计数和输入操作数指数的差异来形成各自的后缀值，被连接到输入加法器的尾数，并且当被相加以产生执行代替常规计算的粘性位时被服务。在近距离路径内，最小值电路46用于计算在减法中产生的中间尾数的前导零数值中的较低者，以及较大的输入操作数指数值，使得施加到中间尾数值的左移位为由于应用左移以去除过大的前导零，因此不能产生无效的浮点结果，因此对应于无法有效表示的指数。

42. 发明授权

US08965945B2 Apparatus and method for performing floating point addition 有权
标题翻译：用于执行浮点加法的装置和方法
公开(公告)号：US08965945B2
公开(公告)日：2015-02-24
申请号：US12929827
申请日：2011-02-17
申请人： David Raymond Lutz
发明人： David Raymond Lutz
IPC分类号： G06F7/38 , G06F7/42 , G06F7/485 , G06F7/57 , G06F7/76
CPC分类号： G06F7/485 , G06F5/012 , G06F7/5443 , G06F7/57 , G06F7/74 , G06F7/76
摘要： An apparatus and method are provided for performing an addition operation on operands A and B in order to produce a result R, the operands A and B and the result R being floating point values each having a significand and an exponent. The apparatus comprises prediction circuitry for generating a shift indication based on a prediction of the number of leading zeros that would be present in an output produced by subjecting the operands A and B to an unlike signed addition. Further, result pre-normalization circuitry performs a shift operation on the significands of both operand A and operand B prior to addition of the significands, this serving to discard a number of most significant bits of the significands of both operands as determined by the shift indication in order to produce modified significands for operands A and B. Operand analysis circuitry detects, with reference to the exponents of operands A and B, the presence of a leading bit cancellation condition, and addition circuitry is configured, in the presence of the leading bit cancellation condition, to perform an addition of the modified significands for operands A and B, in order to produce the significand of the result R. Such an approach provides a particularly simple and efficient apparatus for performing addition operations.
摘要翻译：提供了一种用于对操作数A和B执行加法运算的装置和方法，以便产生结果R，操作数A和B，结果R是各自具有有效位数和指数的浮点值。该装置包括预测电路，该预测电路用于基于通过对操作数A和B进行不同的签名加法而产生的输出中存在的前导零的数量的预测来生成移位指示。此外，结果预归一化电路在添加有效数之前对操作数A和操作数B的有效值执行移位操作，这用于丢弃由移位指示确定的两个操作数的有效位的数量的最高有效位以便对操作数A和B产生修改的有效值。操作数分析电路参照操作数A和B的指数来检测是否存在引导位取消条件，并且在引导位存在的情况下配置加法电路取消条件，以对操作数A和B执行修改的有效数的加法，以便产生结果R的有效位数。这种方法提供了用于执行加法运算的特别简单和有效的装置。

43. 发明授权

US08615542B2 Multi-function floating point arithmetic pipeline 失效
公开(公告)号：US08615542B2
公开(公告)日：2013-12-24
申请号：US12127898
申请日：2008-05-28
申请人： Steven Shaw
发明人： Steven Shaw
IPC分类号： G06F7/42
CPC分类号： G06F7/5443 , G06F7/483
摘要： A scalable engine having multiple datapaths, each of which is a unique multi-function floating point pipeline capable of performing a four component dot product on data in a single pass through the datapath, which allows matrix transformations to be computed in an efficient manner, with a high data throughput and without substantially increasing the cost and amount of hardware required to implement the pipeline.

44. 发明授权

US08601047B2 Decimal floating-point adder with leading zero anticipation 有权
标题翻译：具有前导零预期的十进制浮点加法器
公开(公告)号：US08601047B2
公开(公告)日：2013-12-03
申请号：US13916850
申请日：2013-06-13
申请人： Advanced Micro Devices, Inc.
发明人： Liang-Kai Wang
IPC分类号： G06F7/42 , G06F7/00
CPC分类号： G06F17/10 , G06F7/485 , G06F7/74 , G06F2207/4911
摘要： A decimal floating-point (DFP) adder includes a decimal leading-zero anticipator (LZA). The DFP adder receives DFP operands. Each operand includes a significand, an exponent, a sign bit and a leading zero count for the significand. The DFP adder adds or subtracts the DFP operands to obtain a DFP result. The LZA determines the leading zero count associated with the significand of the DFP result. The LZA operates at least partially in parallel with circuitry (in the DFP adder) that computes the DFP result. The LZA does not wait for that circuitry to finish computation of the DFP result. Instead it “anticipates” the number of leading zeros that the result's significand will contain.
摘要翻译：十进制浮点（DFP）加法器包括一个十进制前置零预期值（LZA）。 DFP加法器接收DFP操作数。每个操作数包括有效数，有效数，指数，符号位和有效位数的前导零计数。 DFP加法器添加或减少DFP操作数以获取DFP结果。 LZA确定与DFP结果的有效位数相关联的前导零计数。 LZA至少部分与计算DFP结果的电路（在DFP加法器中）并行运行。 LZA不等待该电路完成DFP结果的计算。相反，它“预计”结果的有效位数将包含的前导零的数量。

45. 发明授权

US08423600B2 Accumulating operator and accumulating method for floating point operation 有权
标题翻译：积分运算符和浮点运算的累积方法
公开(公告)号：US08423600B2
公开(公告)日：2013-04-16
申请号：US11032486
申请日：2005-01-10
申请人： Ko-Fang Wang
发明人： Ko-Fang Wang
IPC分类号： G06F7/42 , G06F7/38
CPC分类号： G06F7/5443 , G06F7/483
摘要： An accumulating operator is applicable to a digital data processor to realize an output floating point number in response to a first floating point number and a second floating point number. The accumulating operator comprises a splitter dividing the first floating point number into a third floating point number and a compensation number, wherein an exponent of the third floating point number is equal to or greater than the exponent of the second floating point number; an accumulator electrically connected to the splitter for operating the second and third floating point numbers to realize a fourth floating point number; and a compensator electrically connected to the splitter and the accumulator for operating the fourth floating point number and the compensation number to realize the output floating point number. Via compensation, the precision of the floating point operation can be improved.
摘要翻译：累积运算符适用于数字数据处理器，以响应于第一浮点数和第二浮点数实现输出浮点数。累积运算符包括将第一浮点数分成第三浮点数和补偿数的分割器，其中第三浮点数的指数等于或大于第二浮点数的指数; 蓄电池，电连接到所述分路器，用于操作所述第二和第三浮点数以实现第四浮点数; 以及补偿器，电连接到分路器和累加器，用于操作第四浮点数和补偿数，以实现输出浮点数。通过补偿，可以提高浮点运算的精度。

46. 发明授权

US08373490B2 Method, system, and apparatus for RF and DC switching 有权
标题翻译：射频和直流切换的方法，系统和设备
公开(公告)号：US08373490B2
公开(公告)日：2013-02-12
申请号：US12913575
申请日：2010-10-27
申请人： Mark L. Burgener , Fleming Lam
发明人： Mark L. Burgener , Fleming Lam
IPC分类号： G06F7/42 , G06G7/14
CPC分类号： H03C1/36
摘要： Embodiments of RF and DC switching are described generally herein. Other embodiments may be described and claimed.
摘要翻译： RF和DC切换的实施例一般在此描述。可以描述和要求保护其他实施例。

47. 发明申请

US20120239719A1 Floating-Point Addition Acceleration 审中-公开
标题翻译：浮点加法
公开(公告)号：US20120239719A1
公开(公告)日：2012-09-20
申请号：US13487307
申请日：2012-06-04
申请人： Lawrence A. Rigge
发明人： Lawrence A. Rigge
IPC分类号： G06F7/42
CPC分类号： G06F7/485 , G06F7/49936
摘要： Embodiments of the present invention generate a normalized floating-point sum from at least two floating-point addends. The mantissa of an un-normalized floating-point sum is generated. A pointer is generated which indicates the location of the left-most significant digit (LSD) in the mantissa of the un-normalized floating-point sum. A plurality of possible values for the exponent of the normalized floating-point sum are generated, in parallel with each other and in parallel with the mantissa addition, based on a common exponent value (e.g., the largest of the two addends' exponent values). Based on the LSD pointer, one of the possible values is selected as the exponent of the normalized floating-point sum. The mantissa of the un-normalized floating-point sum is normalized to yield the mantissa of the normalized floating-point sum. By generating the possible exponent values in parallel, embodiments of the present invention can result in significant time savings over prior-art methods.
摘要翻译：本发明的实施例从至少两个浮点加数生成归一化浮点和。生成非归一化浮点和的尾数。产生指示非标准化浮点和的尾数中最高有效位（LSD）的位置的指针。基于公共指数值（例如，两个加数指数值中的最大值），生成与归一化浮点和指数相关并且与尾数相加并行的多个可能值，。基于LSD指针，选择其中一个可能的值作为归一化浮点和的指数。非归一化浮点和的尾数被归一化以产生标准化浮点和的尾数。通过平行地产生可能的指数值，与现有技术方法相比，本发明的实施例可以导致显着的时间节省。

48. 发明申请

US20120134685A1 LOOP FILTER 有权
标题翻译：循环过滤器
公开(公告)号：US20120134685A1
公开(公告)日：2012-05-31
申请号：US13233588
申请日：2011-09-15
申请人： Yasuo OHTOMO , Nobukazu KOIZUMI
发明人： Yasuo OHTOMO , Nobukazu KOIZUMI
IPC分类号： H04B10/06 , G06F7/42 , G06F7/44
CPC分类号： H04B10/6164 , H04B10/611 , H04B10/613 , H04B10/614 , H04B10/616
摘要： A loop filter include: a register that stores a result of arithmetic operation performed on a complex signal and outputs the stored complex signal; a first multiplier that multiplies the complex signal output from the register and a predetermined coefficient; an absolute value judging unit that outputs a multiplier coefficient used to control such that the amplitude of the complex signal output from the register is held in a predetermined range; a multiplier that multiplies an output from the first multiplier and the multiplier coefficient; a second multiplier that multiplies an input signal and a value (1−the predetermined coefficient); and an adder that adds an output from the multiplier to an output from the second multiplier and inputs a result of addition into the register.
摘要翻译：环路滤波器包括：寄存器，其存储对复数信号执行的算术运算结果，并输出所存储的复信号; 第一乘法器，将来自寄存器的复信号输出与预定系数相乘; 绝对值判断单元，输出用于控制的寄生器系数，使得从寄存器输出的复数信号的幅度保持在预定范围内; 乘法器，用于将来自第一乘法器的输出和乘数系数相乘; 将输入信号与值（1-预定系数）相乘的第二乘法器; 以及将乘法器的输出与来自第二乘法器的输出相加并将相加结果输入到寄存器的加法器。

49. 发明申请

US20120036172A1 Expanded Scope Incrementor 失效
标题翻译：扩展范围增量器
公开(公告)号：US20120036172A1
公开(公告)日：2012-02-09
申请号：US12852660
申请日：2010-08-09
申请人： Deepak K. Singh
发明人： Deepak K. Singh
IPC分类号： G06F7/42
CPC分类号： G06F7/5055
摘要： An incrementor circuit and method for incrementing is provided that computes an output data word by increasing an input data word magnitude by one of several integer values. The incrementor circuit includes a mode increment signal circuit providing a designation of one of the integer values for increasing the input data word magnitude. A single constant incrementor is connected to the mode increment signal circuit and the input data word and provides an intermediate sum by selectively adding a constant to the input data word. A multiplex circuit logically combines selected input data word bit position values with the mode increment signal circuit designation forming logical bit position values and directs selected input data word bit position values, selected logical bit position values, and selected bit position values of the intermediate sum to form the output data word.
摘要翻译：提供了一种用于递增的递增器电路和方法，其通过将输入数据字幅度增加到几个整数值之一来计算输出数据字。增量器电路包括模式增量信号电路，其提供用于增加输入数据字幅度的整数值之一的指定。单个常数增量器连接到模式增量信号电路和输入数据字，并通过选择性地向输入数据字添加常数来提供中间和。多路复用电路将所选择的输入数据字位位置值与形成逻辑位位置值的模式增量信号电路指定逻辑组合，并将所选择的输入数据字位位置值，所选择的逻辑位位置值和中间和的选定位位置值引导到形成输出数据字。

50. 发明申请

US20110010408A1 CORDIC COMPUTATION CIRCUIT AND METHOD 有权
标题翻译： CORDIC计算电路和方法
公开(公告)号：US20110010408A1
公开(公告)日：2011-01-13
申请号：US12919632
申请日：2009-03-05
申请人： Katsutoshi Seki
发明人： Katsutoshi Seki
IPC分类号： G06F7/44 , G06F7/42 , G06F11/00
CPC分类号： G06F7/5446 , G06T3/604
摘要： Disclosed is a CORDIC circuit in which scale correction process is divided into two stages: rough correction and fine correction, and a second-process of a pseudo-rotation process is performed in parallel with the fine scale correction. A range of the fine scale correction is set so that it is not necessary to perform a scale correction with regard to a remaining rotation angle of the first half of the pseudo-rotation process.
摘要翻译：公开了一种CORDIC电路，其中缩放校正处理被分为两个阶段：粗略校正和精细校正，并且与精细刻度校正并行执行伪旋转处理的第二处理。精确刻度校正的范围被设定为不需要对伪旋转处理的前半部分的剩余旋转角进行刻度校正。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式