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41. 发明授权

US06975525B2 Method of controlling the operation of a power converter having first and second series connected transistors 失效
标题翻译：控制具有第一和第二串联晶体管的功率转换器的操作的方法
公开(公告)号：US06975525B2
公开(公告)日：2005-12-13
申请号：US10295605
申请日：2002-11-14
申请人： Kent Kernahan
发明人： Kent Kernahan
IPC分类号： G05F3/26 , H02J7/00 , H02M1/084 , H02M3/156 , H02M3/157 , H02M3/158 , H03M5/08 , H02M7/24 , H02M7/5387
CPC分类号： H02M3/157 , G05F3/262 , H02J7/0065 , H02M1/0845 , H02M3/156 , H02M3/1588 , H02M2001/0012 , H02M2001/007 , H02M2001/008 , H03M5/08 , H05B41/2828 , Y02B20/186 , Y02B70/1466 , Y10T307/438 , Y10T307/469
摘要： A series connected pair of switching transistors in a switching power converter is controlled by a method to improve the efficiency of the switching power converter. The transition times of the first and second transistors are stored and the timing of the application of conduction control signals is determined based on the transition times of the first and second transistor. The conduction control signals provided to the first and second transistors may include pulse width modulated signals.
摘要翻译：通过提高开关功率转换器的效率的方法来控制开关功率转换器中的串联的开关晶体管。存储第一和第二晶体管的转换时间，并且基于第一和第二晶体管的转换时间来确定施加导通控制信号的定时。提供给第一和第二晶体管的导通控制信号可以包括脉宽调制信号。

42. 发明申请

US20050231403A1 Sampled system agility technique 有权
标题翻译：抽样系统敏捷技术
公开(公告)号：US20050231403A1
公开(公告)日：2005-10-20
申请号：US11108243
申请日：2005-04-18
申请人： Larry Kirn
发明人： Larry Kirn
IPC分类号： G11C27/02 , H03M1/08 , H03M1/10 , H03M1/82 , H03M5/08
CPC分类号： G11C27/02 , H03M1/0836 , H03M1/822 , H03M5/08
摘要： A method of modulating the sampling period of a sampled system with a factor N, and correcting the data stream of the sampling system with the same factor N, thus minimizing distortion artifacts induced by sample frequency modulation. At least a one-period delay from receipt of a new data stream value is used to avoid heterodyning with the incoming stream.
摘要翻译：一种以因子N调制采样系统的采样周期的方法，并以相同因子N校正采样系统的数据流，从而最小化由采样频率调制引起的失真伪像。使用从接收到新的数据流值的至少一个周期的延迟来避免与输入流的外差。

43. 发明授权

US06917188B2 Power converter circuitry and method 有权
标题翻译：电源转换器电路和方法
公开(公告)号：US06917188B2
公开(公告)日：2005-07-12
申请号：US10295980
申请日：2002-11-14
申请人： Kent Kernahan
发明人： Kent Kernahan
IPC分类号： G05F3/26 , H02J7/00 , H02M1/084 , H02M3/156 , H02M3/157 , H02M3/158 , H03M5/08 , G05F1/40 , H02H3/20
CPC分类号： H02M3/157 , G05F3/262 , H02J7/0065 , H02M1/0845 , H02M3/156 , H02M3/1588 , H02M2001/0012 , H02M2001/007 , H02M2001/008 , H03M5/08 , H05B41/2828 , Y02B20/186 , Y02B70/1466 , Y10T307/438 , Y10T307/469
摘要： A switching power supply controller coupled to a first switching power supply circuit and a second switching power supply circuit, the controller sensing voltages provided to the first switching power supply circuit and the second switching power supply circuit. Based on voltages sensed, the switching power supply controller provides signals to operate the second switching power supply in either a first or a second mode of operation. In one of the modes of operation, the second switching power supply includes a transistor which is coupled between a first source of electrical potential and an input terminal of the first switching power supply. If switching power supply controller determines that the magnitude of the first source of electric potential is sufficient to operate the first switching power supply, the switching power supply controller provides a control signal to turn on the transistor continuously.
摘要翻译：一种开关电源控制器，其耦合到第一开关电源电路和第二开关电源电路，所述控制器感测提供给所述第一开关电源电路和所述第二开关电源电路的电压。基于感测的电压，开关电源控制器提供信号以在第一或第二操作模式中操作第二开关电源。在操作模式之一中，第二开关电源包括耦合在第一电源和第一开关电源的输入端之间的晶体管。如果开关电源控制器确定第一电源电压的大小足以操作第一开关电源，则开关电源控制器提供控制信号以连续导通晶体管。

44. 发明授权

US06906500B2 Method of operating a switching power converter 有权
标题翻译：操作开关电源转换器的方法
公开(公告)号：US06906500B2
公开(公告)日：2005-06-14
申请号：US10295448
申请日：2002-11-14
申请人： Kent Kernahan
发明人： Kent Kernahan
IPC分类号： G05F3/26 , H02J7/00 , H02M1/084 , H02M3/156 , H02M3/157 , H02M3/158 , H03M5/08 , G05F1/613
CPC分类号： H02M3/157 , G05F3/262 , H02J7/0065 , H02M1/0845 , H02M3/156 , H02M3/1588 , H02M2001/0012 , H02M2001/007 , H02M2001/008 , H03M5/08 , H05B41/2828 , Y02B20/186 , Y02B70/1466 , Y10T307/438 , Y10T307/469
摘要： A method of operating a switching power converter circuit having first and second transistors connected to an inductor, where a conduction control signal is selectively applied to the second transistor as a function of an operation of the first transistor during a conduction cycle. The decision on whether to provide a conduction control signal to the second transistor is made in one mode of operation as a function of the length of the first conduction control signal applied to the first transistor during the conduction cycle. In another mode of operation a comparison is made of the on-to-off conduction transition time of the second transistor to the length of time remaining in a conduction cycle after the first transistor ceases to conduct.
摘要翻译：一种操作具有连接到电感器的第一和第二晶体管的开关功率转换器电路的方法，其中在导通周期期间将导通控制信号选择性地施加到第二晶体管作为第一晶体管的操作的函数。作为在导通周期期间施加到第一晶体管的第一导通控制信号的长度的函数，在一个操作模式中进行关于是否向第二晶体管提供导通控制信号的决定。在另一种操作模式中，比较了在第一晶体管停止导通之后，第二晶体管的导通到导通转变时间到导通周期中剩余的时间长度。

45. 发明申请

US20050078019A1 Dual phase pulse modulation system 有权
标题翻译：双相脉冲调制系统
公开(公告)号：US20050078019A1
公开(公告)日：2005-04-14
申请号：US10961980
申请日：2004-10-08
申请人： Daniel Cohen , John Fagan
发明人： Daniel Cohen , John Fagan
IPC分类号： H03M5/08 , H03M5/06 , H03M9/00
CPC分类号： H04L25/4902 , H03M5/08 , H04L25/4904 , H04N1/00127 , H04N2201/0015 , H04N2201/0065
摘要： A system configured to transmit and receive data signals over a data link in serial fashion using dual phase pulse modulation (DPPM) is described. The data link may be, for example, a one or two wire unshielded twisted pair (UTP) cable. An exemplary system includes a configurable interface able to accept parallel data from an external source, such as a microprocessor or an imaging device. The interface is externally programmable for a particular data format. An encoder is coupled to the configurable interface and converts parallel data into serial output data, the serial output data having high and low data pulses with each of the high and low data pulses encoded to have one of 2M distinct data pulse widths. The system further includes a decoder coupled to the configurable interface, which is able to convert the serial input data into parallel data.
摘要翻译：描述了被配置为通过数据链路以串行方式使用双相位脉冲调制（DPPM）来发送和接收数据信号的系统。数据链路可以是例如一根或两根非屏蔽双绞线（UTP）电缆。示例性系统包括能够接收来自诸如微处理器或成像设备的外部源的并行数据的可配置接口。该界面可外部编程为特定的数据格式。编码器耦合到可配置接口并将并行数据转换成串行输出数据，串行输出数据具有高和低数据脉冲，其中每个高和低数据脉冲被编码为具有2个不同数据脉冲宽度之一。该系统还包括耦合到可配置接口的解码器，其能够将串行输入数据转换为并行数据。

46. 发明授权

US6064646A Data communication apparatus and method 失效
标题翻译：数据通信装置及方法
公开(公告)号：US6064646A
公开(公告)日：2000-05-16
申请号：US938679
申请日：1997-09-26
申请人： David Andrew Shal , Richard Clarkson Griffin , Dennis Palmer Griffin , Wayne Dale Moore
发明人： David Andrew Shal , Richard Clarkson Griffin , Dennis Palmer Griffin , Wayne Dale Moore
IPC分类号： H03K7/08 , H03K9/08 , H03M5/08
CPC分类号： H03M5/08
摘要： In a first controller that runs a first control algorithm and a first interrupt service, wherein the first control algorithm includes a first series of commands repeatedly executed in sequence, wherein the first interrupt service performs a second series of commands when the first interrupt service is triggered, wherein the first controller includes a first free running counter with a counter timer value that repeatedly increments and resets when the counter timer overflows, a data communication method comprising the steps of: in each sequential execution of the first series of commands: reading a data signal to be transmitted; responsive to the data signal, computing an on-time; setting a first edge of a serial transmission signal; and loading a register with a value equal to a sum of the first counter value and the on time; independent of the first series of commands: comparing the first counter value to the register value; when the first counter value equals the register value, triggering the first interrupt service; and when the first interrupt service is triggered, resetting a second edge of the serial transmission signal, wherein the first edge is not set again until a new data signal to be transmitted is read.
摘要翻译：在运行第一控制算法和第一中断服务的第一控制器中，其中第一控制算法包括顺序重复执行的第一序列命令，其中当第一中断服务被触发时，第一中断服务执行第二系列命令，其中所述第一控制器包括具有计数器定时器值的第一自由运行计数器，所述计数器定时器值在所述计数器定时器溢出时重复增加并复位;数据通信方法，包括以下步骤：在所述第一系列命令的每个顺序执行中：读取数据要发送的信号; 响应于数据信号，计算准时; 设置串行传输信号的第一个边沿; 并加载具有等于第一计数器值和导通时间之和的值的寄存器; 独立于第一系列命令：将第一计数器值与寄存器值进行比较; 当第一个计数器值等于寄存器值时，触发第一个中断服务; 并且当第一中断服务被触发时，复位串行传输信号的第二边缘，其中第一边缘不被再次设置，直到读取要发送的新数据信号为止。

47. 发明授权

US5969646A Apparatus and method for decoding differential multi-level data with adaptive threshold control 失效
标题翻译：用自适应阈值控制解码差分多级数据的装置和方法
公开(公告)号：US5969646A
公开(公告)日：1999-10-19
申请号：US47439
申请日：1998-03-25
申请人： Yi Cheng , Zhenhua Liu , Kris Martin Holt
发明人： Yi Cheng , Zhenhua Liu , Kris Martin Holt
IPC分类号： H03K5/08 , H04L25/06 , H04L25/08 , H04L25/34 , H03M5/08
CPC分类号： H04L25/08 , H03K5/082 , H04L25/061
摘要： An improved decoder for recovering Non-Return-to-Zero Interface (NRZI) digital data from a multiple layer transition (MLT-3) encoded signal in a 100BASE-TX Ethernet (IEEE Standard 802.3u) uses multiple comparators to minimize jitter in the decoded signal. A CMOS-based biasing circuit receives the differential MLT-3 encoded input signals and control signals from a signal amplitude detection circuit. The biasing circuit adjusts for any DC offset, and also generates offset signals based on respective mid-peak voltage values of the respective differential input signals. Four comparators are then used to detect a prescribed edge transition (e.g., a positive edge) coinciding with the respective mid-peak voltage value in the respective signals. The detected edge transitions are then used by edge decoding logic to generate the NRZI bilevel signal.
摘要翻译：用于从100BASE-TX以太网（IEEE标准802.3u）中的多层转换（MLT-3）编码信号中恢复非归零接口（NRZI）数字数据的改进解码器使用多个比较器来最小化解码信号。基于CMOS的偏置电路从信号幅度检测电路接收差分MLT-3编码的输入信号和控制信号。偏置电路调整任何DC偏移，并且还基于各个差分输入信号的各个中间峰值电压值产生偏移信号。然后使用四个比较器来检测与各个信号中的各个中间峰值电压值一致的规定边缘转变（例如，正边沿）。所检测的边缘转换然后由边缘解码逻辑使用以产生NRZI双电平信号。

48. 发明授权

US5959501A Class D amplifier with scaled clock and related methods 失效
标题翻译： D类放大器具有缩放时钟和相关方法
公开(公告)号：US5959501A
公开(公告)日：1999-09-28
申请号：US7326
申请日：1998-01-14
申请人： David B. Chester
发明人： David B. Chester
IPC分类号： H03F3/217 , H03F21/00 , H03K7/08 , H03M5/08
CPC分类号： H03F3/217
摘要： A class D amplifier includes a scaled clock generator for generating a scaled clock signal based upon an N bit pulse code modulation (PCM) signal and a K most significant bits (MSBs) PCM signal from the N bit PCM signal; and a PCM to pulse width modulation (PWM) converter for converting the K MSBs signal to a PWM output signal based upon the scaled clock signal. The amplifier preferably includes an input circuit for generating the N bit PCM signal from an input signal, and a truncation circuit for truncating the N bit PCM digital signal to the K MSBs PCM signal. The PWM output signal may be coupled to a switch driver which, in turn, is coupled to one or more output switches. The amplifier uses a practically implemented reference clock without the drawbacks associated with a conventional noise shaping filter. The scaled clock generator may be provided by a divider having a first input receiving the N bit digital input signal and a second input receiving the K MSBs signal for generating a clock scale ratio signal. The scaled clock generator may also include a reference clock, and a numerically controlled clock connected thereto for producing the scaled clock signal. The scaled clock generator may further include a bias circuit for inputting a bias value to the divider so that a numerator thereof is greater than zero.
摘要翻译： D类放大器包括缩放的时钟发生器，用于基于来自N位PCM信号的N位脉冲编码调制（PCM）信号和K个最高有效位（MSB））PCM信号来产生缩放的时钟信号; 以及PCM至脉宽调制（PWM）转换器，用于基于缩放的时钟信号将K个MSB信号转换为PWM输出信号。放大器优选地包括用于从输入信号产生N位PCM信号的输入电路和用于将N位PCM数字信号截断为K个MSB PCM信号的截断电路。 PWM输出信号可以耦合到开关驱动器，开关驱动器又耦合到一个或多个输出开关。放大器使用实际实现的参考时钟，而没有与常规噪声整形滤波器相关联的缺点。缩放的时钟发生器可以由具有接收N位数字输入信号的第一输入的分频器和接收用于产生时钟比例信号的K个MSB信号的第二输入端提供。缩放的时钟发生器还可以包括参考时钟和与其连接的数控时钟，用于产生缩放的时钟信号。缩放的时钟发生器还可以包括偏置电路，用于将偏置值输入到分频器，使得其分子大于零。

49. 发明授权

US5940018A nB2P coding/decoding device 失效
标题翻译： nB2P编码/解码装置
公开(公告)号：US5940018A
公开(公告)日：1999-08-17
申请号：US941214
申请日：1997-09-30
申请人： Jin-Young Kim , Bhum-Cheol Lee , Kwon-Chul Park
发明人： Jin-Young Kim , Bhum-Cheol Lee , Kwon-Chul Park
IPC分类号： H03M7/14 , H03M5/08 , H03M13/11 , H03M13/31 , H04B3/04 , H04L7/00 , H03M13/00
CPC分类号： H03M13/63 , H03M13/11 , H03M13/31 , H03M5/08
摘要： An nB2P coding/decoding device having a line code function facilitating data transmission and data recovery in the transmission line or link, and a function of a channel code for detecting errors in the recovered data, is provided, including: an nB2P coding device for dividing n bit width parallel data into two data units each having a predetermined bit width, and serial-transmitting the resulting n+2 bit coded data to which two odd parity bits are added, with predetermined n+2 bit with block synchronization data which is orthogonal to the coded data; and an nB2P decoding device for detecting the block synchronization data from the serially transmitted data, converts serial data to parallel form of n+2 bits, checking for errors in the coded data using the odd parity, and removing the odd parity to decode them into the original n bit width parallel data.
摘要翻译：一种具有促进传输线或链路中的数据传输和数据恢复的线路代码功能的nB2P编码/解码装置，以及用于检测恢复数据中的错误的信道码的功能，包括：nB2P编码装置，用于分割将n位宽的并行数据分割成具有预定位宽的两个数据单元，并且将具有两个奇校验位的所生成的n + 2位编码数据与预定的n + 2位串联发送，其中正交的块同步数据到编码数据; 以及用于从串行发送数据检测块同步数据的nB2P解码装置，将串行数据转换成n + 2位的并行形式，使用奇校验检查编码数据中的错误，并且去除奇校验以将其解码为原始n位宽的并行数据。

50. 发明授权

US5859669A System for encoding an image control signal onto a pixel clock signal 失效
标题翻译：用于将图像控制信号编码到像素时钟信号上的系统
公开(公告)号：US5859669A
公开(公告)日：1999-01-12
申请号：US756631
申请日：1996-11-26
申请人： Richard Mark Prentice
发明人： Richard Mark Prentice
IPC分类号： G09G5/00 , G09G5/18 , H04N5/06 , H03M5/08 , H04N7/04
CPC分类号： G09G5/006 , G09G5/18
摘要： A system for encoding control data onto a clock signal includes at least one clock cycle in the clock signal; a first transition in the at least one clock cycle, the first transition is from a first voltage level to a second voltage level, the first transition is in a first location in the at least one clock cycle; a second transition in the at least one clock cycle, the second transition is from the second voltage level to the first voltage level, the second transition has a variable location in the clock cycle; and an encoder circuit for positioning the second transition in the variable location in response to the control data.
摘要翻译：用于将控制数据编码到时钟信号上的系统包括时钟信号中的至少一个时钟周期; 在所述至少一个时钟周期中的第一转变，所述第一转变是从第一电压电平到第二电压电平，所述第一转变在所述至少一个时钟周期中处于第一位置; 在所述至少一个时钟周期中的第二转变，所述第二转变是从所述第二电压电平到所述第一电压电平，所述第二转换在所述时钟周期中具有可变位置; 以及用于响应于所述控制数据将所述第二转换定位在所述可变位置中的编码器电路。

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