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41. 发明授权

US11637126B2 Memory device and method of forming the same 有权
公开(公告)号：US11637126B2
公开(公告)日：2023-04-25
申请号：US17156645
申请日：2021-01-25
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chao-I Wu , Yu-Ming Lin , Sai-Hooi Yeong
IPC分类号： H01L27/11597 , H01L27/1159 , H01L27/11587 , H01L27/11585 , H01L29/51 , H01L27/11553 , H01L21/28
摘要： Provided are a memory device and a method of forming the same. The memory device includes a substrate, a layer stack, and a plurality of composite pillar structures. The layer stack is disposed on the substrate. The layer stack includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The composite pillar structures respectively penetrate through the layer stack. Each composite pillar structure includes a dielectric pillar; a pair of conductive pillars penetrating through the dielectric pillar and electrically isolated from each other through a portion of the dielectric pillar; a channel layer covering both sides of the dielectric pillar and the pair of conductive pillars; a ferroelectric layer disposed between the channel layer and the layer stack; and a buffer layer disposed between the channel layer and the ferroelectric layer.

42. 发明授权

US11508741B2 Nonvolatile memory device having resistance change structure 有权
公开(公告)号：US11508741B2
公开(公告)日：2022-11-22
申请号：US16900448
申请日：2020-06-12
申请人： SK hynix Inc.
发明人： Jae Hyun Han
IPC分类号： G11C13/00 , H01L27/11553 , H01L27/11539 , G11C16/24 , H01L27/1158
摘要： A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, a gate line structure disposed over the substrate, a gate dielectric layer covering one sidewall surface of the gate line structure and disposed over the substrate, a channel layer disposed to cover the gate dielectric layer and disposed over the substrate, a bit line structure and a resistance change structure to contact different portions of the channel layer over the substrate, and a source line structure disposed in the resistance change structure. The gate line structure includes at least one gate electrode layer pattern and interlayer insulation layer pattern that are alternately stacked along a first direction perpendicular to the substrate, and extends in a second direction perpendicular to the first direction.

43. 发明授权

US11107829B2 Method of manufacturing a three-dimensional non-volatile memory device 有权
公开(公告)号：US11107829B2
公开(公告)日：2021-08-31
申请号：US16562100
申请日：2019-09-05
申请人： SK hynix Inc.
发明人： Eun Mee Kwon , Da Som Lee
IPC分类号： H01L27/1158 , H01L27/11573 , H01L27/11565 , H01L27/11519 , H01L27/11514 , H01L27/11553 , H01L27/11504 , H01L27/11509 , H01L27/11526
摘要： In a method of manufacturing a non-volatile memory device, insulating layers and conductive gates may be alternately formed on a semiconductor substrate to form a stack structure. A contact hole may be formed through the stack structure. A channel layer may be formed on a surface of the contact hole. The contact hole may be filled with a gap-fill insulating layer. The gap-fill insulating layer may be etched by a target depth to define a preliminary junction region. The channel layer may be etched until a surface of the channel layer may correspond to a surface of an uppermost gate among the gates. Diffusion-preventing ions may be implanted into the channel layer. A capping layer with impurities may be formed in the preliminary junction region.

44. 发明授权

US11101282B2 Semiconductor storage device 有权
公开(公告)号：US11101282B2
公开(公告)日：2021-08-24
申请号：US16560600
申请日：2019-09-04
申请人： TOSHIBA MEMORY CORPORATION
发明人： Hiroyasu Sato
IPC分类号： H01L27/11573 , H01L27/11565 , H01L27/11553 , H01L27/11519 , H01L27/11526 , H01L27/1158
摘要： According to one embodiment, a semiconductor storage device includes: a substrate; a plurality of first gate electrodes arranged in a first direction intersecting with a substrate surface; a first semiconductor film extending in the first direction and facing the plurality of first gate electrodes; a first gate insulating film provided between the plurality of first gate electrodes and the first semiconductor film; a second gate electrode disposed farther away from the substrate than the plurality of first gate electrodes; a second semiconductor film that extends in the first direction, faces the second gate electrode, and has, in the first direction, one end connected to the first semiconductor film; and a second gate insulating film provided between the second gate electrode and the second semiconductor film. The second gate electrode includes: a first portion; and a second portion provided between the first portion and the second semiconductor film, and facing the second semiconductor film. At least a portion of the second portion is provided closer to a side of the substrate than a surface of the first portion on the side of the substrate side in the first direction.

45. 发明申请

US20210233922A1 Integrated Assemblies and Methods of Forming Integrated Assemblies 有权
公开(公告)号：US20210233922A1
公开(公告)日：2021-07-29
申请号：US17229672
申请日：2021-04-13
申请人： Micron Technology, Inc.
发明人： Justin B. Dorhout , Kunal R. Parekh , Martin C. Roberts , Mohd Kamran Akhtar , Chet E. Carter , David Daycock
IPC分类号： H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11582 , H01L21/308 , H01L21/311 , H01L21/033 , H01L21/768 , H01L27/112 , H01L21/67 , H01L21/3215 , H01L27/11553
摘要： Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region are majority doped with a same dopant type. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending across a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends outwardly from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

46. 发明申请

US20200321057A1 SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME 审中-公开
公开(公告)号：US20200321057A1
公开(公告)日：2020-10-08
申请号：US16905742
申请日：2020-06-18
申请人： TowerJazz Panasonic Semiconductor Co., Ltd.
发明人： Hiroshige HIRANO , Hiroaki KURIYAMA
IPC分类号： G11C16/14 , G11C16/04 , H01L27/11546 , H01L27/11553
摘要： A semiconductor device includes a memory cell formed on a semiconductor substrate. The memory cell includes a first source region and a first drain region that are formed in the semiconductor substrate and a first selection gate, and a first floating gate disposed in series between the first source region and the first drain region. A first floating gate transistor including the first drain region and the first floating gate has a threshold set lower than a threshold of a first selection gate transistor including the first source region and the first selection gate.

47. 发明授权

US10741573B2 Semiconductor memory 有权
公开(公告)号：US10741573B2
公开(公告)日：2020-08-11
申请号：US16287233
申请日：2019-02-27
申请人： Toshiba Memory Corporation
发明人： Go Oike
IPC分类号： H01L27/11578 , H01L27/11582 , H01L23/528 , H01L27/11556 , H01L23/522 , H01L27/11551 , H01L27/11514 , H01L27/1156 , H01L27/11521 , H01L27/11553 , H01L27/1157 , H01L27/06 , H01L23/532
摘要： A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.

48. 发明授权

US10607988B2 Apparatuses having memory cells with two transistors and one capacitor, and having body regions of the transistors coupled with reference voltages 有权
公开(公告)号：US10607988B2
公开(公告)日：2020-03-31
申请号：US16398501
申请日：2019-04-30
申请人： Micron Technology, Inc.
发明人： Kamal M. Karda , Chandra Mouli , Srinivas Pulugurtha , Rajesh N. Gupta
IPC分类号： H01L27/112 , H01L27/07 , H01L27/108 , H01L49/02 , G11C11/4074 , H01L29/08 , H01L27/11556 , H01L21/8234 , H01L21/84 , H01L21/8238 , H01L27/11582 , G11C11/408 , H01L27/11553 , H01L29/92 , G11C5/14 , G11C5/06
摘要： Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

49. 发明申请

US20200058663A1 Integrated Assemblies and Methods of Forming Integrated Assemblies 审中-公开
公开(公告)号：US20200058663A1
公开(公告)日：2020-02-20
申请号：US16663068
申请日：2019-10-24
申请人： Micron Technology, Inc.
发明人： Justin B. Dorhout , Kunal R. Parekh , Martin C. Roberts , Mohd Kamran Akhtar , Chet E. Carter , David Daycock
IPC分类号： H01L27/11524 , H01L27/11553 , H01L27/11582 , H01L27/11556 , H01L27/11551
摘要： Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

50. 发明申请

US20190273120A1 CELL PILLAR STRUCTURES AND INTEGRATED FLOWS 审中-公开
公开(公告)号：US20190273120A1
公开(公告)日：2019-09-05
申请号：US16253111
申请日：2019-01-21
申请人： Micron Technology, Inc.
发明人： Fatma Arzum Simsek-Ege , Krishna K. Parat
IPC分类号： H01L27/24 , H01L45/00 , H01L27/11553 , H01L27/1158 , H01L29/788 , H01L29/66 , H01L29/792
摘要： Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

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