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41. 发明授权

US06629169B2 Apparatus and method for testing of USB device 有权
公开(公告)号：US06629169B2
公开(公告)日：2003-09-30
申请号：US09808577
申请日：2001-03-14
申请人： Ping-Ying Chu
发明人： Ping-Ying Chu
IPC分类号： G06F1314
CPC分类号： G06F13/426 , G06F2213/0042
摘要： A USB device is coupled to a first USB communication line and a second USB communication line. Separate first and second paths are created between an external device and a controller in the USB device, with both paths including the first and second USB communication lines. The USB device detects whether a USB connection exists over the first and second USB communication lines. If a USB connection exists over the first and second USB communication lines, USB communication is routed via the first path. Otherwise, testing communication is routed via the second path. The external device can be either a USB host or a testing unit.

42. 发明授权

US06625676B1 Small computer system with interface control and method of operating same 有权
标题翻译：具有接口控制的小型计算机系统和操作方法相同
公开(公告)号：US06625676B1
公开(公告)日：2003-09-23
申请号：US09640181
申请日：2000-08-17
申请人： Stephen Gold , Jon Bathie
发明人： Stephen Gold , Jon Bathie
IPC分类号： G06F1314
CPC分类号： G06F3/0626 , G06F3/065 , G06F3/0689
摘要： Diagnostic data in a sequential access Small Computer System Interface device is accessed by a first logical unit. A second logical unit is configurable to control a mode of operation of the first logical unit. The first unit Provides normal and/or backup functions while the second unit provides diagnostic/status functions or the second unit activates the first unit to be online or offline, depending on the first unit being commanded to perform the diagnostic function.
摘要翻译：顺序访问中的诊断数据小型计算机系统接口设备由第一个逻辑单元访问。第二逻辑单元可配置为控制第一逻辑单元的操作模式。第一个单元提供正常和/或备份功能，而第二个单元提供诊断/状态功能，或者第二个单元激活第一个单元处于联机或离线状态，这取决于被命令执行诊断功能的第一个单元。

43. 发明授权

US06624817B1 Symmetrical accelerated graphics port (AGP) 有权
标题翻译：对称加速图形端口（AGP）
公开(公告)号：US06624817B1
公开(公告)日：2003-09-23
申请号：US09476661
申请日：1999-12-31
申请人： Brian K. Langendorf
发明人： Brian K. Langendorf
IPC分类号： G06F1314
CPC分类号： G09G5/363 , G06F3/14 , G09G2360/06
摘要： Apparatus and methods are provided for allowing two graphics controllers to cooperate on a single screen and for modifying the AGP protocol to provide symmetric capabilities for both AGP targets and AGP masters. According to one embodiment of the present invention, an Accelerated Graphics Port (AGP) master may initiate a data transaction. A graphics controller receives an AGP transaction request from a core logic device. The graphics controller buffers the AGP transaction request in a request queue. Then, the graphics controller initiates a data transaction in response to the AGP transaction request. According to another embodiment of the present invention, an AGP target may issue AGP transaction requests. The integrated graphics controller issues an AGP transaction request to a graphics controller residing on an expansion card. Subsequently, the integrated graphics controller receives an indication on a status bus that the graphics controller residing on the expansion card is ready to initiate a data transaction in response to the AGP transaction request. If the AGP transaction request is an AGP read transaction, then the integrated graphics controller receives read data from the graphics controller. Otherwise, if the AGP transaction request is an AGP write transaction, then the integrated graphics controller sources write data to the graphics controller residing on the expansion card.
摘要翻译：提供了装置和方法，用于允许两个图形控制器在单个屏幕上协作并且用于修改AGP协议以为AGP目标和AGP主机提供对称能力。根据本发明的一个实施例，加速图形端口（AGP）主机可以发起数据事务。图形控制器从核心逻辑器件接收AGP事务请求。图形控制器在请求队列中缓存AGP事务请求。然后，图形控制器响应于AGP事务请求发起数据事务。根据本发明的另一实施例，AGP目标可以发出AGP事务请求。集成图形控制器向位于扩展卡上的图形控制器发出AGP事务请求。随后，集成图形控制器在状态总线上接收驻留在扩展卡上的图形控制器准备好响应于AGP事务请求发起数据事务的指示。如果AGP事务请求是AGP读取事务，则集成图形控制器从图形控制器接收读取数据。否则，如果AGP事务请求是AGP写入事务，则集成图形控制器将数据写入驻留在扩展卡上的图形控制器。

44. 发明授权

US06618783B1 Method and system for managing a PCI bus coupled to another system 失效
标题翻译：用于管理耦合到另一系统的PCI总线的方法和系统
公开(公告)号：US06618783B1
公开(公告)日：2003-09-09
申请号：US09430369
申请日：1999-10-29
申请人： Peter J. Hammersley
发明人： Peter J. Hammersley
IPC分类号： G06F1314
CPC分类号： G06F11/2033 , G06F11/2005 , G06F11/2035
摘要： The present invention provides a PCI bus switching architecture to allow a pair of PCI processors to have access to a common set of PCI I/O cards. More specifically, this design allows either cross-coupled processor to dynamically take over the operational controls of the common set of PCI I/O cards if the primary processor for the same become inoperative. The present invention achieves the objective by employing a point to point data link connection between each processor and their respective controllers for each common set of PCI I/O cards associated with a PCI bus.
摘要翻译：本发明提供了一种PCI总线交换架构，以允许一对PCI处理器访问一组共同的PCI I / O卡。更具体地说，这种设计允许交叉耦合处理器动态地接管普通PCI I / O卡组的操作控制，如果它们的主处理器变得不起作用。本发明通过对与PCI总线相关联的每个公共PCI I / O卡集合采用每个处理器及其相应控制器之间的点对点数据链路连接来实现目的。

45. 发明授权

US06615295B2 Relaxed read completion ordering in a system using transaction order queue 失效
公开(公告)号：US06615295B2
公开(公告)日：2003-09-02
申请号：US09749111
申请日：2000-12-26
申请人： Paras A. Shah
发明人： Paras A. Shah
IPC分类号： G06F1314
CPC分类号： G06F13/1626
摘要： A technique is provided for automatically bypassing a transaction order queue for read completion transactions. The technique incorporates logic within an ASIC bridge, wherein read completion transactions are designated a relaxed ordering attribute value. Logic within the ASIC facilitates the read transactions by bypassing the transaction order queue if the relaxed ordering attribute is set accordingly. Similarly, the logic disables the attribute and enqueues the read completion transaction into the transaction order queue, if the relaxed ordering attribute is set to logical zero.

46. 发明授权

US06615230B2 Data access right management apparatus in a data-independent computer system 失效
标题翻译：数据访问权管理装置在数据无关的计算机系统中
公开(公告)号：US06615230B2
公开(公告)日：2003-09-02
申请号：US09093937
申请日：1998-06-09
申请人： Takeshi Nishimura
发明人： Takeshi Nishimura
IPC分类号： G06F1314
CPC分类号： H04L63/102 , G06F21/31 , G06F21/6218 , H04L29/06 , H04L63/101 , H04L63/20
摘要： The computer system has a processing machine for receiving an electronic message including a request of a transaction from a network, transmitting an electronic message including results of the transaction to the network, and executing the transaction processes corresponding to transmitted/received electronic messages. The computer system also has a data machine for receiving the electronic message including the request of the data accesses from the network, transmitting the electronic message including the results of the data accesses to the network. The computer system also has a man-machine interface machine for transmitting the electronic message including the results of the transaction to the network, receiving the electronic message including the results of the transaction form the network. This computer system includes a network manager for managing access rights of respective users for accessing the processing machine and the data machine connected to the network.
摘要翻译：计算机系统具有处理机器，用于接收包括来自网络的交易请求的电子消息，将包括交易结果的电子消息发送到网络，以及执行与发送/接收的电子消息相对应的交易处理。计算机系统还具有数据机，用于接收包括来自网络的数据访问请求的电子消息，发送包括对网络的数据访问结果的电子消息。计算机系统还具有用于将包括交易结果的电子消息发送到网络的人机界面机器，从网络接收包括交易结果的电子消息。该计算机系统包括网络管理器，用于管理各个用户访问处理机器和连接到网络的数据机器的访问权限。

47. 发明授权

US06614698B2 Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths 有权
公开(公告)号：US06614698B2
公开(公告)日：2003-09-02
申请号：US09974387
申请日：2001-10-09
申请人： Kevin J. Ryan , Terry R. Lee
发明人： Kevin J. Ryan , Terry R. Lee
IPC分类号： G06F1314
CPC分类号： G06F13/161 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C8/00 , G11C11/4076 , G11C11/4082 , G11C11/4093
摘要： A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and input data until an available interval is located where no read data or read addresses occupy the memory array. During the available interval, data is transferred from the interim data register to a location in the memory array identified by the address in the interim array register. In one embodiment, the SDRAM also includes address and compare logic to prevent reading incorrect data from an address to which the proper data has not yet been written. In another embodiment, a system controller monitors commands and addresses and inserts no operation commands to prevent such collision of data and addresses.

48. 发明授权

US06614437B1 Apparatus and method for efficient memory utilization in an electronic system 失效
标题翻译：一种用于电子系统中有效利用存储器的装置和方法
公开(公告)号：US06614437B1
公开(公告)日：2003-09-02
申请号：US09236822
申请日：1999-01-25
申请人： Chon In Kou , Tomonari Tohara
发明人： Chon In Kou , Tomonari Tohara
IPC分类号： G06F1314
CPC分类号： H04N19/423 , H04N19/61
摘要： An apparatus and method for efficient memory utilization in an electronic system comprises a memory divided into memory units of equal size, a data source, and an interface between the memory and the data source, which manages storage and retrieval of data in the memory. The data source generates first data components and second data components, each of the first data components being larger than each of the second data components. Each memory unit is sized to contain one of the second data components. The memory units are configured as a continuous memory ring. The interface stores the data components sequentially in the memory ring as the data components are generated by the data source. The interface also retrieves the data components sequentially from the memory ring. A control module sends control signals to the interface to control read and write operations for the data components.
摘要翻译：一种用于电子系统中有效的存储器利用的装置和方法包括：分配成相等大小的存储单元的存储器，数据源以及存储器和数据源之间的接口，其管理存储器中的数据的存储和检索。数据源产生第一数据分量和第二数据分量，每个第一数据分量大于每个第二数据分量。每个存储器单元的尺寸被设置为包含第二数据组件之一。存储器单元被配置为连续存储器环。由于数据源由数据分量生成，接口将数据组件顺序存储在存储环中。该接口还从存储环中顺序检索数据组件。控制模块向接口发送控制信号，以控制数据组件的读写操作。

49. 发明授权

US06606717B1 Cache control method and system for mixed streaming and non-streaming data 有权
标题翻译：混合流和非流数据的缓存控制方法和系统
公开(公告)号：US06606717B1
公开(公告)日：2003-08-12
申请号：US09628892
申请日：2000-07-31
申请人： Sharon H. Yu , Gary K. Laatsch , Quoc N. Dang
发明人： Sharon H. Yu , Gary K. Laatsch , Quoc N. Dang
IPC分类号： G06F1314
CPC分类号： G06F12/0866 , G06F2212/312
摘要： The present invention may be embodied in a cache control method for caching disk data in a disk drive configured to receive commands for both streaming and non-streaming data from a host. A lossy state record is provided for memory segments in a cache memory. The lossy state record allows hosts commands to be mixed for streaming and non-streaming data without flushing of cache data for a command mode change.
摘要翻译：本发明可以体现在缓存控制方法中，用于在配置为从主机接收流和非流数据的命令的盘驱动器中缓存磁盘数据。为高速缓冲存储器中的存储器段提供有损状态记录。有损状态记录允许主机命令混合用于流和非数据流数据，而不刷新命令模式更改的缓存数据。

50. 发明授权

US06606678B1 Computer system 失效
标题翻译：电脑系统
公开(公告)号：US06606678B1
公开(公告)日：2003-08-12
申请号：US09605399
申请日：2000-06-28
申请人： Nobutaka Nakamura
发明人： Nobutaka Nakamura
IPC分类号： G06F1314
CPC分类号： G06F13/4059
摘要： In this invention, the bus of a computer body is connected to the bus of an expansion unit through a serial interface so as to implement connection wirings in the form of a serial cable. A PCI-PCI bridge for connecting a primary PCI bus to a secondary PCI bus comprises two physically isolated controllers, i.e., a primary PCI serial transfer controller implemented on the PC body side and a secondary PCI serial transfer controller implemented on the docking station side. The two controllers are connected to each other through serial LVDS lines. Transactions are exchanged between the primary PCI bus and the secondary PCI bus by serial transfer between the primary PCI serial transfer controller and the secondary PCI serial transfer controller.
摘要翻译：在本发明中，计算机机身的总线通过串行接口连接到扩展单元的总线，以实现串行电缆形式的连接布线。用于将主PCI总线连接到辅助PCI总线的PCI-PCI桥接器包括两个物理隔离的控制器，即在PC主体侧实现的主PCI串行传输控制器和在对接站侧上实现的辅助PCI串行传输控制器。两个控制器通过串行LVDS线相互连接。通过主PCI串行传输控制器和辅助PCI串行传输控制器之间的串行传输，在主PCI总线和辅助PCI总线之间交换交易。

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