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41. 发明申请

US20120074094A1 Manufacturing Method for Forming Circuit Structure on Non-Conductive Carrier 审中-公开
标题翻译：在非导电载体上形成电路结构的制造方法
公开(公告)号：US20120074094A1
公开(公告)日：2012-03-29
申请号：US13206047
申请日：2011-08-09
申请人： Cheng-Feng Chiang , Jung-Chuan Chiang , Wei-Cheng Fu
发明人： Cheng-Feng Chiang , Jung-Chuan Chiang , Wei-Cheng Fu
IPC分类号： H05K3/10 , H05K3/22 , B82Y99/00
CPC分类号： H05K3/185 , H01L21/4846 , H01L2924/0002 , H05K2201/0236 , H05K2203/0709 , H05K2203/107 , H01L2924/00
摘要： A manufacturing method of forming an electrical circuit on a non-conductive carrier comprises following steps. After providing an electrically non-conductive carrier, catalysts are dispersed on or in the electrically non-conductive carrier. A predetermined track structure is formed on the electrically non-conductive carrier to expose the catalysts on the surface of the predetermined track structure. The surface of the predetermined track structure containing the catalysts is metalized to form a conductor track.
摘要翻译：在非导电载体上形成电路的制造方法包括以下步骤。在提供非导电载体之后，催化剂分散在非导电载体上或其中。在非导电载体上形成预定的轨道结构，以暴露预定轨道结构表面上的催化剂。包含催化剂的预定轨道结构的表面被金属化以形成导体轨迹。

42. 发明授权

US08124226B2 Flexible circuits 有权
标题翻译：柔性电路
公开(公告)号：US08124226B2
公开(公告)日：2012-02-28
申请号：US13078831
申请日：2011-04-01
申请人： Sunity Sharma , Jaspreet Singh Dhau
发明人： Sunity Sharma , Jaspreet Singh Dhau
IPC分类号： B32B9/00
CPC分类号： C23C18/2033 , C23C18/1653 , C23C18/30 , H05K1/0284 , H05K1/0393 , H05K3/182 , H05K2201/0999 , H05K2203/0709 , Y10S428/901 , Y10T428/24917 , Y10T428/2857
摘要： The present invention provides a circuit creation technology that improves conductive line manufacture by adding active and elemental palladium onto the surface of a substrate. The palladium is disposed in minute amounts on the surface and does not form a conductive layer by itself, but facilitates subsequent deposition of a metal onto the surface, according to the pattern of the palladium, to form the conductive lines.
摘要翻译：本发明提供一种电路创建技术，其通过将活性和元素钯添加到基底的表面上来改善导线生产。钯在表面上以微量的形式设置，并且本身不形成导电层，但是根据钯的图案有助于随后将金属沉积到表面上以形成导电线。

43. 发明申请

US20100310761A1 PROCESS FOR PRODUCING TRANSPARENT ELECTROCONDUCTIVE MEMBER 审中-公开
标题翻译：生产透明电极成员的工艺
公开(公告)号：US20100310761A1
公开(公告)日：2010-12-09
申请号：US12734608
申请日：2008-11-11
申请人： Masanori Tsubota , Hidekazu Shiomi , Hiroshi Ogata
发明人： Masanori Tsubota , Hidekazu Shiomi , Hiroshi Ogata
IPC分类号： H05K3/12
CPC分类号： H05K3/1208 , H05K3/182 , H05K3/207 , H05K3/386 , H05K2201/0116 , H05K2201/0209 , H05K2203/0113 , H05K2203/0709
摘要： [PROBLEMS] To provide a method for forming a high-definition electroconductive thin line free from blurring at low cost.[MEANS FOR SOLVING PROBLEMS] A resin film having a hardness of 20 to 70, as measured by a type A measuring method specified in JIS K 6253, is formed on a surface of a resin base material. A thin line pattern is formed on the resin film using an electroconductive paste by intaglio printing or stencil printing or using an electroless plating catalyst ink by intaglio printing or stencil printing. Subsequently, a metal film is formed on the thin line pattern by plating to form an electroconductive thin line.
摘要翻译： [问题]提供一种低成本地形成高分辨率导电细线不会模糊的方法。解决问题的手段根据JIS K 6253规定的A型测定方法测定硬度为20〜70的树脂膜，形成在树脂基材的表面上。使用导电糊通过凹版印刷或模板印刷或使用无电镀催化剂油墨通过凹版印刷或模版印刷在树脂膜上形成细线图案。随后，通过电镀在薄线图案上形成金属膜以形成导电细线。

44. 发明申请

US20100132986A1 Method for preparing a conductive feature on a substrate 审中-公开
标题翻译：在基板上制备导电特征的方法
公开(公告)号：US20100132986A1
公开(公告)日：2010-06-03
申请号：US12382006
申请日：2009-03-05
申请人： Jurgen Hackert , Paul Tranter , Joost Hubert Maas
发明人： Jurgen Hackert , Paul Tranter , Joost Hubert Maas
IPC分类号： H05K1/09 , C25D5/02 , C23C28/02
CPC分类号： H05K3/182 , C25D5/02 , H05K3/125 , H05K3/246 , H05K3/381 , H05K2201/0347 , H05K2203/013 , H05K2203/0709 , H05K2203/107 , H05K2203/121
摘要： The invention provides method for preparing a conductive device comprising the steps of: (a) providing a non-conductive substrate layer; (b) modifying the surface of the non-conductive substrate layer by means of a laser beam treatment; (c) applying a pattern of an ink on a surface of the substrate layer, which ink comprises a first metal; (d) depositing a second metal on the ink pattern obtained in step (c); and (e) applying a third metal on the second metal by means of electrodeposition. The invention further provides a conductive device obtainable by said method.
摘要翻译：本发明提供了一种制备导电器件的方法，包括以下步骤：（a）提供非导电衬底层; （b）通过激光束处理改性非导电基底层的表面; （c）在基材层的表面上施加油墨图案，该油墨包括第一金属; （d）在步骤（c）中获得的油墨图案上沉积第二金属; 和（e）通过电沉积在第二金属上施加第三金属。本发明还提供可通过所述方法获得的导电装置。

45. 发明授权

US07661186B2 Fabrication method of radio frequency identification antenna coil 有权
标题翻译：射频识别天线线圈制作方法
公开(公告)号：US07661186B2
公开(公告)日：2010-02-16
申请号：US11590856
申请日：2006-11-01
申请人： Chung-Wei Wang , Yung-Kuo Ho , Ming-Huan Yang , Chia-Chi Wu , Chao-Kai Cheng
发明人： Chung-Wei Wang , Yung-Kuo Ho , Ming-Huan Yang , Chia-Chi Wu , Chao-Kai Cheng
IPC分类号： H01Q17/00
CPC分类号： H01Q7/00 , H01Q1/2208 , H05K1/165 , H05K3/182 , H05K3/381 , H05K2201/0338 , H05K2201/086 , H05K2203/013 , H05K2203/0709 , Y10T29/49018 , Y10T29/49071 , Y10T29/49073 , Y10T29/4908
摘要： A fabrication method of a radio frequency identification (RFID) antenna coil is provided. First, a substrate is processed by a surface modified procedure, to form a self-assembly membranes (SAMs) on a surface of the substrate. A catalyst is sprayed on the SAMs of the substrate according to patterning. After that, the first electroless plating procedure is first carried out for the substrate to generate a magnetic metal layer corresponding to the wiring pattern on the catalyst, and the second electroless plating procedure is then carried out for the substrate to generate the metal layer on the magnetic metal layer.
摘要翻译：提供射频识别（RFID）天线线圈的制造方法。首先，通过表面改性方法处理衬底，以在衬底的表面上形成自组装膜（SAM）。根据图案化将催化剂喷涂在基板的SAM上。之后，首先对基板进行第一次化学镀处理，以生成与催化剂上的布线图形对应的磁性金属层，然后对基板进行第二无电镀处理，以在基板上产生金属层磁性金属层。

46. 发明申请

US20090280239A1 METHOD OF MANUFACTURING PRINTED CIRCUIT BOARD 审中-公开
标题翻译：制造印刷电路板的方法
公开(公告)号：US20090280239A1
公开(公告)日：2009-11-12
申请号：US12425792
申请日：2009-04-17
申请人： Shigenori MORITA , Takashi ODA , Naoko YOSHIDA
发明人： Shigenori MORITA , Takashi ODA , Naoko YOSHIDA
IPC分类号： H05K3/00
CPC分类号： H05K3/107 , H05K3/182 , H05K2203/0108 , H05K2203/0338 , H05K2203/0709
摘要： First, a catalyst for performing electroless plating in a subsequent step is caused to adhere to surfaces of uneven portions of a matrix. Next, an insulating layer made of a resin material is prepared. Then, the insulating layer is heated to be softened while the uneven portions of the matrix are pressed against one surface of the insulating layer. Thus, grooves corresponding to shapes of the uneven portions of the matrix are formed in the insulating layer while the catalyst is transferred to bottom surfaces and side surfaces of the grooves. The insulating layer is then subjected to electroless plating. In this case, metal is deposited by reduction reaction on portions of the insulating layer where the catalyst exists. Accordingly, conductor traces are formed in the grooves of the insulating layer.
摘要翻译：首先，在随后的步骤中进行无电镀的催化剂附着在基体的不均匀部分的表面。接着，制备由树脂材料制成的绝缘层。然后，将绝缘层加热软化，同时将基体的不均匀部分压在绝缘层的一个表面上。因此，在催化剂转移到槽的底面和侧面的同时，在绝缘层中形成对应于矩阵的不平坦部分的形状的凹槽。然后对绝缘层进行化学镀。在这种情况下，通过还原反应将金属沉积在存在催化剂的绝缘层的部分上。因此，导体迹线形成在绝缘层的沟槽中。

47. 发明申请

US20080304213A1 Process for manufacturing a cover 审中-公开
标题翻译：盖子制造工艺
公开(公告)号：US20080304213A1
公开(公告)日：2008-12-11
申请号：US12221846
申请日：2008-08-06
申请人： Kenichi Hashizume , Takaharu Fujii
发明人： Kenichi Hashizume , Takaharu Fujii
IPC分类号： H05K5/03
CPC分类号： H05K1/119 , H01R9/226 , H01R13/50 , H01R43/24 , H05K1/0284 , H05K3/0014 , H05K3/182 , H05K2201/09118 , H05K2201/0999 , H05K2203/0709
摘要： A process of manufacturing a cover for an electronic device, the process comprising forming the cover for the device, incorporating electrical circuitry into the cover during the formation, and providing on the cover an integral connector structure for connecting the electrical circuitry to an electronic component.
摘要翻译：一种制造用于电子设备的盖的方法，该方法包括形成用于该装置的盖，在形成期间将电路并入盖中，以及在盖上提供用于将电路连接到电子部件的整体连接器结构。

48. 发明授权

US07350297B2 Method of manufacturing a wiring substrate 有权
标题翻译：制造布线基板的方法
公开(公告)号：US07350297B2
公开(公告)日：2008-04-01
申请号：US11356215
申请日：2006-02-17
申请人： Naoko Yamaguchi , Hideo Aoki
发明人： Naoko Yamaguchi , Hideo Aoki
IPC分类号： H01K3/10
CPC分类号： H05K3/422 , H05K3/1266 , H05K3/182 , H05K3/4084 , H05K2201/09081 , H05K2201/091 , H05K2201/09563 , H05K2201/09827 , H05K2203/0221 , H05K2203/0517 , H05K2203/0709 , Y10T29/49117 , Y10T29/49124 , Y10T29/49155 , Y10T29/49165 , Y10T29/49167 , Y10T428/24917
摘要： A first plating foundation layer is formed by printing on a front face of a sheet-shaped insulating substrate. By inserting a punch into the sheet-shaped insulating substrate having the first plating foundation layer, a through hole is formed while leaving a piece having the plating foundation layer in the portion where the punch is inserted. A second plating foundation layer is formed by printing on a rear face of the sheet-shaped insulating substrate. A first and second wiring layers composed of a metal plating layer are formed by performing electroless plating, and at the same time, a metal plating layer connecting between the first and second wiring layers is formed in the through hole using the plating foundation layer on the piece.
摘要翻译：通过在片状绝缘基板的正面上印刷形成第一电镀基础层。通过在具有第一电镀基础层的片状绝缘基板上插入冲头，在将冲压件插入部分留下具有电镀基础层的部件的同时形成通孔。通过在片状绝缘基板的背面上印刷形成第二电镀基础层。通过进行无电解电镀形成由金属镀层构成的第一和第二配线层，同时，在通孔中形成连接在第一和第二布线层之间的金属镀层，使用电镀基底层片。

49. 发明申请

US20070153488A1 Multi-Layer Printed Circuit Board and Method for Fabricating the Same 有权
标题翻译：多层印刷电路板及其制造方法
公开(公告)号：US20070153488A1
公开(公告)日：2007-07-05
申请号：US11554882
申请日：2006-10-31
申请人： Ming-Huan Yang , Chung-Wei Wang , Chia-Chi Wu , Chao-Kai Cheng , Tzyy-Jang Tseng , Chang-Ming Lee , Cheng-Po Yu , Cheng-Hung Yu
发明人： Ming-Huan Yang , Chung-Wei Wang , Chia-Chi Wu , Chao-Kai Cheng , Tzyy-Jang Tseng , Chang-Ming Lee , Cheng-Po Yu , Cheng-Hung Yu
IPC分类号： H05K7/00 , H05K3/10
CPC分类号： H05K3/182 , H05K3/389 , H05K3/421 , H05K3/422 , H05K3/426 , H05K3/4661 , H05K2203/013 , H05K2203/0565 , H05K2203/0709 , Y10T29/49155
摘要： A method for fabricating a double-sided or multi-layer printed circuit board (PCB) by ink-jet printing that includes providing a substrate, forming a first self-assembly membrane (SAM) on at least one side of the substrate, forming a non-adhesive membrane on the first SAM, forming at least one microhole in the substrate, forming a second SAM on a surface of the microhole, providing catalyst particles on the at least one side of the substrate and on the surface of the microhole, and forming a catalyst circuit pattern on the substrate.
摘要翻译：一种通过喷墨印刷制造双面或多层印刷电路板（PCB）的方法，其包括提供基板，在所述基板的至少一侧上形成第一自组装膜（SAM），形成在所述第一SAM上形成非粘性膜，在所述基底中形成至少一个微孔，在所述微孔的表面上形成第二SAM，在所述基底的至少一侧和所述微孔的表面上提供催化剂颗粒，以及在基板上形成催化剂电路图案。

50. 发明申请

US20060194031A1 Wiring substrate and manufacturing method thereof 有权
标题翻译：接线基板及其制造方法
公开(公告)号：US20060194031A1
公开(公告)日：2006-08-31
申请号：US11356215
申请日：2006-02-17
申请人： Naoko Yamaguchi , Hideo Aoki
发明人： Naoko Yamaguchi , Hideo Aoki
IPC分类号： B05D5/12
CPC分类号： H05K3/422 , H05K3/1266 , H05K3/182 , H05K3/4084 , H05K2201/09081 , H05K2201/091 , H05K2201/09563 , H05K2201/09827 , H05K2203/0221 , H05K2203/0517 , H05K2203/0709 , Y10T29/49117 , Y10T29/49124 , Y10T29/49155 , Y10T29/49165 , Y10T29/49167 , Y10T428/24917
摘要： A first plating foundation layer is formed by printing on a front face of a sheet-shaped insulating substrate. By inserting a punch into the sheet-shaped insulating substrate having the first plating foundation layer, a through hole is formed while leaving a piece having the plating foundation layer in the portion where the punch is inserted. A second plating foundation layer is formed by printing on a rear face of the sheet-shaped insulating substrate. A first and second wiring layers composed of a metal plating layer are formed by performing electroless plating, and at the same time, a metal plating layer connecting between the first and second wiring layers is formed in the through hole using the plating foundation layer on the piece.
摘要翻译：通过在片状绝缘基板的正面上印刷形成第一电镀基础层。通过在具有第一电镀基础层的片状绝缘基板上插入冲头，在将冲压件插入部分留下具有电镀基础层的部件的同时形成通孔。通过在片状绝缘基板的背面上印刷形成第二电镀基础层。通过进行无电解电镀形成由金属镀层构成的第一和第二配线层，同时，在通孔中形成连接在第一和第二布线层之间的金属镀层，使用电镀基底层片。

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