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41. 发明申请

US20100282503A1 MULTI-LAYER SUBSTRATE 有权
标题翻译：多层基板
公开(公告)号：US20100282503A1
公开(公告)日：2010-11-11
申请号：US12675678
申请日：2007-08-31
申请人： Taras Kushta
发明人： Taras Kushta
IPC分类号： H05K1/11
CPC分类号： H05K1/0251 , H05K1/0219 , H05K1/0222 , H05K1/0245 , H05K1/116 , H05K3/429 , H05K2201/09236 , H05K2201/09454 , H05K2201/09618 , H05K2201/09636 , H05K2201/09718 , H05K2201/09781
摘要： A multi-layer substrate includes a planar transmission line structure and a signal via, which are connected by a multi-tier transition. The multi-tier transition includes a signal via pad configured to serve for a full-value connection of the signal via and the planar transmission line; and a dummy pad connected to the signal via, formed in an area of a clearance hole in a conductor layer disposed between a signal terminal of the signal via and the planar transmission line, and isolated from the conductor layer.
摘要翻译：多层基板包括通过多层转换连接的平面传输线结构和信号通孔。多层转换包括经配置以用于信号通孔和平面传输线的全值连接的信号通孔; 以及连接到信号通孔的虚拟焊盘，形成在设置在信号通孔的信号端子和平面传输线之间并与导体层隔离的导体层中的间隙孔的区域中。

42. 发明申请

US20100242271A1 DIELECTRIC LAMINATION STRUCTURE, MANUFACTURING METHOD OF A DIELECTRIC LAMINATION STRUCTURE, AND WIRING BOARD INCLUDING A DIELECTRIC LAMINATION STRUCTURE 有权
标题翻译：电介质层压结构，电介质层压结构的制造方法和包括电介质层压结构的接线板
公开(公告)号：US20100242271A1
公开(公告)日：2010-09-30
申请号：US12785037
申请日：2010-05-21
申请人： Yasuhiko Inui , Takamichi Ogawa , Seiji Ichiyanagi , Jun Otsuka , Manabu Sato
发明人： Yasuhiko Inui , Takamichi Ogawa , Seiji Ichiyanagi , Jun Otsuka , Manabu Sato
IPC分类号： H05K3/00
CPC分类号： H05K1/162 , H01L21/4857 , H01L23/49822 , H01L23/50 , H01L2924/0002 , H01L2924/09701 , H05K1/092 , H05K3/4644 , H05K2201/0175 , H05K2201/0352 , H05K2201/0355 , H05K2201/09309 , H05K2201/09509 , H05K2201/09718 , H05K2201/09736 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165 , Y10T29/4981 , Y10T407/1946 , Y10T407/1948 , H01L2924/00
摘要： A dielectric structure including a metal foil, a dielectric layer and a conductor layer provided in this order, wherein the metal foil has a thickness of from 10 to 40 μm, the dielectric layer has a thickness of from 0.3 to 5 μm, and the conductor layer has a thickness of from 0.3 to 10 μm. The dielectric structure has plural vias which are separated from each other, and which penetrate through both of the dielectric layer and the conductor layer. The vias of the dielectric layer have different diameters which are in a range of from 100 to 300 μm, a diameter of each of the vias of the conductor layer is larger than a diameter of a corresponding via of the dielectric layer by 5 to 50 μm, and a minimum via pitch is from 100 to 350 μm.
摘要翻译：包括依次设置的金属箔，电介质层和导体层的电介质结构体，其中金属箔的厚度为10〜40μm，电介质层的厚度为0.3〜5μm，导体层的厚度为0.3〜10μm。电介质结构具有彼此分离并且穿透介电层和导体层两者的多个通孔。电介质层的通孔具有不同的直径，范围为100〜300μm，导体层的通孔的直径大于电介质层的通孔的直径为5〜50μm ，最小通孔间距为100〜350μm。

43. 发明申请

US20100188167A1 KU-BAND DIPLEXER 有权
公开(公告)号：US20100188167A1
公开(公告)日：2010-07-29
申请号：US12376738
申请日：2007-09-07
申请人： Jeff Devereux , Fritz Gerd Berger , William A. Johnston , Mohammad Ali Tassoudji , Scott Aldern
发明人： Jeff Devereux , Fritz Gerd Berger , William A. Johnston , Mohammad Ali Tassoudji , Scott Aldern
IPC分类号： H01P5/12
CPC分类号： H01P5/085 , H05K1/0243 , H05K1/116 , H05K3/3447 , H05K2201/09718 , H05K2201/09809 , Y10T29/49139
摘要： A compact Ku band microwave diplexer configured as a three port surface mount component on a miniature alumina substrate. Input signals occurring at a common port having frequencies within a first pass band are passed to a second port while being isolated from signals occurring at a third port. Signals occurring at the third port are passed to the common port while being isolated from the signals at the second port. A microstrip dual spur line filter is used combined with open circuit stubs to provide enhanced second harmonic suppression on the transmit side, while using a coupled line microstrip filter on the receive side. This approach allows for compact size and automated component assembly through pick and place and reflow manufacturing techniques.
摘要翻译：在微型氧化铝基板上构造为三端口表面安装部件的紧凑型Ku波段微波双工器。在具有第一通带内的频率的公共端口处发生的输入信号被传递到第二端口，同时与在第三端口处发生的信号隔离。在第三个端口发生的信号被传递到公共端口，同时与第二个端口的信号隔离。微带双支路线路滤波器与开路短路组合使用，以在发射侧提供增强的二次谐波抑制，同时在接收侧使用耦合线路微带滤波器。这种方法允许通过拾取和放置和回流制造技术实现紧凑的尺寸和自动部件组装。

44. 发明授权

US07745737B2 Printed circuit board having vias 有权
标题翻译：具有通孔的印刷电路板
公开(公告)号：US07745737B2
公开(公告)日：2010-06-29
申请号：US11478922
申请日：2006-06-30
申请人： Yu-Hsu Lin , Shang-Tsang Yeh , Chao-Chen Huang , Chuan-Bing Li
发明人： Yu-Hsu Lin , Shang-Tsang Yeh , Chao-Chen Huang , Chuan-Bing Li
IPC分类号： H01R12/04 , H05K1/11 , H01K3/22
CPC分类号： H05K1/116 , H05K1/0216 , H05K3/429 , H05K2201/0352 , H05K2201/09509 , H05K2201/09536 , H05K2201/09718 , Y10T29/49165
摘要： A printed circuit board (PCB) having vias for reducing reflections of input signals includes a first signal layer, a second signal layer, one via, an input signal line arranged on the first signal layer, and an output signal line arranged on the second signal layer. The via further includes a drill hole, a first pad, and a second pad. The first pad is electrically connected with the input signal line, and the second pad is electrically connected with the output signal line. An outer diameter of the first pad is smaller than an outer diameter of the second pad.
摘要翻译：具有用于减少输入信号的反射的通孔的印刷电路板（PCB）包括第一信号层，第二信号层，一个通孔，布置在第一信号层上的输入信号线和布置在第二信号上的输出信号线层。通孔还包括钻孔，第一垫和第二垫。第一焊盘与输入信号线电连接，第二焊盘与输出信号线电连接。第一垫的外径小于第二垫的外径。

45. 发明授权

US07738257B2 Microelectronic device including bridging interconnect to top conductive layer of passive embedded structure and method of making same 有权
标题翻译：微电子器件包括桥接互连到被动嵌入式结构的顶层导电层及其制造方法
公开(公告)号：US07738257B2
公开(公告)日：2010-06-15
申请号：US11610385
申请日：2006-12-13
申请人： Islam Salama , Yongki Min , Huankiat Seh
发明人： Islam Salama , Yongki Min , Huankiat Seh
IPC分类号： H05K1/18
CPC分类号： H05K1/162 , H05K1/0269 , H05K3/4644 , H05K3/4652 , H05K2201/0175 , H05K2201/09309 , H05K2201/09509 , H05K2201/09563 , H05K2201/096 , H05K2201/09627 , H05K2201/09718 , H05K2201/09918 , H05K2203/0353 , Y10T29/4913 , Y10T29/49155
摘要： A microelectronic device, a method of fabricating the device, and a system including the device. The device includes: a substrate including a polymer build-up layer, and a passive structure embedded in the substrate. The passive structure includes a top conductive layer overlying the polymer build-up layer, a dielectric layer overlying the top conductive layer, and a bottom conductive layer overlying the dielectric layer. The device further includes a conductive via extending through the polymer build-up layer and electrically insulated from the bottom conductive layer, an insulation material insulating the conductive via from the bottom conductive layer, and a bridging interconnect disposed at a side of the top conductive layer facing away from the dielectric layer, the bridging interconnect electrically connecting the conductive via to the top conductive layer.
摘要翻译：微电子器件，制造该器件的方法以及包括该器件的系统。该装置包括：包含聚合物累积层的基底和嵌入基底中的被动结构。被动结构包括覆盖聚合物积聚层的顶部导电层，覆盖顶部导电层的电介质层和覆盖在电介质层上的底部导电层。该器件还包括延伸穿过聚合物积聚层并与底部导电层电绝缘的导电通孔，将导电通孔与底部导电层绝缘的绝缘材料以及布置在顶部导电层侧面的桥接互连背离电介质层，桥接互连将导电通孔电连接到顶部导电层。

46. 发明授权

US07732913B2 Semiconductor package substrate 有权
标题翻译：半导体封装基板
公开(公告)号：US07732913B2
公开(公告)日：2010-06-08
申请号：US11701767
申请日：2007-02-02
申请人： Tsung-Tien Hsieh , Wen-Jung Chiang , Yu-Po Wang , Cheng-Hsu Hsiao , Sen-Yen Yang
发明人： Tsung-Tien Hsieh , Wen-Jung Chiang , Yu-Po Wang , Cheng-Hsu Hsiao , Sen-Yen Yang
IPC分类号： H01L23/04
CPC分类号： H01L23/49827 , H01L23/64 , H01L2223/6638 , H01L2924/0002 , H01L2924/3011 , H05K1/0245 , H05K1/0251 , H05K1/114 , H05K3/429 , H05K2201/09236 , H05K2201/09636 , H05K2201/09718 , H01L2924/00
摘要： A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one electrically integrated layer formed in the substrate body, and having an opening corresponding to the two adjacent conductive through holes formed as the differential pair and the ball pads thereof. Thus, the spacing between the conductive through holes and the electrically integrated layer and the spacing between the ball pads can be enlarged by the opening, so as to balance the impedance match.
摘要翻译：提供了一种半导体封装基板，其包括其中形成有多个导电通孔的基板主体，其中至少两个相邻的导电通孔形成为差分对，每个导体通孔在其一端形成有球垫; 以及形成在所述基板主体中的至少一个电气集成层，并且具有与形成为所述差动对的两个相邻的导电通孔对应的开口及其球垫。因此，可以通过开口来扩大导电通孔和电气集成层之间的间隔以及球垫之间的间隔，从而平衡阻抗匹配。

47. 发明申请

US20100126010A1 Radio Frequency Interconnect Circuits and Techniques 有权
标题翻译：射频互连电路和技术
公开(公告)号：US20100126010A1
公开(公告)日：2010-05-27
申请号：US12694450
申请日：2010-01-27
申请人： Angelo M. Puzella , Joseph M. Crowder , Patricia S. Dupuis , Michael C. Fallica , John B. Francis , Joseph A. Licciardello
发明人： Angelo M. Puzella , Joseph M. Crowder , Patricia S. Dupuis , Michael C. Fallica , John B. Francis , Joseph A. Licciardello
IPC分类号： H05K3/10 , H03H7/38
CPC分类号： H01Q21/0087 , H03H7/38 , H05K1/0251 , H05K1/116 , H05K3/429 , H05K3/4623 , H05K2201/09145 , H05K2201/09454 , H05K2201/09536 , H05K2201/09718 , H05K2201/09727 , H05K2201/209 , H05K2203/061 , Y10T29/49165
摘要： A multilayer circuit board assembly includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the circuit board assembly. The RF interconnects can include one or more RF matching pads which provide a mechanism for matching impedance characteristics of RF stubs to provide the RF interconnects having desired insertion loss and impedance characteristics over a desired RF operating frequency band. The RF matching pads allow the manufacture of circuit boards having RF interconnects without the need to perform any back drill and back fill operation to remove stub portions of the RF interconnects in the multilayer circuit board assembly.
摘要翻译：多层电路板组件包括构成电路板组件的不同电路板上的不同电路层之间的一个或多个射频（RF）互连。 RF互连可以包括一个或多个RF匹配焊盘，其提供用于匹配RF短截线的阻抗特性的机制，以在期望的RF工作频带上提供具有期望的插入损耗和阻抗特性的RF互连。 RF匹配焊盘允许制造具有RF互连的电路板，而不需要执行任何后钻和反向填充操作以去除多层电路板组件中的RF互连的短截线部分。

48. 发明申请

US20100108369A1 Printed Circuit Boards, Printed Circuit Board Capacitors, Electronic Filters, Capacitor Forming Methods, and Articles of Manufacture 审中-公开
标题翻译：印刷电路板，印刷电路板电容器，电子滤波器，电容器形成方法和制造
公开(公告)号：US20100108369A1
公开(公告)日：2010-05-06
申请号：US12262979
申请日：2008-10-31
申请人： Alexander Tom
发明人： Alexander Tom
IPC分类号： H05K1/11 , H05K1/16 , H01R43/00 , G06F17/50
CPC分类号： H05K1/162 , H03H7/0115 , H05K1/0251 , H05K1/116 , H05K3/429 , H05K2201/09454 , H05K2201/09627 , H05K2201/09672 , H05K2201/097 , H05K2201/09718 , H05K2201/09727 , Y10T29/4921
摘要： Printed circuit board capacitors include a first electrode comprising a via extending at least partially through a multi-layer printed circuit board and a plurality of conductive pads in electrical contact with the via and extending radially outward from the via, and a second electrode electrically isolated from the first electrode and comprising a plurality of ground-plane layers of the printed circuit board. The plurality of ground-plane layers include electrically conductive material overlapping the plurality of conductive pads.
摘要翻译：印刷电路板电容器包括第一电极，其包括至少部分延伸穿过多层印刷电路板的通孔和与通孔电接触并从通孔径向向外延伸的多个导电焊盘，以及与通孔电绝缘的第二电极所述第一电极并且包括所述印刷电路板的多个接地层。多个接地层包括与多个导电焊盘重叠的导电材料。

49. 发明申请

US20100065321A1 PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：印刷线路板及其制造方法
公开(公告)号：US20100065321A1
公开(公告)日：2010-03-18
申请号：US12557371
申请日：2009-09-10
申请人： KAZUHIRO KASHIWAKURA
发明人： KAZUHIRO KASHIWAKURA
IPC分类号： H05K1/11 , H05K3/10
CPC分类号： H05K1/116 , H05K1/0222 , H05K1/0251 , H05K3/429 , H05K2201/09618 , H05K2201/09718 , Y10T29/49124 , Y10T29/49155
摘要： A printed wiring board comprises ground layers stacked via insulator(s); a first through hole; second through holes formed at predetermined positions along a circle concentric with a center axis of the first through hole; clearances provided between the first through hole and each of the ground layers; and signal wirings each extending from the first through hole through the clearance between predetermined ones of the ground layers, disposed between predetermined second through holes of the second through holes. Each of first clearances in the ground layers neighboring layer in which the signal wiring is disposed has an outline that a distance between the first through hole and outline of the first clearance is minimum of the signal wiring. Each of second clearances in the ground layers not adjacent to the signal wiring has an outline formed outside a circle connecting each center of second through holes centering the first signal through hole, such that outline of second clearance docs not contact with the second through holes. The second through holes arc not connected to the ground layers that are not adjacent to the signal wiring but are connected to the ground layer neighboring layer in which the signal wiring is disposed.
摘要翻译：印刷电路板包括通过绝缘体堆叠的接地层; 第一个通孔; 沿着与所述第一通孔的中心轴同心的圆的预定位置形成的第二通孔; 间隙设置在第一通孔和每个接地层之间; 以及信号布线，其各自从第一通孔延伸穿过位于第二通孔的预定第二通孔之间的预定接地层之间的间隙。其中布置信号布线的地层相邻层中的每个第一间隙具有第一通孔之间的距离和第一间隙的轮廓线是信号布线最小的轮廓。与信号线不相邻的接地层中的每个第二间隙具有形成在围绕第一信号通孔的第二通孔的每个中心的圆周外的轮廓，使得第二间隙的轮廓不与第二通孔接触。第二通孔不连接到不与信号线相邻的接地层，而是连接到布置信号布线的接地层相邻层。

50. 发明授权

US07671696B1 Radio frequency interconnect circuits and techniques 有权
标题翻译：射频互连电路和技术
公开(公告)号：US07671696B1
公开(公告)日：2010-03-02
申请号：US11558126
申请日：2006-11-09
申请人： Angelo M. Puzella , Joseph M. Crowder , Patricia S. Dupuis , Michael C. Fallica , John B. Francis , Joseph A. Licciardello
发明人： Angelo M. Puzella , Joseph M. Crowder , Patricia S. Dupuis , Michael C. Fallica , John B. Francis , Joseph A. Licciardello
IPC分类号： H03H7/38
CPC分类号： H01Q21/0087 , H03H7/38 , H05K1/0251 , H05K1/116 , H05K3/429 , H05K3/4623 , H05K2201/09145 , H05K2201/09454 , H05K2201/09536 , H05K2201/09718 , H05K2201/09727 , H05K2201/209 , H05K2203/061 , Y10T29/49165
摘要： A multilayer circuit board assembly includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the circuit board assembly. The RF interconnects can include one or more RF matching pads which provide a mechanism for matching impedance characteristics of RF stubs to provide the RF interconnects having desired insertion loss and impedance characteristics over a desired RF operating frequency band. The RF matching pads allow the manufacture of circuit boards having RF interconnects without the need to perform any back drill and back fill operation to remove stub portions of the RF interconnects in the multilayer circuit board assembly.
摘要翻译：多层电路板组件包括构成电路板组件的不同电路板上的不同电路层之间的一个或多个射频（RF）互连。 RF互连可以包括一个或多个RF匹配焊盘，其提供用于匹配RF短截线的阻抗特性的机制，以在期望的RF工作频带上提供具有期望的插入损耗和阻抗特性的RF互连。 RF匹配焊盘允许制造具有RF互连的电路板，而不需要执行任何后钻和反向填充操作以去除多层电路板组件中的RF互连的短截线部分。

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