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41. 发明授权

US07706261B2 Queue-based active queue management process 有权
标题翻译：基于队列的活动队列管理过程
公开(公告)号：US07706261B2
公开(公告)日：2010-04-27
申请号：US10928765
申请日：2004-08-27
申请人： Jinshen Sun , King-Tim Ko , Guanrong Chen , Sammy Chan , Moshe Zukerman
发明人： Jinshen Sun , King-Tim Ko , Guanrong Chen , Sammy Chan , Moshe Zukerman
IPC分类号： G08C15/00 , H04L12/28
CPC分类号： H04L47/10 , H04L47/263 , H04L47/30 , H04L47/32 , H04L49/3018 , H04L49/3027
摘要： An active queue management (AQM) process for network communications equipment. The AQM process is queue based and involves applying at a queue size threshold congestion notification to communications packets in a queue of a link via packet dropping; and adjusting said queue size threshold on the basis of the congestion level. The AQM process releases more buffer capacity to accommodate more incoming packets by increasing said queue size threshold when congestion increases; and decreases buffer capacity by reducing said queue size threshold when congestion decreases. Network communications equipment includes a switch component for switching communications packets between input ports and output ports, packet queues for at least the output ports, and an active queue manager for applying congestion notification to communications packets in the queues for the output ports via packet dropping. The congestion notification is applied at respective queue size thresholds for the queues, and the thresholds adjusted on the basis of the respective congestion levels of the queues of the output ports.
摘要翻译：网络通信设备的主动队列管理（AQM）流程。 AQM过程是基于队列的，并且涉及通过分组丢弃将队列大小阈值拥塞通知应用于链路队列中的通信分组; 以及基于所述拥塞级别来调整所述队列大小阈值。 AQM进程通过在拥塞增加时增加队列大小阈值来释放更多的缓冲区容量来容纳更多的传入数据包; 并且当拥塞减小时通过减小所述队列大小阈值来减小缓冲器容量。网络通信设备包括用于在输入端口和输出端口之间切换通信分组的交换组件，用于至少输出端口的分组队列，以及主动队列管理器，用于通过分组丢弃向拥塞通知队列中的通信分组提供拥塞通知。针对队列以相应的队列大小阈值应用拥塞通知，并且基于输出端口的队列的相应拥塞级别调整阈值。

42. 发明授权

US07693149B2 Programmable packet processor with flow resolution logic 有权
标题翻译：具有流分辨率逻辑的可编程数据包处理器
公开(公告)号：US07693149B2
公开(公告)日：2010-04-06
申请号：US11428616
申请日：2006-07-05
申请人： Jim Cathey , Timothy S. Michels
发明人： Jim Cathey , Timothy S. Michels
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/254 , H04L41/5003 , H04L41/5045 , H04L41/5054 , H04L41/5096 , H04L45/00 , H04L45/44 , H04L45/50 , H04L45/54 , H04L47/10 , H04L47/20 , H04L47/215 , H04L47/2408 , H04L47/2441 , H04L47/2458 , H04L47/31 , H04L47/32 , H04L49/103 , H04L49/205 , H04L49/3018 , H04L49/3027 , H04L49/351 , H04L49/354 , H04L49/503 , H04L49/602 , H04L49/90 , H04L49/9042 , H04L69/22
摘要： A programmable packet switching controller has a packet buffer, a pattern match module, a programmable packet classification engine and an application engine. The packet buffer stores inbound packets, and includes a header data extractor to extract header data from the inbound packets and to store the extracted header data in a header data cache. The header data extractor also generates a header data cache index and provides it to the packet classification engine for it to retrieve the extracted header data. The packet classification engine has a decision tree-based classification logic for classifying a packet. Each of the leaves of the tree represents a packet classification. The packet classification engine uses the header data cache index to retrieve the header data to perform multiple header checks, starting at a root of the tree and traversing branches until a leaf has been reached. The application engine has a number of programmable sub-engines arrayed in a pipelined architecture. The packet classification engine provides start indicators based on the packet classification to the programmable sub-engines to identify application programs to be executed. The sub-engines includes a source lookup engine, a destination lookup engine and a disposition engine, which are used to make a disposition decision for the inbound packets in a processing pipeline. The pattern match module is used to compare the packet to a pre-defined pattern in order to provide a disposition recommendation.
摘要翻译：可编程分组交换控制器具有分组缓冲器，模式匹配模块，可编程分组分类引擎和应用引擎。分组缓冲器存储入站分组，并且包括报头数据提取器，用于从入站分组中提取报头数据，并将提取的报头数据存储在报头数据高速缓存中。报头数据提取器还产生报头数据高速缓存索引，并将其提供给分组分类引擎，以便它检索提取的报头数据。分组分类引擎具有用于对分组进行分类的基于决策树的分类逻辑。树的每个叶表示分组分类。分组分类引擎使用报头数据高速缓存索引来检索报头数据以执行多个报头检查，从树的根开始并遍历分支直到叶已经到达。应用引擎具有排列在流水线架构中的多个可编程子引擎。分组分类引擎基于分组分类向可编程子引擎提供启动指示符，以识别要执行的应用程序。子引擎包括源查找引擎，目的地查找引擎和配置引擎，其用于对处理流水线中的入站分组进行配置决定。模式匹配模块用于将数据包与预定义模式进行比较，以提供处置建议。

43. 发明授权

US07684330B2 Flow based congestion control 有权
标题翻译：基于流量的拥塞控制
公开(公告)号：US07684330B2
公开(公告)日：2010-03-23
申请号：US11727614
申请日：2007-03-27
申请人： Shiri Kadambi , Shekhar Ambe , Mohan Kalkunte , Sandeep Relan
发明人： Shiri Kadambi , Shekhar Ambe , Mohan Kalkunte , Sandeep Relan
IPC分类号： H04L12/26 , H04L12/28
CPC分类号： H04L47/2433 , H04L12/4641 , H04L29/06 , H04L45/66 , H04L47/10 , H04L47/11 , H04L47/16 , H04L47/18 , H04L47/24 , H04L47/2441 , H04L47/266 , H04L47/29 , H04L47/30 , H04L47/33 , H04L47/50 , H04L47/6205 , H04L47/6215 , H04L47/6225 , H04L49/205 , H04L49/3018 , H04L49/351 , H04L49/50 , H04L49/508 , H04L49/90 , Y02D50/10
摘要： A method for selectively controlling the flow of data through a network device is discussed. The network device has a plurality of ports, with each port of the plurality of ports having a plurality of priority queues. Congestion at one priority queue of the plurality of priority queues is detected and a virtual channel message is sent to other network devices connected to the network device causing data destined for the one priority queue to be halted. After the congestion at the one priority queue has abated, a virtual channel resume message is sent to the other network devices.
摘要翻译：讨论了通过网络设备选择性地控制数据流的方法。网络设备具有多个端口，多个端口的每个端口具有多个优先级队列。检测到多个优先级队列的一个优先级队列的拥塞，并将虚拟频道消息发送到连接到网络设备的其他网络设备，从而导致去往一个优先级队列的数据被停止。在一个优先级队列的拥塞已经减轻之后，虚拟通道恢复消息被发送到其他网络设备。

44. 发明授权

US07627701B2 Indicating last data buffer by last bit flag bit 有权
标题翻译：用最后一位标志位指示最后一个数据缓冲区
公开(公告)号：US07627701B2
公开(公告)日：2009-12-01
申请号：US12120419
申请日：2008-05-14
申请人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
IPC分类号： G06F5/00 , G06F15/16
CPC分类号： H04L49/901 , H04L49/103 , H04L49/3018 , H04L49/90 , H04L49/9094
摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.
摘要翻译：提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器的特定框架。

45. 发明授权

US07586909B1 Striping algorithm for switching fabric 有权
标题翻译：交换结构的划线算法
公开(公告)号：US07586909B1
公开(公告)日：2009-09-08
申请号：US10269928
申请日：2002-10-11
申请人： Jean Walrand , John T. Musacchio , Roy T. Myers , Chung Kuang Chin
发明人： Jean Walrand , John T. Musacchio , Roy T. Myers , Chung Kuang Chin
IPC分类号： H04Q11/00
CPC分类号： H04Q3/68 , H04L49/1515 , H04L49/201 , H04L49/205 , H04L49/25 , H04L49/254 , H04L49/3018 , H04L49/3027 , H04L49/3072
摘要： A striping algorithm selects a route on which to transmit each next data segment, in dependence upon relative channel loading so far, taking account of multicast. Input modules can keep a channel loading history for each route it has, and can update its history for each route that a data segment follows through the fabric. In an embodiment, the input module transmits each data segment toward an i'th intermediate stage module, where i minimizes q(i,a(G),c)+q(i,b(G),c)+ . . . +q(i,k(G),c), where q(i, j, c) indicates the number of bytes of data sent, during a given prior time period, from the input module to each j'th one of the output modules via each i'th one of the intermediate stage modules, and a(G), b(G), . . . , and k(G) are the output module(s) in the multicast group G to which the data segment is destined.
摘要翻译：条带化算法根据到目前为止的相对信道负载，考虑到多播，选择在其上发送每个下一个数据段的路由。输入模块可以为其拥有的每个路由保留一个通道加载历史记录，并且可以通过该结构更新数据段跟随的每个路由的历史记录。在一个实施例中，输入模块向第i个中间级模块传输每个数据段，其中i使<？in-line-formula description =“In-line Formulas”end =“lead”？> q（i，a （G），c）+ q（i，b（G），c）+。。。 + q（i，k（G），c），<？in-line-formula description =“In-line Formulas”end =“tail”？>其中q（i，j，c）表示在给定的先前时间段期间，经由每个第i个中间级模块以及（G），b（G），从输入模块向每个第j个输出模块发送数据。。。，并且k（G）是数据段到达的组播组G中的输出模块。

46. 发明申请

US20090185575A1 PACKET SWITCH APPARATUS AND METHOD 审中-公开
标题翻译：分组开关装置和方法
公开(公告)号：US20090185575A1
公开(公告)日：2009-07-23
申请号：US12274690
申请日：2008-11-20
申请人： Waki Iwata , Katsuya Tsushita
发明人： Waki Iwata , Katsuya Tsushita
IPC分类号： H04L12/56
CPC分类号： H04L49/25 , H04L49/3009 , H04L49/3018 , H04L49/3027 , H04L49/90 , H04L49/901
摘要： A packet switch apparatus for switching a packet between a plurality of input ports and a plurality of output ports includes a plurality of input buffers for storing a packet inputted to the input port, a plurality of output buffers for storing a packet outputted to the output port, and a path controller for transmitting the packet stored in the input buffer to the output buffer on the basis of path information of the packet stored in the input buffer by a higher transfer rate than an input rate for receiving the packet at the input port.
摘要翻译：一种用于在多个输入端口和多个输出端口之间切换分组的分组交换设备包括：多个输入缓冲器，用于存储输入到输入端口的分组;多个输出缓冲器，用于存储输出到输出端口的分组以及路径控制器，用于基于存储在输入缓冲器中的分组的路径信息，将存储在输入缓冲器中的分组传送到输出缓冲器，传输速率高于用于在输入端口接收分组的输入速率。

47. 发明授权

US07525995B2 Method and system for switching packets 有权
标题翻译：切换数据包的方法和系统
公开(公告)号：US07525995B2
公开(公告)日：2009-04-28
申请号：US11099582
申请日：2005-04-06
申请人： Ofer Iny
发明人： Ofer Iny
IPC分类号： H04J3/24
CPC分类号： H04L49/254 , H04L49/15 , H04L49/1523 , H04L49/3018 , H04L49/3027
摘要： A system for switching variable size packets in a network is disclosed. The system comprises at least one ingress controller which receives a plurality of packets and which segments each of the packets into fixed sized fragments. The at least one ingress controller has a time-clock. The time clocks of all ingress controllers are synchronized to within a tolerance. Each fragment is tagged with at least a unique source of ID, time-stamp, and a fragment-number to form a cell. Each cell belongs to one packet having the same time-stamp value. The ingress controller sends each of the cells through a link such that a cell's destination is reachable through that link. The system includes a fabric element which receives cells from a plurality of inputs links. The cells are ordered. The fabric element sends ordered cells through a plurality of outputs and through which the destination of the cells is reachable. The cell order is defined such that a cell ahead of another either has a lagging time stamp, or if the timestamp is the same the cell ahead of another has a source-id which has a predetermined priority, or if both the timestamp and the source-id are the same the cell ahead of another has a lagging fragment-number. The system finally includes at least one egress controller which receives the ordered cells from the plurality of input links, and sends the ordered cells through an output where such order results in complete packets. A packet switching device in accordance with the present invention solves the cell ordering and packet reassembly issues using a unified distributed method in a multi-stage interconnect network.
摘要翻译：公开了一种用于在网络中切换可变大小分组的系统。该系统包括至少一个入口控制器，其接收多个分组，并且将每个分组划分成固定大小的分段。所述至少一个入口控制器具有时钟。所有入口控制器的时钟同步到公差范围内。每个片段至少标识一个唯一的ID源，时间戳和片段号以形成一个单元格。每个小区属于具有相同时间戳值的一个分组。入口控制器通过链路发送每个小区，使得小区的目的地可通过该链路到达。该系统包括从多个输入链接接收单元的结构元件。细胞是有序的。织物元件通过多个输出发送有序单元，并且单元的目的地可通过该单元到达。单元顺序被定义为使得另一个之前的单元格具有滞后时间戳，或者如果时间戳相同，则另一个之前的单元具有具有预定优先级的源代码，或者如果时间戳和源 -id是相同的，在另一个之前的单元格具有滞后的片段号。系统最终包括至少一个出口控制器，其从多个输入链路接收有序单元，并且通过输出发送排序单元，其中这样的订单导致完整的分组。根据本发明的分组交换设备使用多级互连网络中的统一分布式方法来解决小区排序和分组重组问题。

48. 发明授权

US07519066B1 Method for switching data in a crossbar switch 有权
标题翻译：用于在交叉开关中切换数据的方法
公开(公告)号：US07519066B1
公开(公告)日：2009-04-14
申请号：US10434785
申请日：2003-05-08
申请人： Sung Soo Park
发明人： Sung Soo Park
IPC分类号： H04L12/28
CPC分类号： H04L49/3009 , H04L49/101 , H04L49/254 , H04L49/3018 , H04L49/3027
摘要： A method and system for switching data in a data switch. In one embodiment, the present invention comprises receiving a plurality of cells at a merged input queue of the data switch, wherein a cell of the plurality of cells is characterized by a priority and a destination. In one embodiment, the destination identifies an output port of the data switch. An age tag is assigned to at least one cell of the plurality of cells. In one embodiment, the age tag indicates the relative length of time a cell of has been in the merged input queue as compared to other cells of the plurality of cells. A portion of the plurality of cells is selected according to a priority selection. It is determined whether any cells of the portion have the same destination. At least one connection request associated with cells of the portion is transmitted, wherein cells having the same destination are transmitted according to the age tag.
摘要翻译：一种在数据交换机中切换数据的方法和系统。在一个实施例中，本发明包括在数据交换机的合并输入队列处接收多个小区，其中多个小区的小区的特征在于优先级和目的地。在一个实施例中，目的地识别数据交换机的输出端口。年龄标签被分配给多个单元中的至少一个单元。在一个实施例中，age标签指示与多个单元中的其他单元相比，单元格已经在合并输入队列中的相对时间长度。根据优先级选择来选择多个单元的一部分。确定该部分的任何单元格是否具有相同的目的地。发送与该部分的小区相关联的至少一个连接请求，其中根据年龄标签发送具有相同目的地的小区。

49. 发明申请

US20090074001A1 Switch assembly having multiple blades in a chassis 有权
公开(公告)号：US20090074001A1
公开(公告)日：2009-03-19
申请号：US12292207
申请日：2008-11-13
申请人： Mohan Kalkunte , Shekhar Ambe
发明人： Mohan Kalkunte , Shekhar Ambe
IPC分类号： H04L12/56
CPC分类号： H04L43/00 , H04L43/12 , H04L49/3018 , H04L49/351 , H04L49/354
摘要： A switch assembly having multiple blades in a chassis and a method of using that assembly to switch data is disclosed. A network switch assembly for network communications includes at least one fabric blade and a plurality of port blades. The at least one fabric blade has at least one switch having a plurality of data port interfaces, supporting a plurality of fabric data ports transmitting and receiving data, and a CPU interface, where CPU interface is configured to communicate with a CPU. The at least one fabric blade also has a CPU subsystem communicating with the CPU interface. Each of said plurality of port blades has at least one switch having a plurality of data port interfaces, supporting a plurality of port data ports transmitting and receiving data. The plurality of port data ports communicate with the plurality of fabric data ports along multiple paths such that data received by the port data ports is switched to a destination port of the network switch assembly along a specified path of the multiple paths based on a portion of the received data. In particular, the invention relates to configurations having five and nine blades to provide the requisite switching capacity.

50. 发明授权

US07499456B2 Multi-tiered virtual local area network (VLAN) domain mapping mechanism 有权
标题翻译：多层虚拟局域网（VLAN）域映射机制
公开(公告)号：US07499456B2
公开(公告)日：2009-03-03
申请号：US11651145
申请日：2007-01-09
申请人： Suran S. De Silva , Norman W. Finn
发明人： Suran S. De Silva , Norman W. Finn
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L47/2491 , H04L12/4641 , H04L49/205 , H04L49/3018 , H04L49/351 , H04L49/354 , H04L2012/5665
摘要： In one embodiment, a first port of a device provides connectivity to a customer network and a second port of the device provides connectivity to a provider network. Frame mapping logic associated with the first port processes a network message received at the first port and accesses a Virtual Local Area Network (VLAN) mapping data structure that maps customer VLAN designations used in the customer network to provider VLAN designations used in the provider network. Frame mapping logic uses the VLAN mapping data structure to associate the received network message with a particular provider VLAN designation based upon the received network message's particular customer VLAN designation. The received network message is then passed toward the second port.
摘要翻译：在一个实施例中，设备的第一端口提供到客户网络的连接，并且设备的第二端口提供到提供商网络的连接。与第一端口相关联的帧映射逻辑处理在第一端口处接收的网络消息，并访问将客户网络中使用的客户VLAN名称映射到提供商网络中使用的提供商VLAN名称的虚拟局域网（VLAN）映射数据结构。帧映射逻辑使用VLAN映射数据结构，根据接收到的网络消息的特定客户VLAN名称将接收到的网络消息与特定提供商VLAN指定相关联。然后将接收的网络消息传递给第二个端口。

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