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41. 发明授权

US07479840B2 Digital pulse width controlled oscillation modulator 有权
标题翻译：数字脉宽调制振荡器
公开(公告)号：US07479840B2
公开(公告)日：2009-01-20
申请号：US10548432
申请日：2004-03-23
申请人： Ole Neis Nielsen
发明人： Ole Neis Nielsen
IPC分类号： H03K7/08
CPC分类号： H03M5/08 , H03M3/506 , H03M7/3004 , H03M7/3028 , H03M7/304
摘要： A pulse width modulator (10) for converting a digital signal into a PWM signal, comprising a plurality of integrators (11) with integrator gains (12) arranged in series, a comparator (17) for comparing the output of the last integrator (11′) with a reference, and thereby creating the PWM signal. The modulator further has means (13) for realizing self-oscillation at a desired switching frequency, and a feedback path (14) connected to a point down stream said comparator and leading to a plurality of summing points, each preceding one of said integrators, wherein the PWM signal is quantized in time by the clock frequency of the modulator, and wherein the integrator gains (12) are adapted to reduce any quantization noise.
摘要翻译：一种用于将数字信号转换为PWM信号的脉冲宽度调制器（10），包括具有串联布置的积分器增益（12）的多个积分器（11），比较器（17），用于比较最后一个积分器 '），从而产生PWM信号。调制器还具有用于以期望的开关频率实现自振荡的装置（13）和连接到下游流的所述比较器并且导致多个求和点的反馈路径（14），每个求和点各自在所述积分器之一之前，其中所述PWM信号在调制器的时钟频率上被量化，并且其中所述积分器增益（12）适于减少任何量化噪声。

42. 发明授权

US07197522B2 Bi-quad digital filter configured with a bit binary rate multiplier 失效
标题翻译：双二进制数字滤波器配置了一个二进制比特倍增器
公开(公告)号：US07197522B2
公开(公告)日：2007-03-27
申请号：US10453901
申请日：2003-06-02
申请人： Andrew Martin Mallinson
发明人： Andrew Martin Mallinson
IPC分类号： G06F7/68
CPC分类号： H03M7/3004 , H03H17/0248 , H03M7/3028 , H03M7/3042
摘要： The invention is directed to a bi-quad filter circuit configured with sigma-delta devices that operate as binary rate multipliers (BRMs). Unlike conventional bi-quad filter circuits, the invention provides a bi-quad filter configured with a single-bit BRM. In another embodiment, the invention further provides a bi-quad filter configured with multiple-bit BRMs.
摘要翻译：本发明涉及一种双向滤波器电路，其配置为以二进制比率乘法器（BRM）操作的Σ-Δ器件。与传统的双通道滤波器电路不同，本发明提供一种配置有单位BRM的双通道滤波器。在另一个实施例中，本发明还提供一种配置有多位BRM的双二进制滤波器。

43. 发明申请

US20060232351A1 Digital pulse width controlled oscillation modulator 有权
标题翻译：数字脉宽调制振荡器
公开(公告)号：US20060232351A1
公开(公告)日：2006-10-19
申请号：US10548432
申请日：2004-03-23
申请人： Ole Nielsen
发明人： Ole Nielsen
IPC分类号： H03K7/08
CPC分类号： H03M5/08 , H03M3/506 , H03M7/3004 , H03M7/3028 , H03M7/304
摘要： A pulse width modulator (10) for converting a digital signal into a PWM signal, comprising a plurality of integrators (11) with integrator gains (12) arranged in series, a comparator (17) for comparing the output of the last integrator (11′) with a reference, and thereby creating the PWM signal. The modulator further has means (13) for realizing self-oscillation at a desired switching frequency, and a feedback path (14) connected to a point down stream said comparator and leading to a plurality of summing points, each preceding one of said integrators, wherein the PWM signal is quantized in time by the clock frequency of the modulator, and wherein the integrator gains (12) are adapted to reduce any quantization noise.
摘要翻译：一种用于将数字信号转换为PWM信号的脉冲宽度调制器（10），包括具有串联布置的积分器增益（12）的多个积分器（11），比较器（17），用于比较最后一个积分器 '），从而产生PWM信号。调制器还具有用于以期望的开关频率实现自振荡的装置（13）和连接到下游流的所述比较器并且导致多个求和点的反馈路径（14），每个求和点各自在所述积分器之一之前，其中所述PWM信号在调制器的时钟频率上被量化，并且其中所述积分器增益（12）适于减少任何量化噪声。

44. 发明公开

US20240223205A1 AREA-EFFICIENT AND MODERATE CONVERSION TIME ANALOG TO DIGITAL CONVERTER (ADC) 审中-公开
公开(公告)号：US20240223205A1
公开(公告)日：2024-07-04
申请号：US18354370
申请日：2023-07-18
申请人： SanDisk Technologies LLC
发明人： V.M. SHIVASUBRAMANIYARAJAN , ASWANI KRISHNA ADDAGALLA , PRADEEP ANANTULA
IPC分类号： H03M1/20 , H03M1/18 , H03M7/32
CPC分类号： H03M1/203 , H03M1/182 , H03M7/3004
摘要： Systems and methods for converting an input analog signal to a digital representation thereof. A method includes determining an input analog signal voltage range of the input analog signal, and splitting the input analog signal voltage range into n+1 sub-ranges, n being a number of splits in the input analog signal voltage range. The method also includes assigning a respective N-bit coarse digital code i to each sub-range. The method also includes identifying the input analog signal with a corresponding sub-range, the corresponding sub-range having respective digital code i. A delta-sigma operation is performed on the input analog signal using upper and lower reference voltages of the corresponding sub-range that the input analog signal is identified with, to produce the digital representation.

45. 发明申请

US20180302097A1 Fractional-N frequency synthesizer and method thereof 审中-公开
公开(公告)号：US20180302097A1
公开(公告)日：2018-10-18
申请号：US15590776
申请日：2017-05-09
申请人： Beken Corporation
发明人： Dawei GUO , Caogang YU
IPC分类号： H03L7/197 , H03L7/087 , H03L7/089
CPC分类号： H03L7/1976 , H03C3/0925 , H03C3/0933 , H03K23/68 , H03L7/06 , H03L7/085 , H03L7/087 , H03L7/0891 , H03L7/18 , H03M7/3004
摘要： A fractional-N frequency synthesizer comprising a multi-phase generator, a multi-path error phase generator; a current combiner; a loop filter connected to the current combiner; an oscillator (150) connected to the loop filter; a frequency divider (160); a SDM connected to both the frequency divider and the multi-phase generator, to generate variable division ratio.

46. 发明授权

US09853657B2 Delta sigma modulator with dynamic error cancellation 有权
公开(公告)号：US09853657B2
公开(公告)日：2017-12-26
申请号：US15489124
申请日：2017-04-17
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Eeshan Miglani , Karthikeyan Gunasekaran , Santhosh Kumar Gowdhaman , Shagun Dusad
IPC分类号： H03M3/00 , H03M1/06 , H03M1/00 , H03M1/74 , H03M7/30 , H03M1/12
CPC分类号： H03M3/50 , H03M1/00 , H03M1/001 , H03M1/0626 , H03M1/0665 , H03M1/12 , H03M1/747 , H03M3/30 , H03M3/34 , H03M3/422 , H03M3/458 , H03M7/3004
摘要： The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.

47. 发明授权

US09762250B2 Cancellation of spurious tones within a phase-locked loop with a time-to-digital converter 有权
公开(公告)号：US09762250B2
公开(公告)日：2017-09-12
申请号：US14448458
申请日：2014-07-31
申请人： Silicon Laboratories Inc.
发明人： Michael H. Perrott
IPC分类号： H03L7/06 , H03L7/08 , H03L7/093 , H03M1/08 , H03M1/66 , G04F10/00 , H03L7/099 , H03M3/00 , H03L7/085 , H02M3/07 , H03M7/30
CPC分类号： H03L7/0802 , G04F10/005 , H02M3/07 , H03L7/085 , H03L7/093 , H03L7/0995 , H03M1/0836 , H03M1/0854 , H03M1/66 , H03M3/358 , H03M3/368 , H03M7/3004
摘要： A phase-locked loop (PLL) includes a spur cancellation circuit that receives a residue signal indicative of a first frequency and receives a residual phase error signal and generates a spur cancellation signal. A summing circuit combines the spur cancellation signal and a first phase error signal corresponding to a phase difference between a reference signal and a feedback signal in the PLL and generates a second phase error signal with a reduced spurious tone at the first frequency.

48. 发明授权

US09742427B2 Electrical circuit 有权
公开(公告)号：US09742427B2
公开(公告)日：2017-08-22
申请号：US15151236
申请日：2016-05-10
申请人： Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
发明人： Michael Hackner , Hans-Peter Hohe , Markus Sand
IPC分类号： H03M3/02 , H03M3/00 , H03M1/12 , H03M1/82 , H03M7/30 , H03L7/08 , H03M1/50
CPC分类号： H03M3/39 , H03L7/08 , H03M1/1255 , H03M1/50 , H03M1/82 , H03M3/462 , H03M3/496 , H03M3/50 , H03M7/3004
摘要： An electrical circuit includes a signal processing chain and a controller. The signal processing chain includes an integrator configured to integrate an input signal over an integration time. The controller is connected to a signal output of the signal processing chain to receive and evaluate an output signal of the signal processing chain. The controller is further configured to adapt the integration time based on the output signal.

49. 发明授权

US09740175B2 All-digital phase locked loop (ADPLL) including a digital-to-time converter (DTC) and a sampling time-to-digital converter (TDC) 有权
公开(公告)号：US09740175B2
公开(公告)日：2017-08-22
申请号：US15370796
申请日：2016-12-06
申请人： Marvell World Trade Ltd.
发明人： Olivier Burg , Haisong Wang , Xiang Gao
IPC分类号： H03M1/50 , G04F10/00 , H03M1/00 , H04M1/50 , H03M1/12 , H03B21/02 , H03L7/089
CPC分类号： G04F10/005 , H03B21/02 , H03L7/0891 , H03L7/091 , H03L7/0991 , H03L7/18 , H03M1/00 , H03M1/12 , H03M1/50 , H03M7/3004 , H03M2201/4233 , H04M1/505
摘要： A digital phase locked loop (DPLL) circuit includes a digital-to-time converter (DTC) configured to generate a delayed reference clock signal by delaying a reference clock signal according to a delay control signal and a time-to-digital converter (TDC) coupled to an output of the DTC. The TDC is configured to sample a value of a transition signal according to the delayed reference clock signal and to generate an output signal indicating a phase difference between the delayed clock signal and an input clock signal. A method of controlling a DPLL includes delaying a reference clock signal according to a delay control signal, sampling a value of a transition signal according to the delayed reference clock signal, generating an output signal indicating a phase difference between the delayed clock signal and an input clock signal, and generating a digitally controlled oscillator (DCO) clock signal according to the output signal.

50. 发明授权

US09490818B2 Cancellation of delta-sigma quantization noise within a fractional-N PLL with a nonlinear time-to-digital converter 有权
$Cancellation of delta-sigma quantization noise within a fractional-N PLL with a nonlinear time-to-digital converter$
标题翻译：用非线性时间 - 数字转换器消除小数N PLL内的Δ-sigma量化噪声
公开(公告)号：US09490818B2
公开(公告)日：2016-11-08
申请号：US14448447
申请日：2014-07-31
申请人： Silicon Laboratories Inc.
发明人： Michael H. Perrott
IPC分类号： H03L7/06 , H03L7/08 , H03L7/093 , H03M1/08 , H03M1/66 , G04F10/00 , H03L7/099 , H03M3/00 , H03L7/085 , H02M3/07 , H03M7/30
CPC分类号： H03L7/0802 , G04F10/005 , H02M3/07 , H03L7/085 , H03L7/093 , H03L7/0995 , H03M1/0836 , H03M1/0854 , H03M1/66 , H03M3/358 , H03M3/368 , H03M7/3004
摘要： A fractional-N phase-locked loop (PLL) includes a nonlinear time to digital converter that generates a digital representation of a phase error corresponding to a time difference between a feedback signal of the fractional-N PLL and a reference signal. A nonlinear quantization noise cancellation circuit supplies a correction signal to ensure that the generated digital representation has reduced quantization noise. The correctional signal may be applied in the analog or digital domain.
摘要翻译：分数N锁相环（PLL）包括非线性时间到数字转换器，其产生对应于分数N PLL的反馈信号与参考信号之间的时间差的相位误差的数字表示。非线性量化噪声消除电路提供校正信号以确保生成的数字表示具有降低的量化噪声。校正信号可以应用于模拟或数字域。

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