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41. 发明授权

US07007053B1 Area efficient realization of coefficient architecture for bit-serial FIR, IIR filters and combinational/sequential logic structure with zero latency clock output 有权
标题翻译：区域有效实现位串行FIR，IIR滤波器和具有零延迟时钟输出的组合/顺序逻辑结构的系数架构
公开(公告)号：US07007053B1
公开(公告)日：2006-02-28
申请号：US09807500
申请日：1998-10-13
申请人： Rakesh Malik , Puneet Goel
发明人： Rakesh Malik , Puneet Goel
IPC分类号： G06F17/10
CPC分类号： H03H17/0223 , H03H17/0225 , H03H17/0227 , H03H2218/08 , H03H2218/10
摘要： An area-efficient realization of a coefficient block includes hardware sharing techniques and optimizations applied to this block. The block is connected to coefficient lines coming from a delay block to be connected to perform a filtering operation or a mathematical computing operation with optimization in hardware and provides a zero latency output. The coefficient block also enables an area minimal realization of digital filters based on the coefficient block, when operated in serial bit fashion. The optimization techniques and structure are good for bit-serial digital filters typically a finite impulse response (FIR) filter, including finite impulse response filter (IIR) and for other filters and applications based on combinational logic that includes delay elements, multipliers, and serial adders and/or subtractors.
摘要翻译：系数块的区域有效实现包括应用于该块的硬件共享技术和优化。该块连接到来自要连接的延迟块的系数线，以执行硬件优化的过滤操作或数学计算操作，并提供零延迟输出。当以串行位方式操作时，系数块还使得能够基于系数块的数字滤波器的面积最小化实现。优化技术和结构对于位串行数字滤波器通常是有限脉冲响应（FIR）滤波器，包括有限脉冲响应滤波器（IIR）以及基于组合逻辑的其他滤波器和应用，包括延迟元件，乘法器和串行加法器和/或减法器。

42. 发明申请

US20050094723A1 Adaptive FIR filter and method 有权
标题翻译：自适应FIR滤波器和方法
公开(公告)号：US20050094723A1
公开(公告)日：2005-05-05
申请号：US10954137
申请日：2004-09-28
申请人： Hiroshi Takatori
发明人： Hiroshi Takatori
IPC分类号： G06F20060101 , H03K5/159
CPC分类号： H03H17/0607 , H03H17/0227 , H03H17/06 , H03H21/0012 , H03H21/0067 , H03H2017/0297 , H03H2218/025 , H04L25/03057 , H04L25/03885 , H04L25/4921
摘要： Finite impulse response filters are commonly used in high speed data communications electronics for reducing error rates in multilevel symbol encoding schemes. Schemes such as pulse amplitude modulation and quadrature amplitude modulation may have higher error rates for symbols with low signal to noise ratios. By selectively updating the tap coefficients of the filter based on the symbols received, a more robust, accurate filter can be built.
摘要翻译：有限脉冲响应滤波器通常用于高速数据通信电子设备中，用于降低多电平符号编码方案中的误码率。诸如脉冲幅度调制和正交幅度调制的方案对于具有低信噪比的符号可能具有较高的误码率。通过基于所接收的符号选择性地更新滤波器的抽头系数，可以构建更鲁棒，精确的滤波器。

43. 发明申请

US20010026601A1 Digital filter and refrence signal cancelling device and method using the same 失效
标题翻译：数字滤波器和参考信号消除装置及其使用方法
公开(公告)号：US20010026601A1
公开(公告)日：2001-10-04
申请号：US09822374
申请日：2001-04-02
发明人： Yuji Yamamoto
IPC分类号： H04B001/10
CPC分类号： H03H17/04 , H03H17/0227
摘要： A second-order bandpass IIR type digital filter, assuming that a sampling frequency is six times as large as a central frequency of a passing frequency band, a first-order input feedback coefficient b1 is set at null1null2nulln and a second-order input feedback coefficient b2 is set at 1null2null(nnull1) (n: an odd number of 3 or larger). In this configuration, second-order IIP type digital filter with a simple arrangement and high accuracy can be provided. In a reference signal canceling apparatus, using such a digital filter, the reference signal can be canceled effectively and completely.
摘要翻译：二阶带通IIR型数字滤波器，假设采样频率是通过频带的中心频率的六倍，一阶输入反馈系数b1设置为-1 + 2-n，第二级输入反馈系数b1设置为顺序输入反馈系数b2被设置为1-2-（n-1）（n：奇数3或更大）。在这种配置中，可以提供具有简单布置和高精度的二阶IIP型数字滤波器。在参考信号消除装置中，使用这种数字滤波器，可以有效且完全地取消参考信号。

44. 发明授权

US6101517A Circuit and method for the multiple use of a digital transversal filter 失效
标题翻译：用于多次使用数字横向滤波器的电路和方法
公开(公告)号：US6101517A
公开(公告)日：2000-08-08
申请号：US68431
申请日：1998-05-08
申请人： Stefan Meier
发明人： Stefan Meier
IPC分类号： H03H17/02 , H03H17/06 , G06F17/10
CPC分类号： H03H17/0227 , H03H17/0275 , H03H17/0276 , H03H17/0621 , H03H17/0657 , H03H17/0664 , H03H2218/04 , H03H2218/08
摘要： Circuit and method for the multiple use of a digital transversal filter wherein a coefficient block of n coefficients, there is, in each case, provision of 2 multiplier units which are subject to multiple use if the internal clock of the filter is greater, than an order of magnitude, than an external clock which is required by the filter.
摘要翻译： PCT No.PCT / DE96 / 01883 Sec。 371日期1998年5月8日 102（e）日期1998年5月8日PCT提交1996年10月1日PCT公布。出版物WO97 / 17758 日期1997年5月15日用于多次使用数字横向滤波器的电路和方法，其中n个系数的系数块在每种情况下都存在如果滤波器的内部时钟为多个则需要多次使用的2个乘法器单元比过滤器要求的外部时钟大一个数量级。

45. 发明授权

US3959637A Digital filter 失效
标题翻译：数字滤波器
公开(公告)号：US3959637A
公开(公告)日：1976-05-25
申请号：US558972
申请日：1975-03-17
申请人： Henri J. Nussbaumer
发明人： Henri J. Nussbaumer
IPC分类号： H03H17/00 , G06J1/00 , H03H17/02 , H03H17/06 , H04J3/02 , G06F1/02 , G06F15/34
CPC分类号： H03H17/06 , G06J1/00 , H03H17/0227 , H03H17/0236 , H03H17/0614 , H04J3/025
摘要： A digital filter for a plural digitally expressed pulse code modulated (PCM) signal utilizes a storage register to retain several samples of the signal and obviates the need for digital multiplication circuits by using a delta coding for the filter coefficients. Processing steps are at a multiple of the sampling rate and at each step, the value of one stored sample is combined additively or subtractively with previously stored sample values as determined by stored delta coefficient values. The summed values are periodically transmitted as output samples of a filtered PCM signal.
摘要翻译：用于多个数字表达的脉冲编码调制（PCM）信号的数字滤波器利用存储寄存器来保留信号的几个采样，并且通过对滤波器系数使用增量编码来消除对数字乘法电路的需要。处理步骤是采样率的倍数，并且在每个步骤中，将一个存储的样本的值与由存储的delta系数值确定的先前存储的样本值相加或减去地组合。累加值作为滤波PCM信号的输出样本周期性地发送。

46. 发明授权

US3696235A Digital filter using weighting 失效
标题翻译：数字滤波器使用称重
公开(公告)号：US3696235A
公开(公告)日：1972-10-03
申请号：US3696235D
申请日：1970-06-22
申请人： SANDERS ASSOCIATES INC
发明人： TUFTS DONALD W , BURT RALPH E , DAVIS VICTOR I JR , QUEENAN JAMES F , MALOON RICHARD A , WATERMAN DAVID W
IPC分类号： G01R23/00 , H03H17/02 , G06F7/38
CPC分类号： H03H17/0264 , G01R23/00 , H03H17/0225 , H03H17/0227
摘要： Digital filter apparatus in which a set of weighting signal samples to be multiplied in the filter has values which are exactly powers of two such that the filter multiplier network may be comprised of simple signal routing circuits.
摘要翻译：数字滤波器装置，其中要在滤波器中相乘的一组加权信号样本具有恰好是两倍的功率的值，使得滤波器乘法器网络可以由简单信号路由电路组成。

47. 发明申请

US20160203104A1 DIGITAL PROCESSING APPARATUS AND DIGITAL PROCESSING METHOD 有权
标题翻译：数字处理设备和数字处理方法
公开(公告)号：US20160203104A1
公开(公告)日：2016-07-14
申请号：US14914763
申请日：2014-08-20
申请人： NEC CORPORATION
发明人： HIDEMI NOGUCHI
IPC分类号： G06F17/14 , H04L25/03 , H03H17/02
CPC分类号： G06F17/14 , H03H17/0213 , H03H17/0226 , H03H17/0227 , H04B3/06 , H04L25/03057
摘要： In order to enhance the speed of a processing necessary for setting the factor of a filter and further maintain the accuracy of the filter, a digital processing apparatus includes: a Fourier transform unit that Fourier transforms a time domain digital signal, thereby generating N frequency domain signals; a filter unit that uses N first factors to process the frequency domain signals in the frequency domain; an inverse Fourier transform unit that transforms the frequency domain signals as processed by the filer unit to a time domain digital signal; a low accuracy factor calculation unit that uses m second factors to calculate N first A factors; a high accuracy factor calculation unit that includes a factor division unit for calculating respective ratios of N third factors to the N first A factors and that also includes a factor variable unit for calculating N first B factors varying stepwise from one to the respective ratios; a multiplication unit that multiplies the first A factors by the first B factors, thereby calculating the N first factors; and a control unit that controls the low accuracy factor calculation unit and high accuracy factor calculation unit by causing only the low accuracy factor calculation unit to operate with the first B factors being set to one and thereafter causing the high accuracy factor calculation unit to calculate the first B factors based on the third factors.
摘要翻译：为了提高设定滤波器系数所需的处理速度，进一步保持滤波器的精度，数字处理装置包括：傅立叶变换单元，对时域数字信号进行傅里叶变换，生成N频域信号; 滤波器单元，其使用N个第一因子来处理频域中的频域信号; 逆傅立叶变换单元，将由所述滤波器单元处理的频域信号变换为时域数字信号; 一个低精度因子计算单元，其使用m个第二因子来计算N个第一个A因子; 高精度因子计算单元，包括用于计算N个第三因子与N个第一A因子的相应比率的因子分割单元，并且还包括用于计算从一个到各个比率逐步变化的N个第一B个因子的因子可变单元; 乘法单元，将第一A因子乘以第一B因子，从而计算N个第一因子; 以及控制单元，其通过仅使所述低精度因子计算单元在所述第一B因子被设置为1的情况下操作来控制所述低精度因子计算单元和所述高精度因子计算单元，并且随后使所述高精度因子计算单元计算第一个B因素基于第三个因素。

48. 发明授权

US08848847B2 Sampling receiver with inherent mixer functionality 有权
标题翻译：具有固有混频器功能的采样接收机
公开(公告)号：US08848847B2
公开(公告)日：2014-09-30
申请号：US13443394
申请日：2012-04-10
申请人： Christoph Schultz , Markus Hammes , Rainer Kreienkamp
发明人： Christoph Schultz , Markus Hammes , Rainer Kreienkamp
IPC分类号： H04B1/10
CPC分类号： H03D7/125 , H03D2200/0062 , H03H17/0227 , H03H17/06 , H03H2015/007 , H03H2017/0692
摘要： One embodiment of the present invention relates to a combined mixer filter circuit. The circuit includes a sampler, a plurality of filter branches, and a coefficient generator. The sampler is configured to provide a sampled signal by sampling a received signal at a specified rate. The plurality of filter branches has selectable filter coefficients. The plurality of filter branches are configured to receive the sampled signal and generate a mixed and filtered output signal without a separate mixer component. The coefficient generator is coupled to the plurality of filter branches. The coefficient generator is configured to assign filter coefficient values to the selectable filter coefficients to yield a selected mixing function for the mixed filtered output signal.
摘要翻译：本发明的一个实施例涉及组合式混合器滤波器电路。电路包括采样器，多个滤波器分支和系数发生器。采样器被配置为通过以指定的速率对接收到的信号进行采样来提供采样信号。多个滤波器分支具有可选择的滤波器系数。多个滤波器分支被配置为接收采样信号，并产生混合和滤波的输出信号而没有单独的混频器部件。系数发生器耦合到多个滤波器分支。系数发生器被配置为将滤波器系数值分配给可选择的滤波器系数，以产生用于混合滤波输出信号的选择的混频功能。

49. 发明申请

US20130266101A1 Sampling Receiver with Inherent Mixer Functionality 有权
标题翻译：具有固有混频器功能的采样接收机
公开(公告)号：US20130266101A1
公开(公告)日：2013-10-10
申请号：US13443394
申请日：2012-04-10
申请人： Christoph Schultz , Markus Hammes , Rainer Kreienkamp
发明人： Christoph Schultz , Markus Hammes , Rainer Kreienkamp
IPC分类号： H04B1/10
CPC分类号： H03D7/125 , H03D2200/0062 , H03H17/0227 , H03H17/06 , H03H2015/007 , H03H2017/0692
摘要： One embodiment of the present invention relates to a combined mixer filter circuit. The circuit includes a sampler, a plurality of filter branches, and a coefficient generator. The sampler is configured to provide a sampled signal by sampling a received signal at a specified rate. The plurality of filter branches has selectable filter coefficients. The plurality of filter branches are configured to receive the sampled signal and generate a mixed and filtered output signal without a separate mixer component. The coefficient generator is coupled to the plurality of filter branches. The coefficient generator is configured to assign filter coefficient values to the selectable filter coefficients to yield a selected mixing function for the mixed filtered output signal.
摘要翻译：本发明的一个实施例涉及组合式混合器滤波器电路。电路包括采样器，多个滤波器分支和系数发生器。采样器被配置为通过以指定的速率对接收到的信号进行采样来提供采样信号。多个滤波器分支具有可选择的滤波器系数。多个滤波器分支被配置为接收采样信号，并产生混合和滤波的输出信号而没有单独的混频器部件。系数发生器耦合到多个滤波器分支。系数发生器被配置为将滤波器系数值分配给可选择的滤波器系数，以产生用于混合滤波输出信号的选择的混频功能。

50. 发明申请

US20120296608A1 SAMPLING RATE CONVERTING APPARATUS AND SAMPLING RATE CONVERTING METHOD 审中-公开
标题翻译：采样速率转换装置和采样速率转换方法
公开(公告)号：US20120296608A1
公开(公告)日：2012-11-22
申请号：US13574931
申请日：2011-01-20
申请人： Koji Tomitsuka , Hiroyasu Sano
发明人： Koji Tomitsuka , Hiroyasu Sano
IPC分类号： G06F15/00
CPC分类号： H03H17/0642 , H03H17/0227 , H03H17/0275 , H03H17/0294 , H03H2017/0222
摘要： A sampling rate converting apparatus that performs sampling frequency conversion includes: a sampling-phase detecting unit configured to calculate a sampling phase based on sampling timing after the sampling frequency conversion for each operation reference clock, based on a ratio of a frequency of an operation reference clock and a sampling frequency after the sampling frequency conversion; a sampling-clock detecting unit configured to detect a sampling period based on the sampling phase; a poliphase filter configured to apply filtering to an input signal and generate a signal after the sampling frequency conversion, based on the sampling period; and a filter-coefficient control unit configured to set a filter coefficient in the poliphase filter, based on the sampling phase.
摘要翻译：执行采样频率转换的采样率转换装置包括：采样相位检测单元，被配置为基于每个操作参考时钟的采样频率转换之后的采样定时，基于操作参考频率的比率来计算采样相位时钟和采样频率后的采样频率转换; 采样时钟检测单元，被配置为基于所述采样相位来检测采样周期; 配置为对输入信号进行滤波并根据采样周期产生采样频率转换后的信号的脉冲相滤波器; 以及滤波器系数控制单元，被配置为基于所述采样相位来设置所述相位滤波器中的滤波器系数。

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