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41. 发明申请

US20140367773A1 Method of Manufacturing a Semiconductor Device with Self-Aligned Contact Plugs and Semiconductor Device 有权
标题翻译：制造具有自对准接触插头和半导体器件的半导体器件的方法
公开(公告)号：US20140367773A1
公开(公告)日：2014-12-18
申请号：US13920179
申请日：2013-06-18
申请人： Infineon Technologies Austria AG
发明人： Martin Poelzl
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L23/528 , H01L21/76897 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/6634 , H01L29/66348 , H01L29/66621 , H01L29/66666 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7396 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/7825 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor oxide pillars are selectively grown on semiconductor mesas between precursor structures that extend from a main surface into a semiconductor substrate. Spaces between the semiconductor oxide pillars are filled with one or more auxiliary materials to form alignment plugs in a vertical projection of the precursor structures. The semiconductor oxide pillars are removed selectively against the alignment plugs. Contact spacers are provided along sidewalls of the alignment plugs. Between opposing ones of the contact spacers contact plugs are provided directly adjoining the semiconductor mesas. The contact plugs are self-aligned to the semiconductor mesas and allow a further reduction of the lateral dimensions of the semiconductor mesas without recessing the semiconductor mesas.
摘要翻译：半导体氧化物柱选择性地生长在从主表面延伸到半导体衬底中的前体结构之间的半导体台面上。半导体氧化物柱之间的空间填充有一种或多种辅助材料，以在前体结构的垂直投影中形成对准插塞。半导体氧化物柱被选择性地移除对准插塞。接触垫片沿对准插塞的侧壁设置。在相对的接触间隔件之间，接触插塞直接邻接半导体台面。接触插塞与半导体台面自对准，并允许半导体台面的横向尺寸进一步减小而不会使半导体台面凹陷。

42. 发明申请

US20140339602A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20140339602A1
公开(公告)日：2014-11-20
申请号：US14375895
申请日：2013-02-18
申请人： DENSO CORPORATION
发明人： Yasushi Higuchi , Masakiyo Sumitomo
IPC分类号： H01L29/739 , H01L29/08 , H01L29/10
CPC分类号： H01L29/7393 , H01L29/0808 , H01L29/1008 , H01L29/1095 , H01L29/4236 , H01L29/7394 , H01L29/7397 , H01L29/7824 , H01L29/7825
摘要： In a trench-gate-type insulated gate bipolar transistor, a current will not flow down to a lower portion of a trench, a high electrical field at the lower portion of the trench is suppressed even if a high voltage is applied, such as at a time of turning off, an increase in on-state resistance and a decrease in breakdown resistance and withstand voltage are suppressed. In the semiconductor device, a plurality of trenches is disposed to reach a rear surface of a drift layer, and a collector layer is disposed at a tip end side in an extended direction of the trenches in a surface layer portion of the drift layer. When a gate electrode is applied with a predetermined voltage, a channel region is formed in a portion of the base layer contacting the trenches, and an electric current flows in the predetermined direction along the trenches.
摘要翻译：在沟槽栅型绝缘栅双极晶体管中，电流不会向下流到沟槽的下部，即使施加高电压，也抑制沟槽下部的高电场，例如在关断时间，抑制导通电阻的上升和耐击穿电压和耐电压的降低。在半导体器件中，设置多个沟槽到达漂移层的后表面，并且集电极层设置在漂移层的表面层部分中的沟槽的延伸方向的前端侧。当施加预定电压的栅电极时，在接触沟槽的基底层的一部分中形成沟道区，并且电流沿着沟槽沿预定方向流动。

43. 发明授权

US08866217B2 Vertical gate LDMOS device 有权
标题翻译：垂直门LDMOS器件
公开(公告)号：US08866217B2
公开(公告)日：2014-10-21
申请号：US13572015
申请日：2012-08-10
申请人： Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan
发明人： Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/66704 , H01L21/265 , H01L21/28105 , H01L21/823481 , H01L27/088 , H01L29/0626 , H01L29/063 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66696 , H01L29/78 , H01L29/7802 , H01L29/7825 , H01L29/7827 , H01L29/7835
摘要： Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.
摘要翻译：这里描述的是晶体管及其制造方法。在一个实施方式中，晶体管包括注入到衬底的表面中的n阱区域和n阱区域中的沟槽。沟槽从表面延伸到第一深度。沟槽包括在沟槽中的导电材料的栅极，以及填充未被导电材料填充的一定体积的电介质材料。晶体管还包括在从第二深度延伸到第三深度的第一区域中的p型材料，第二深度和第三深度大于第一深度。晶体管还包括源极区和漏极区。

44. 发明授权

US08860136B2 Semiconductor device and method of manufacturing a semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08860136B2
公开(公告)日：2014-10-14
申请号：US13692397
申请日：2012-12-03
申请人： Infineon Technologies AG
发明人： Andreas Meiser , Till Schloesser
IPC分类号： H01L27/06 , H01L29/78 , H01L29/66
CPC分类号： H01L29/78 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/42376 , H01L29/66666 , H01L29/66696 , H01L29/66704 , H01L29/7825 , H01L29/785
摘要： A semiconductor device includes a transistor, formed in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode being adjacent to the channel region, the gate electrode configured to control a conductivity of a channel formed in the channel region. The channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a ridge extending along the first direction and the drift zone including a superjunction layer stack.
摘要翻译：半导体器件包括形成在具有第一主表面的半导体衬底中的晶体管。所述晶体管包括源极区，漏极区，沟道区，漂移区以及与所述沟道区相邻的栅极，所述栅电极被配置为控制在所述沟道区中形成的沟道的导电性。沟道区域和漂移区域沿着源极区域和漏极区域之间的第一方向设置，第一方向平行于第一主表面。沟道区具有沿着第一方向延伸的脊的形状，并且漂移区包括超结层层叠。

45. 发明申请

US20140291762A1 POWER DEVICE INTEGRATION ON A COMMON SUBSTRATE 有权
公开(公告)号：US20140291762A1
公开(公告)日：2014-10-02
申请号：US14305632
申请日：2014-06-16
申请人： IO Semiconductor Inc.
发明人： Jacek Korec , Boyi Yang
IPC分类号： H01L29/872 , H01L29/78
CPC分类号： H01L29/0626 , H01L21/823437 , H01L21/8249 , H01L27/0629 , H01L27/0635 , H01L27/088 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/36 , H01L29/402 , H01L29/41766 , H01L29/42304 , H01L29/4236 , H01L29/4933 , H01L29/66181 , H01L29/66659 , H01L29/66681 , H01L29/66696 , H01L29/66704 , H01L29/7302 , H01L29/735 , H01L29/78 , H01L29/7821 , H01L29/7824 , H01L29/7825 , H01L29/7835 , H01L29/8605 , H01L29/861 , H01L29/872 , H01L29/94 , H01L2224/0401 , H01L2224/05552 , H01L2224/05569 , H01L2224/05572 , H01L2224/11 , H01L2224/13 , H01L2924/00 , H01L2924/00014 , H01L2924/12032 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091
摘要： A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

46. 发明申请

US20140225190A1 SEMICONDUCTOR DEVICE EMPLOYING TRENCHES FOR ACTIVE GATE AND ISOLATION 审中-公开
标题翻译：用于主动门和隔离的半导体器件
公开(公告)号：US20140225190A1
公开(公告)日：2014-08-14
申请号：US14196286
申请日：2014-03-04
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Shekar Mallikarjunaswamy
IPC分类号： H01L29/78 , H01L27/092
CPC分类号： H01L29/407 , H01L21/823412 , H01L21/823807 , H01L21/8249 , H01L27/0617 , H01L27/0623 , H01L27/092 , H01L29/0634 , H01L29/0649 , H01L29/0696 , H01L29/0821 , H01L29/0878 , H01L29/1095 , H01L29/408 , H01L29/4175 , H01L29/42356 , H01L29/4236 , H01L29/42368 , H01L29/732 , H01L29/7393 , H01L29/7813 , H01L29/7816 , H01L29/7817 , H01L29/7823 , H01L29/7825 , H01L29/7831
摘要： A semiconductor device with multiple transistor devices includes a semiconductor layer of a first conductivity type formed on a substrate; a first trench formed in the semiconductor layer including a first trench gate; a second trench formed in the semiconductor layer and extending into the substrate and including a second trench gate; a first transistor device being an LDMOS transistor formed in the semiconductor layer between the first trench and the second trench; and a second transistor device formed in the semiconductor layer on the other side of the second trench. The first transistor device is electrically isolated from the second transistor device by the second trench.
摘要翻译：具有多个晶体管器件的半导体器件包括形成在衬底上的第一导电类型的半导体层; 在所述半导体层中形成的包括第一沟槽栅极的第一沟槽; 形成在所述半导体层中并且延伸到所述衬底中并且包括第二沟槽栅极的第二沟槽; 第一晶体管器件是在第一沟槽和第二沟槽之间的半导体层中形成的LDMOS晶体管; 以及形成在第二沟槽的另一侧上的半导体层中的第二晶体管器件。第一晶体管器件通过第二沟槽与第二晶体管器件电隔离。

47. 发明申请

US20140191313A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140191313A1
公开(公告)日：2014-07-10
申请号：US14208911
申请日：2014-03-13
申请人： Seiko Instruments Inc.
发明人： Masayuki HASHITANI
IPC分类号： H01L29/10 , H01L29/78
CPC分类号： H01L29/1037 , H01L29/0847 , H01L29/66575 , H01L29/66621 , H01L29/78 , H01L29/7825
摘要： Provided is a semiconductor device formed with a trench portion for providing a concave portion in a gate width direction and with a gate electrode provided within and on a top surface of the trench portion via a gate insulating film. At least a part of a surface of each of the source region and the drain region is made lower than other parts of the surface by removing a thick oxide film formed in the vicinity of the gate electrode. Making lower the part of the surface of each of the source region and the drain region allows current flowing through a top surface of the concave portion of the gate electrode at high concentration to flow uniformly through the entire trench portion, which increase an effective gate width of the concave portion formed so as to have a varying depth in a gate width direction.
摘要翻译：提供了一种半导体器件，其形成有沟槽部分，用于在栅极宽度方向上提供凹部，并且栅极电极经由栅极绝缘膜设置在沟槽部分的顶表面内和栅极电极的顶表面上。通过除去形成在栅电极附近的厚氧化膜，使源极区域和漏极区域中的每一个的表面的至少一部分被制成为低于表面的其它部分。使源极区域和漏极区域中的每一个的部分表面下降，允许以高浓度流过栅电极的凹部的顶表面的电流均匀地流过整个沟槽部分，这增加了有效栅极宽度所述凹部形成为在栅极宽度方向上具有变化的深度。

48. 发明申请

US20140117407A1 POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US20140117407A1
公开(公告)日：2014-05-01
申请号：US14149578
申请日：2014-01-07
申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.
发明人： In Hyuk Song , Jae Hoon Park , Dong Soo Seo
IPC分类号： H01L29/66 , H01L21/265 , H01L29/739
CPC分类号： H01L29/6634 , H01L21/046 , H01L21/22 , H01L21/2253 , H01L21/265 , H01L21/3081 , H01L21/324 , H01L29/0847 , H01L29/1095 , H01L29/36 , H01L29/4236 , H01L29/66325 , H01L29/66348 , H01L29/66674 , H01L29/7393 , H01L29/7397 , H01L29/7825
摘要： Disclosed herein is a power semiconductor device including: a base substrate having one surface and the other surface and formed of a first conductive type drift layer; a first conductive type diffusion layer formed on one surface of the base substrate and having a concentration higher than that of the first conductive type drift layer; and a trench formed so as to penetrate through the second conductive type well layer and the first conductive type diffusion layer from one surface of the base substrate including the second conductive type well layer in a thickness direction.
摘要翻译：本发明公开了一种功率半导体器件，包括：具有一个表面和另一个表面并由第一导电型漂移层形成的基底基板; 形成在所述基底基板的一个表面上并且具有比所述第一导电型漂移层的浓度高的浓度的第一导电型扩散层; 以及形成为从厚度方向包括第二导电类型阱层的基底基板的一个表面穿过第二导电型阱层和第一导电型扩散层的沟槽。

49. 发明授权

US08674436B2 Lateral double diffusion metal-oxide semiconductor device and method for manufacturing the same 有权
标题翻译：横向双扩散金属氧化物半导体器件及其制造方法
公开(公告)号：US08674436B2
公开(公告)日：2014-03-18
申请号：US13406726
申请日：2012-02-28
申请人： Jong Seok Lee , Kyoung Kook Hong
发明人： Jong Seok Lee , Kyoung Kook Hong
IPC分类号： H01L29/78 , H01L29/06
CPC分类号： H01L29/0657 , H01L29/0634 , H01L29/1608 , H01L29/42368 , H01L29/66068 , H01L29/7825
摘要： Disclosed is an LDMOS device, which is configured to reduce an electric field concentrated to a gate oxide film and lower an ON-resistance produced when the device conducts a forward action, and a method for manufacturing the same. More specifically, when an n-drift region is formed on a P-type substrate, a p-body is formed on the n-drift region through an epitaxial process, and then the p-body region is partially etched to form a plurality of p-epitaxial layers, so that when the device executes an action for blocking a reverse voltage, depletion layers are formed between the junction surfaces of the p-epitaxial layers and the n-drift region including the junction surfaces between the n-drift region and the p-body.
摘要翻译：公开了一种LDMOS器件，其被配置为减少集中到栅极氧化物膜的电场并降低当器件进行正向动作时产生的导通电阻及其制造方法。更具体地，当在P型衬底上形成n漂移区时，通过外延工艺在n漂移区上形成p体，然后部分蚀刻p体区以形成多个使得当器件执行用于阻止反向电压的动作时，在p-外延层的连接表面和n漂移区之间形成耗尽层，该n-漂移区域包括n-漂移区和 p体。

50. 发明申请

US20140061717A1 POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20140061717A1
公开(公告)日：2014-03-06
申请号：US13688320
申请日：2012-11-29
申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.
发明人： In Hyuk Song , Jae Hoon Park , Dong Soo Seo
IPC分类号： H01L29/739 , H01L29/66
CPC分类号： H01L29/6634 , H01L21/046 , H01L21/22 , H01L21/2253 , H01L21/265 , H01L21/3081 , H01L21/324 , H01L29/0847 , H01L29/1095 , H01L29/36 , H01L29/4236 , H01L29/66325 , H01L29/66348 , H01L29/66674 , H01L29/7393 , H01L29/7397 , H01L29/7825
摘要： Disclosed herein is a power semiconductor device including: a base substrate having one surface and the other surface and formed of a first conductive type drift layer; a first conductive type diffusion layer formed on one surface of the base substrate and having a concentration higher than that of the first conductive type drift layer; and a trench formed so as to penetrate through the second conductive type well layer and the first conductive type diffusion layer from one surface of the base substrate including the second conductive type well layer in a thickness direction.

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