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41. 发明申请

US20130052831A1 METHOD OF PATTERNING HARD MASK LAYER FOR DEFINING DEEP TRENCH 有权
标题翻译：用于定义深层TRENCH的硬掩模层的方法
公开(公告)号：US20130052831A1
公开(公告)日：2013-02-28
申请号：US13218281
申请日：2011-08-25
申请人： Sheng-Jie Hsu , Shin-He Siao
发明人： Sheng-Jie Hsu , Shin-He Siao
IPC分类号： H01L21/32
CPC分类号： H01L21/31116 , H01L21/31144 , H01L27/1087 , H01L29/66181
摘要： A method of patterning a hard mask layer for defining a deep trench is described. A substrate formed with an isolation structure therein is provided. A hard mask layer is formed over the substrate provided. A patterned photoresist layer is formed over the hard mask layer, having therein a deep-trench opening pattern over the isolation structure. An etching gas not containing hydrogen is used to etch the hard mask layer with the patterned photoresist layer as a mask and thereby transfer the deep-trench opening pattern to the hard mask layer.
摘要翻译：描述了用于限定深沟槽的硬掩模层的图案化方法。提供了在其中形成有隔离结构的基板。在所提供的基板上形成硬掩模层。在硬掩模层之上形成图案化的光致抗蚀剂层，其中在隔离结构上具有深沟槽开口图案。使用不含氢的蚀刻气体来蚀刻具有图案化的光致抗蚀剂层作为掩模的硬掩模层，从而将深沟槽开口图案转移到硬掩模层。

42. 发明授权

US08377829B2 Method of manufacturing a capacitor deep trench and of etching a deep trench opening 有权
标题翻译：制造电容器深沟槽并蚀刻深沟槽开口的方法
公开(公告)号：US08377829B2
公开(公告)日：2013-02-19
申请号：US11871166
申请日：2007-10-12
申请人： Ta-Chuan Yeh , Ni-Min Chung , Kao-Su Huang , Yung-Chang Lin , Ruey-Chyr Lee , Chien-Kuo Wang
发明人： Ta-Chuan Yeh , Ni-Min Chung , Kao-Su Huang , Yung-Chang Lin , Ruey-Chyr Lee , Chien-Kuo Wang
IPC分类号： H01L21/302 , H01L21/461 , B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00
CPC分类号： H01L27/1087 , H01L21/76205
摘要： A substrate is provided having an oxide layer, a first nitride-silicon, a STI, and a second nitride-silicon. A pattern poly-silicon layer on the second nitride-silicon layer is etched to form a deep trench opening. Etching the pattern poly-silicon layer also deepens the deep trench opening. Then, a conductive layer is filled in the deep trench opening.
摘要翻译：提供了具有氧化物层，第一氮化硅 - 硅，STI和第二氮化硅 - 硅的衬底。蚀刻第二氮化硅 - 硅层上的图案多晶硅层以形成深沟槽开口。蚀刻图案多晶硅层也加深了深沟槽开口。然后，在深沟槽开口中填充导电层。

43. 发明申请

US20130032929A1 METHOD OF PROTECTING DEEP TRENCH SIDEWALL FROM PROCESS DAMAGE 审中-公开
标题翻译：从过程损坏中保护深层钢板的方法
公开(公告)号：US20130032929A1
公开(公告)日：2013-02-07
申请号：US13198873
申请日：2011-08-05
申请人： Effendi Leobandung
发明人： Effendi Leobandung
IPC分类号： H01L23/482 , H01L21/311
CPC分类号： H01L27/1087 , H01L21/76224 , H01L21/84 , H01L27/1203 , H01L29/66181 , H01L29/945
摘要： Method of protecting a liner in a previously formed deep trench module from subsequent processing steps, and resulting structure. A deep trench module includes a deep trench with one or more liner films and a fill material in an SOI substrate. A mask layer is patterned to form first and second masks aligned over the liner films on first and second sidewalls of the deep trench, respectively. Further etching creates a polysilicon tab under the first mask which protects the liner film adjacent the first sidewall from being exposed during subsequent etches. The second mask protects its underlying polysilicon from subsequent etches to maintain a conduction strap from SOI layer to deep trench. The masks are removed. An isolation film is deposited on the substrate and planarized to form and isolation region. The resulting structure has a polysilicon tab interposed between the deep trench liner and the isolation region.
摘要翻译：在先前形成的深沟槽模块中保护衬垫的方法不受后续处理步骤的影响，以及结果。深沟槽模块包括具有一个或多个衬垫膜的深沟槽和SOI衬底中的填充材料。图案化掩模层以形成分别在深沟槽的第一和第二侧壁上的衬垫膜上对准的第一和第二掩模。进一步的蚀刻在第一掩模下形成多晶硅片，保护邻近第一侧壁的衬垫膜在随后的蚀刻期间被暴露。第二个掩模保护其底层多晶硅免受后续腐蚀，以保持从SOI层到深沟槽的导带。去除面具。将隔离膜沉积在衬底上并平坦化以形成和分离区域。所得结构具有插入深沟槽衬垫和隔离区之间的多晶硅片。

44. 发明申请

US20130032868A1 TRENCH CAPACITOR WITH SPACER-LESS FABRICATION PROCESS 失效
标题翻译：具有无间隙制造工艺的TRENCH电容器
公开(公告)号：US20130032868A1
公开(公告)日：2013-02-07
申请号：US13198100
申请日：2011-08-04
申请人： Chengwen Pei , Xi Li , Geng Wang
发明人： Chengwen Pei , Xi Li , Geng Wang
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L29/0692 , H01L21/3081 , H01L21/3086 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L29/66181 , H01L29/945
摘要： A trench capacitor and method of fabrication are disclosed. The SOI region is doped such that a selective isotropic etch used for trench widening does not cause appreciable pullback of the SOI region, and no spacers are needed in the upper portion of the trench.
摘要翻译：公开了一种沟槽电容器和制造方法。掺杂SOI区域使得用于沟槽加宽的选择性各向同性蚀刻不会导致SOI区域的明显的回退，并且在沟槽的上部不需要间隔物。

45. 发明申请

US20120181665A1 STRUCTURE AND METHOD FOR HARD MASK REMOVAL ON AN SOI SUBSTRATE WITHOUT USING CMP PROCESS 失效
标题翻译：不使用CMP工艺在SOI衬底上进行硬掩模去除的结构和方法
公开(公告)号：US20120181665A1
公开(公告)日：2012-07-19
申请号：US13009056
申请日：2011-01-19
申请人： OH-JUNG KWON
发明人： OH-JUNG KWON
IPC分类号： H01L29/06 , G06F17/50 , H01L21/20
CPC分类号： H01L27/1087 , H01L21/3081 , H01L21/31111 , H01L21/31144 , H01L29/66181
摘要： A hard mask material is removed from an SOI substrate without using a chemical mechanical polish (CMP) process. A blocking material is deposited on a hard mask material after a deep trench reactive ion etch (RIE) process. The blocking material on top of the hard mask material is removed. A selective wet etching process is used to remove the hard mask material. Trench recess depth is effectively controlled.
摘要翻译：不使用化学机械抛光（CMP）工艺，从SOI衬底去除硬掩模材料。在深沟槽反应离子蚀刻（RIE）工艺之后，将阻挡材料沉积在硬掩模材料上。去除硬掩模材料顶部的阻挡材料。使用选择性湿法蚀刻工艺去除硬掩模材料。沟槽深度有效控制。

46. 发明授权

US08198169B2 Deep trench capacitor in a SOI substrate having a laterally protruding buried strap 有权
标题翻译： SOI衬底中的深沟槽电容器具有横向突出的埋入带
公开(公告)号：US08198169B2
公开(公告)日：2012-06-12
申请号：US12974451
申请日：2010-12-21
申请人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
发明人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
IPC分类号： H01L21/425
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1087
摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
摘要翻译：深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。节点电介质和沟槽填充材料沉积到深沟槽中。掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

47. 发明申请

US20110204429A1 DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：动态随机存取存储器（DRAM）电池及其制造方法
公开(公告)号：US20110204429A1
公开(公告)日：2011-08-25
申请号：US13098193
申请日：2011-04-29
申请人： Hyun-Jin CHO , Sang H. DHONG , Jung-Suk GOO , Gurupada MANDAL
发明人： Hyun-Jin CHO , Sang H. DHONG , Jung-Suk GOO , Gurupada MANDAL
IPC分类号： H01L27/108
CPC分类号： H01L27/10802 , H01L27/108 , H01L27/1082 , H01L27/1087 , H01L29/7841
摘要： A semiconductor memory cell is provided that includes a trench capacitor and an access transistor. The access transistor comprises a source region, a drain region, a gate structure overlying the trench capacitor, and an active body region that couples the drain region to the source region. The active body region directly contacts the trench capacitor.
摘要翻译：提供一种包括沟槽电容器和存取晶体管的半导体存储单元。存取晶体管包括源区域，漏极区域，覆盖沟槽电容器的栅极结构以及将漏极区域耦合到源极区域的有源体区域。有源体区域直接接触沟槽电容器。

48. 发明授权

US08003488B2 Shallow trench isolation structure compatible with SOI embedded DRAM 有权
标题翻译：浅沟槽隔离结构与SOI嵌入式DRAM兼容
公开(公告)号：US08003488B2
公开(公告)日：2011-08-23
申请号：US11861614
申请日：2007-09-26
申请人： Kangguo Cheng , Munir D. Naeem , David M. Dobuzinsky , Byeong Y. Kim
发明人： Kangguo Cheng , Munir D. Naeem , David M. Dobuzinsky , Byeong Y. Kim
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L27/1087 , H01L21/84 , H01L27/1203
摘要： A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of the pad layer having an edge that is vertically coincident with a sidewall of the deep trench is exposed by lithographic means. Exposed portion of the pad layer are removed selective to the planarizing material layer, followed by removal of exposed portion of a semiconductor layer selective to the conductive trench fill region by an anisotropic etch. The planarizing material layer is removed and a shallow trench isolation structure having a lower sidewall that is self-aligned to an edge of the original deep trench is formed. Another shallow trench isolation structure may be formed outside the deep trench concurrently.
摘要翻译：在绝缘体上半导体（SOI）衬底和其上的衬垫层上形成深沟槽。在深沟槽中形成导电沟槽填充区域。施加具有相对于焊盘层的蚀刻选择性的平坦化材料层。具有与深沟槽的侧壁垂直一致的边缘的焊盘层的一部分被光刻装置暴露。对平坦化材料层选择性地去除衬垫层的暴露部分，然后通过各向异性蚀刻去除对导电沟槽填充区域选择性的半导体层的暴露部分。去除平坦化材料层，并且形成具有与原始深沟槽的边缘自对准的下侧壁的浅沟槽隔离结构。另一个浅沟槽隔离结构可以同时形成在深沟槽的外部。

49. 发明授权

US07999300B2 Memory cell structure and method for fabrication thereof 有权
标题翻译：存储单元结构及其制造方法
公开(公告)号：US07999300B2
公开(公告)日：2011-08-16
申请号：US12361521
申请日：2009-01-28
申请人： Zhao Lun , James Yong Meng Lee , Lee Wee Teo , Shyue Seng Tan , Chung Woh Lai , Johnny Widodo , Shailendra Mishra , Jeffrey Chee
发明人： Zhao Lun , James Yong Meng Lee , Lee Wee Teo , Shyue Seng Tan , Chung Woh Lai , Johnny Widodo , Shailendra Mishra , Jeffrey Chee
IPC分类号： H01L27/108
CPC分类号： H01L27/11 , H01L27/1085 , H01L27/1087 , H01L28/88 , H01L29/66181 , Y10S257/903
摘要： A memory cell includes a substrate, an access transistor and a storage capacitor. The access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion region located on a first and second opposing sides of the gate stack. The storage capacitor comprises a first capacitor plate comprising a portion embedded within the substrate below the first diffusion region, a second capacitor plate and a capacitor dielectric sandwiched between the embedded portion of the first capacitor plate. At least a portion of the first diffusion region forms the second capacitor plate.
摘要翻译：存储单元包括衬底，存取晶体管和存储电容器。所述存取晶体管包括设置在所述衬底上的栅极堆叠，以及位于所述栅极堆叠的第一和第二相对侧上的第一和第二扩散区域。存储电容器包括：第一电容器板，包括嵌入在第一扩散区域下方的衬底内的部分，第二电容器板和夹在第一电容器板的嵌入部分之间的电容器电介质。第一扩散区的至少一部分形成第二电容器板。

50. 发明申请

US20110169065A1 METHOD AND STRUCTURE FOR FORMING CAPACITORS AND MEMORY DEVICES ON SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES 有权
标题翻译：在半导体绝缘体（SOI）衬底上形成电容器和存储器件的方法和结构
公开(公告)号：US20110169065A1
公开(公告)日：2011-07-14
申请号：US12686403
申请日：2010-01-13
申请人： Kangguo Cheng , Ramachandra Divakaruni
发明人： Kangguo Cheng , Ramachandra Divakaruni
IPC分类号： H01L27/06 , H01L21/8242
CPC分类号： H01L21/84 , H01L27/0207 , H01L27/1087 , H01L27/10894 , H01L27/1203 , H01L29/66181
摘要： A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided.
摘要翻译：提供了一种在绝缘体上半导体（SOI）衬底上包括存储器，逻辑和电容器结构的器件。在一个实施例中，该器件包括具有存储区域和逻辑区域的绝缘体上半导体（SOI）衬底。沟槽电容器存在于存储器区域和逻辑区域中，其中每个沟槽电容器在结构上相同。第一晶体管存在于与存在于存储器区域中的至少一个沟槽电容器的第一电极电连通的存储区域中。第二晶体管存在于通过绝缘材料与沟槽电容器物理分离的逻辑区域中。在一些实施例中，存在于逻辑区域中的沟槽电容器包括去耦电容器和无效电容器。还提供了一种用于形成上述装置的方法。

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