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41. 发明授权

US09595327B2 Variable resistance memory device and verify method thereof 有权
标题翻译：可变电阻存储器件及其验证方法
公开(公告)号：US09595327B2
公开(公告)日：2017-03-14
申请号：US14847395
申请日：2015-09-08
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kikuko Sugimae , Reika Ichihara
IPC分类号： G11C13/00
CPC分类号： G11C13/0064 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0092 , G11C2213/77
摘要： A resistance variable memory has a controller configured to control a voltage to be applied to the memory cell. The controller has a reset operation to bring the memory cell into a reset state, a first operation to apply a set voltage between the first wire and the second wire, a second operation to determine whether a current flowing to the memory cell to be set exceeds a first threshold when a first reading voltage is applied between the first wire and the second wire, a third operation to determine whether a current flowing to the memory cell to be set exceeds a second threshold when a second reading voltage is applied between the first wire and the second wire, and a fourth operation to apply a second reset voltage, between the first wire and the second wire.
摘要翻译：电阻变量存储器具有被配置为控制要施加到存储单元的电压的控制器。控制器具有复位操作以使存储器单元进入复位状态，第一操作在第一线和第二线之间施加设定电压，第二操作确定流向要设定的存储单元的电流是否超过当在第一线和第二线之间施加第一读取电压时的第一阈值，当在第一线和第二线之间施加第二读取电压时，确定流向待设置的存储器单元的电流是否超过第二阈值的第三操作和第二线，以及在第一线和第二线之间施加第二复位电压的第四操作。

42. 发明授权

US09564585B1 Multi-level phase change device 有权
标题翻译：多级相变装置
公开(公告)号：US09564585B1
公开(公告)日：2017-02-07
申请号：US14845016
申请日：2015-09-03
申请人： HGST Netherlands B.V.
发明人： Jeffrey Lille , Luiz M. Franca-Neto
IPC分类号： G11C13/00 , H01L45/00 , H01L27/24 , G11C11/56
CPC分类号： G11C13/0069 , G11C11/5678 , G11C13/0002 , G11C13/0004 , G11C2013/0092 , G11C2213/51 , H01L27/2436 , H01L27/2445 , H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/1246 , H01L45/126 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/148
摘要： Embodiments of the present disclosure generally relate to electronic devices, and more specifically, to multi-level phase change devices. In one embodiment, a memory cell device is provided. The memory cell device generally includes a top surface, a bottom surface and a cell body between the top surface and the bottom surface. The cell body may include a plurality of phase change material layers, which may be used to store data of the cell. In another embodiment, a method of programming a memory cell is provided. The method generally may include applying a sequence of different pulses to each phase change material layer of the cell as the voltage of each pulse in the sequence is ratcheted down from the start of a write cycle to the end of a write cycle.
摘要翻译：本公开的实施例一般涉及电子设备，更具体地涉及多电平相位变换设备。在一个实施例中，提供了存储单元装置。存储单元装置通常包括顶表面，底表面和在顶表面和底表面之间的电池体。电池体可以包括多个相变材料层，其可以用于存储电池的数据。在另一个实施例中，提供了一种编程存储器单元的方法。该方法通常可以包括将不同脉冲的序列应用于单元的每个相变材料层，因为序列中的每个脉冲的电压从写入周期的开始向下被写入到写入周期的结束。

43. 发明授权

US09564214B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US09564214B2
公开(公告)日：2017-02-07
申请号：US14817392
申请日：2015-08-04
申请人： Kabushiki Kaisha Toshiba
发明人： Kazuhiko Yamamoto , Kunifumi Suzuki
IPC分类号： G11C13/00 , H01L45/00 , H01L27/24
CPC分类号： G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/0033 , G11C13/0035 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/005 , G11C2013/0073 , G11C2013/009 , G11C2013/0092 , G11C2213/33 , G11C2213/35 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/79 , H01L27/2463 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/141 , H01L45/144 , H01L45/1608
摘要： According to one embodiment, a memory device includes a controller; a first electrode and a second electrode connected to the controller; and a variable resistance layer provided between the first electrode and the second electrode. The variable resistance layer has a first structure, and a second structure. The controller configured to be able to perform a first operation of applying a first voltage between the first electrode and the second electrode, a second operation of applying a second voltage between the first electrode and the second electrode and determining whether or not the variable resistance layer has the second structure, and a third operation of applying a third voltage between the first electrode and the second electrode having the interposed variable resistance layer determined to not have the second structure in the second operation.
摘要翻译：根据一个实施例，存储器件包括控制器; 连接到所述控制器的第一电极和第二电极; 以及设置在第一电极和第二电极之间的可变电阻层。可变电阻层具有第一结构和第二结构。控制器被配置为能够执行在第一电极和第二电极之间施加第一电压的第一操作，第二操作在第一电极和第二电极之间施加第二电压，并且确定可变电阻层具有第二结构，以及在具有在第二操作中被确定为不具有第二结构的插入的可变电阻层的第一电极和第二电极之间施加第三电压的第三操作。

44. 发明授权

US09558823B1 Resistance drift recovery method for MLC PCM 有权
标题翻译： MLC PCM电阻漂移恢复方法
公开(公告)号：US09558823B1
公开(公告)日：2017-01-31
申请号：US14846393
申请日：2015-09-04
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Win-San Khwa , Tzu-Hsiang Su , Chao-I Wu , Hsiang-Pan Li , Meng-Fan Chang
IPC分类号： G11C11/00 , G11C13/00 , G11C11/56
CPC分类号： G11C13/0069 , G11C11/5678 , G11C13/0004 , G11C13/0021 , G11C13/0033 , G11C13/004 , G11C2013/0092
摘要： A method is provided for operating a memory device including an array of memory cells including programmable resistive memory elements. Memory cells in the array are programmed to store data by applying program pulses to the memory cells to establish resistance levels within a number N of specified ranges of resistance, where each of the specified ranges corresponds to a particular data value. A drift recovery process is executed to the memory cells, including applying a recovery pulse having a pulse shape to a set of programmed memory cells, where memory cells in the set have resistance levels within two or more of the specified resistance ranges.
摘要翻译：提供一种用于操作包括包括可编程电阻存储器元件的存储单元阵列的存储器件的方法。阵列中的存储单元被编程为通过向存储器单元施加编程脉冲来存储数据，以建立指定范围电阻数量N内的电阻电平，其中每个指定范围对应于特定数据值。对存储器单元执行漂移恢复处理，包括将具有脉冲形状的恢复脉冲施加到一组编程存储器单元，其中该组中的存储单元具有在指定电阻范围内的两个或更多个内的电阻电平。

45. 发明授权

US09552877B2 Writable device based on alternating current 有权
标题翻译：基于交流电的可写器件
公开(公告)号：US09552877B2
公开(公告)日：2017-01-24
申请号：US14889738
申请日：2013-05-29
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： Robert J. Brooks
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0007 , G11C13/0009 , G11C2013/0073 , G11C2013/008 , G11C2013/009 , G11C2013/0092
摘要： A nonvolatile memory device is writable to a high resistance state and a low resistance state. The nonvolatile memory device may be heated to at least a threshold temperature, based on application of an alternating current (AC) signal, and may be written based on application of a voltage bias.
摘要翻译：非易失性存储器件可写入高电阻状态和低电阻状态。可以基于施加交流（AC）信号将非易失性存储器件加热到至少一个阈值温度，并且可以基于施加电压偏置而被写入。

46. 发明授权

US09543004B1 Provision of holding current in non-volatile random access memory 有权
标题翻译：在非易失性随机存取存储器中提供保持电流
公开(公告)号：US09543004B1
公开(公告)日：2017-01-10
申请号：US14742316
申请日：2015-06-17
申请人： Intel Corporation
发明人： Dany-Sebastien Ly-Gagnon , Kiran Pangal , Raymond W. Zeng , Mase J. Taub
IPC分类号： G11C13/00 , G06F11/10 , G11C7/04 , G11C11/56 , H04L29/06
CPC分类号： G11C11/00 , G06F11/1048 , G11C7/04 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0045 , G11C2013/0078 , G11C2013/0092 , G11C2213/77 , H01L29/06 , H04L65/403
摘要： Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了用于控制非易失性随机存取存储器（NVRAM）设备中的电流的技术和配置。在一个实施例中，NVRAM器件可以包括耦合到多个位线的多个存储器单元，其形成具有寄生电容的位线节点。每个存储器单元可以包括具有保持电流的所需电平的开关器件，以保持电池的导通状态。电压供应电路和控制器可以与NVRAM器件耦合。控制器可以控制电路以提供使存储器单元处于导通状态的电流脉冲。响应于在实现设定点之后通过存储器单元的位线节点电容的放电，脉冲可以包括随时间从设定点改变到保持电流电平的分布。可以描述和/或要求保护其他实施例。

47. 发明授权

US09530494B2 Memory device and method of operating the same 有权
标题翻译：存储器件及其操作方法
公开(公告)号：US09530494B2
公开(公告)日：2016-12-27
申请号：US14697244
申请日：2015-04-27
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Yong-Kyu Lee , Dae-Seok Byeon , Yeong-Taek Lee , Chi-Weon Yoon , Hyun-Kook Park , Hyo-Jin Kwon
IPC分类号： G11C16/10 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0033 , G11C13/0035 , G11C16/10 , G11C2013/0092
摘要： A method of operating a memory device, which includes of memory cells respectively arranged in regions where first signal lines and second lines cross each other, includes determining a plurality of pulses so that each of the plurality of pulses that are sequentially applied to a selected memory cell among the plurality of memory cells is changed according to a number of times of executing programming loops. In response to the change of the plurality of pulses, at least one of a first inhibit voltage and a second inhibit voltage is determined so that a voltage level of at least one of the first and second inhibit voltages that are respectively applied to unselected first and second signal lines connected to unselected memory cells among the plurality of memory cells is changed according to the number of times of executing the programming loops.
摘要翻译：一种操作存储器件的方法，所述存储器件包括分别布置在第一信号线和第二线彼此交叉的区域中的存储器单元，包括确定多个脉冲，使得多个脉冲中的每一个顺序地施加到选择的存储器根据执行编程循环的次数来改变多个存储单元之间的单元。响应于多个脉冲的变化，确定第一禁止电压和第二禁止电压中的至少一个，使得分别施加到未选择的第一和第二禁止电压中的至少一个的电压电平，连接到多个存储单元之间的未选择的存储单元的第二信号线根据执行编程循环的次数而改变。

48. 发明申请

US20160358652A1 RESET CURRENT DELIVERY IN NON-VOLATILE RANDOM ACCESS MEMORY 有权
标题翻译：在非易失性随机访问存储器中复位电流传输
公开(公告)号：US20160358652A1
公开(公告)日：2016-12-08
申请号：US14731212
申请日：2015-06-04
申请人： Intel Corporation
发明人： Sandeep K. Guliani , Ved Pragyan
IPC分类号： G11C13/00 , G06F12/08
CPC分类号： G11C13/0097 , G06F12/0891 , G11C13/0004 , G11C13/0028 , G11C13/0038 , G11C2013/009 , G11C2013/0092 , G11C2213/76
摘要： Embodiments of the present disclosure describe techniques and configurations for providing a reset current to a non-volatile random access memory (NVRAM), such as a phase change memory (PCM) device. In an embodiment, the apparatus may comprise an NVRAM device; a selection mirror circuit coupled with the NVRAM device to apply a selection mirror voltage to the NVRAM device, to select a memory cell of the NVRAM device; and a reset mirror circuit coupled with the NVRAM device to apply a reset mirror voltage to the memory cell of the NVRAM device, subsequent to the application of the selection mirror voltage, to reset the memory cell. The reset mirror voltage may be lower than the selection mirror voltage, to facilitate delivery of a reset current above a current threshold to the memory cell. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了用于向诸如相变存储器（PCM）设备的非易失性随机存取存储器（NVRAM）提供复位电流的技术和配置。在一个实施例中，该装置可以包括NVRAM装置; 与NVRAM器件耦合以将选择镜电压施加到NVRAM器件的选择镜电路，以选择NVRAM器件的存储器单元; 以及与NVRAM器件耦合的复位镜电路，以在施加选择镜电压之后将复位镜电压施加到NVRAM器件的存储单元，以复位存储器单元。复位镜电压可以低于选择镜电压，以便于将高于电流阈值的复位电流传送到存储器单元。可以描述和/或要求保护其他实施例。

49. 发明申请

US20160358650A1 MULTI-FUNCTION RESISTANCE CHANGE MEMORY CELLS AND APPARATUSES INCLUDING THE SAME 有权
公开(公告)号：US20160358650A1
公开(公告)日：2016-12-08
申请号：US15237248
申请日：2016-08-15
申请人： Micron Technology, Inc.
发明人： Scott E. Sills
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C11/005 , G11C11/5685 , G11C13/0002 , G11C13/0011 , G11C13/0023 , G11C13/003 , G11C13/0033 , G11C13/0038 , G11C13/004 , G11C14/00 , G11C2013/0078 , G11C2013/0083 , G11C2013/0092
摘要： Various embodiments comprise apparatuses having a number of memory cells including drive circuitry to provide signal pulses of a selected time duration and/or amplitude, and an array of resistance change memory cells electrically coupled to the drive circuitry. The resistance change memory cells may be programmed for a range of retention time periods and operating speeds based on the received signal pulse. Additional apparatuses and methods are described.

50. 发明申请

US20160314835A1 ELECTRONIC DEVICE AND METHOD FOR OPERATING ELECTRONIC DEVICE 有权
标题翻译：电子设备和操作电子设备的方法
公开(公告)号：US20160314835A1
公开(公告)日：2016-10-27
申请号：US15203716
申请日：2016-07-06
申请人： SK hynix Inc.
发明人： Mi-Jung Kim
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C29/021 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C2013/0047 , G11C2013/0052 , G11C2013/0092
摘要： An electronic device comprising a semiconductor memory unit that may a variable resistance element configured to be changed in its resistance value in response to current flowing through both ends thereof; an information storage unit configured to store switching frequency information corresponding to a switching frequency which minimizes an amplitude of a voltage to be applied to both ends of the variable resistance element to change the resistance value of the variable resistance element and switching amplitude information corresponding to a minimum amplitude; and a driving unit configured to generate a driving voltage with the switching frequency and the minimum amplitude in response to the switching frequency information and the switching amplitude information and apply the driving voltage to both ends of the variable resistance element.
摘要翻译：一种电子设备，包括：半导体存储单元，其可变电阻元件被配置为响应于流过其两端的电流而改变其电阻值; 信息存储单元，被配置为存储对应于切换频率的开关频率信息，所述开关频率使施加到所述可变电阻元件的两端的电压的幅度最小化，以改变所述可变电阻元件的电阻值，并且切换对应于最小幅度以及驱动单元，被配置为响应于开关频率信息和开关振幅信息产生具有开关频率和最小振幅的驱动电压，并将驱动电压施加到可变电阻元件的两端。

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