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41. 发明授权

US07620803B2 Data processing device and electronic equipment using pipeline control 失效
标题翻译：数据处理装置和电子设备采用管道控制
公开(公告)号：US07620803B2
公开(公告)日：2009-11-17
申请号：US10601005
申请日：2003-06-20
申请人： Makoto Kudo
发明人： Makoto Kudo
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00 , G06F9/30 , G06F9/40
CPC分类号： G06F9/3806 , G06F9/325 , G06F9/3842
摘要： A data processing device is provided using pipeline architecture to reduce a time loss due to a branch without causing an increase in circuit scale. The data processing device uses pipeline control. The data processing device includes an instruction queue in which a plurality of instruction codes can be fetched, a fetch address operation circuit which calculates a fetch address, a fetch circuit which fetches an instruction code based on the fetch address, and a branch information setting circuit which decodes a branch setting instruction, stores a branch address in a branch address storage register, and stores a branch target address in a branch target address storage register. The fetch address operation circuit compares either a previous fetch address or an expected next fetch address with a value stored in the branch address storage register, and determines a next fetch address to be output, based on the comparison result.
摘要翻译：使用流水线架构提供数据处理装置，以减少由于分支引起的时间损失而不引起电路规模的增加。数据处理设备使用流水线控制。数据处理装置包括可以取出多个指令代码的指令队列，计算取出地址的取出地址运算电路，基于取出地址取出指令代码的取出电路以及分支信息设定电路解码分支设置指令，将分支地址存储在分支地址存储寄存器中，并将分支目标地址存储在分支目标地址存储寄存器中。提取地址操作电路将先前的取出地址或预期的下一个取出地址与存储在分支地址存储寄存器中的值进行比较，并且基于比较结果确定要输出的下一个提取地址。

42. 发明申请

US20090240928A1 CHANGE IN INSTRUCTION BEHAVIOR WITHIN CODE BLOCK BASED ON PROGRAM ACTION EXTERNAL THERETO 审中-公开
标题翻译：根据程序动作外部指令改变代码块中的指令行为
公开(公告)号：US20090240928A1
公开(公告)日：2009-09-24
申请号：US12050622
申请日：2008-03-18
申请人： Michael A. Fischer , Wesley D. Hardell
发明人： Michael A. Fischer , Wesley D. Hardell
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/325 , G06F9/462
摘要： Extended, alternate and/or modified instruction behavior can be established using a program construct that appears outside a bounded block of program code in such a way that the behavioral changes are limited to the bounded block and coincide with a particular point in the execution thereof. These extensions, alternations and/or modifications are supported in some processor embodiments in ways that add neither additional code space nor additional execution cycles to the bounded block. In general, the particular point in execution of the bounded block may be specified in a variety of ways, including positionally or temporally. Techniques described herein have broad applicability, but will be understood by persons of ordinary skill in the art in the context of certain illustrative code blocks, including zero- (or low-) overhead loops, lightweight procedures and very long instruction word (VLIW) type instruction packets, and processors that support them.
摘要翻译：可以使用出现在有界程序代码块之外的程序结构来建立扩展的，交替的和/或修改的指令行为，使得行为改变被限制到有界块并且与其执行中的特定点一致。这些扩展，替换和/或修改在一些处理器实施例中以不增加附加代码空间和附加执行周期添加到有界块的方式得到支持。通常，有界块的执行中的特定点可以以各种方式来指定，包括位置或时间上。本文描述的技术具有广泛的适用性，但是在某些说明性代码块的上下文中，本领域普通技术人员将会理解，包括零（或低）开销循环，轻量级程序和非常长的指令字（VLIW）类型指令包和支持它们的处理器。

43. 发明授权

US07532722B2 Apparatus and method for performing transparent block cipher cryptographic functions 有权
标题翻译：用于执行透明块密码加密功能的装置和方法
公开(公告)号：US07532722B2
公开(公告)日：2009-05-12
申请号：US10727973
申请日：2003-12-04
申请人： Thomas A. Crispin , G. Glenn Henry , Arturo Martin-de-Nicolas , Terry Parks
发明人： Thomas A. Crispin , G. Glenn Henry , Arturo Martin-de-Nicolas , Terry Parks
IPC分类号： H04L9/00
CPC分类号： G06F9/3001 , G06F9/30007 , G06F9/30043 , G06F9/3017 , G06F9/30178 , G06F9/325 , G06F9/3885 , G06F21/72 , H04L9/0631 , H04L9/0637 , H04L2209/125 , H04L2209/24
摘要： The present invention provides an apparatus and method for performing cryptographic operations on a plurality of input data blocks within a processor. In one embodiment, an apparatus for performing cryptographic operations is provided. The apparatus includes a cryptographic instruction and execution logic. The cryptographic instruction is received by a computing device as part of an instruction flow executing on the computing device, wherein the cryptographic instruction prescribes one of the cryptographic operations. The execution logic is operatively coupled to the cryptographic instruction and executes the one of the cryptographic operations. The one of the cryptographic operations includes indicating whether the one of the cryptographic operations has been interrupted by an interrupting event.
摘要翻译：本发明提供一种用于对处理器内的多个输入数据块执行密码操作的装置和方法。在一个实施例中，提供了一种用于执行密码操作的装置。该装置包括密码指令和执行逻辑。密码指令由计算设备接收，作为在计算设备上执行的指令流的一部分，其中密码指令规定了一个密码操作。执行逻辑可操作地耦合到密码指令，并执行加密操作之一。加密操作之一包括指示密码操作中的一个是否已被中断事件中断。

44. 发明申请

US20090070557A1 PARALLEL PROGRAM EXECUTION OF COMMAND BLOCKS USING FIXED BACKJUMP ADDRESSES 审中-公开
标题翻译：使用固定的后座地址进行并行程序执行命令块
公开(公告)号：US20090070557A1
公开(公告)日：2009-03-12
申请号：US12256236
申请日：2008-10-22
申请人： Helge Betzinger
发明人： Helge Betzinger
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/325 , G06F9/30072 , G06F9/3836
摘要： The invention relates to a method for executing instructions in a processor, according to which an instruction to be executed of a program memory is addressed by a program control unit by means of a program counter reading of a program counter that operates in said unit. The addressed instruction is then read out, decoded and executed by the program control unit. The program control unit additionally stores the current program counter reading and the number of successive instructions when a jump instruction occurs in the form of a block instruction, according to which a specific number of instructions are to be executed successively, thus defining the return address after execution. After the last instruction of the instruction block to be executed, the program counter resumes the counting operation from the stored program counter reading.
摘要翻译：本发明涉及一种用于在处理器中执行指令的方法，根据该方法，由程序控制单元通过在所述单元中操作的程序计数器的程序计数器读取来对程序存储器执行的指令进行寻址。寻址指令然后由程序控制单元读出，解码和执行。程序控制单元另外存储当前程序计数器读取和当以块指令的形式发生跳转指令时的连续指令的数目，根据该程序指令将依次执行特定数量的指令，从而定义返回地址执行。在执行指令块的最后一条指令之后，程序计数器从存储的程序计数器读数中恢复计数操作。

45. 发明申请

US20090055589A1 Cache memory system for a data processing apparatus 审中-公开
标题翻译：用于数据处理装置的高速缓冲存储器系统
公开(公告)号：US20090055589A1
公开(公告)日：2009-02-26
申请号：US11892667
申请日：2007-08-24
申请人： Daren Croxford , Timothy Fawcett Milner
发明人： Daren Croxford , Timothy Fawcett Milner
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F9/325 , G06F9/381 , G06F9/3844 , G06F12/0897 , G06F2212/1028 , Y02D10/13
摘要： A data processing apparatus is provided having a cache memory 262, 264, a cache controller 240 and a location-specifying memory 252. The location-specifying memory is configured to store mapping data providing a mapping between a given memory address and a storage location in the cache. The stored mapping data is used instead of performing a cache look up to access the information corresponding to the given memory address in the cache memory. Furthermore, a data processing apparatus is provided having a pipelined processing circuit 220, a cache memory 262, 264, loop detection circuitry, branch prediction circuitry 232 and control circuitry 240. The branch prediction circuitry is configured to generate branch prediction information, which is used by the control circuitry to control which program instructions of detected program loops are stored by the buffer memory.
摘要翻译：提供了具有高速缓冲存储器262,264，高速缓存控制器240和位置指定存储器252的数据处理装置。位置指定存储器被配置为存储提供给定存储器地址和存储位置之间的映射的映射数据缓存。使用所存储的映射数据而不是执行高速缓存查找以访问与高速缓冲存储器中的给定存储器地址相对应的信息。此外，提供了具有流水线处理电路220，高速缓冲存储器262,264，环路检测电路，分支预测电路232和控制电路240的数据处理装置。分支预测电路被配置为生成分支预测信息，其被使用由控制电路控制由缓冲存储器存储检测到的程序循环的哪些程序指令。

46. 发明申请

US20080263115A1 Very long arithmetic logic unit for security processor 审中-公开
标题翻译：用于安全处理器的非常长的算术逻辑单元
公开(公告)号：US20080263115A1
公开(公告)日：2008-10-23
申请号：US11785363
申请日：2007-04-17
申请人： Tomer Y. Morad , Ami Hazbany
发明人： Tomer Y. Morad , Ami Hazbany
IPC分类号： G06F7/575 , G06F7/38
CPC分类号： G06F9/30014 , G06F9/30101 , G06F9/325
摘要： An arithmetic and logic unit carries out arithmetic or logic operations on long operands. The unit comprises: an operation unit having a processing location, and configured for carrying out processing on bits at the processing location, the processing comprising any of a plurality of pre-defined arithmetic or logical operations, the processes being defined for a first number of bits determined by the operand word length; a fetch and write unit comprising direct memory access circuitry for fetching a second number of bits of operand data by direct access from an external memory and for writing results to memory, the second number being set by a predetermined memory access width; the second number being smaller than said operand word length, and the direct memory access circuitry being configured to deliver said second number of bits directly to the processing location without aggregation prior to processing. The fetch and write unit is controllable to carry out fetch operations for a further second number of bits of the long operand while a current part of the operand is being processed in said operation unit, thereby to hide memory access latency.
摘要翻译：算术和逻辑单元对长操作数执行算术或逻辑运算。该单元包括：具有处理位置并被配置为对处理位置处的位进行处理的操作单元，该处理包括多个预定义的算术或逻辑操作中的任何一个，该处理被定义为第一数量的由操作数字长度确定的位; 获取和写入单元，其包括直接存储器访问电路，用于通过从外部存储器的直接访问获取第二数量的操作数数据位，并将结果写入存储器，第二数量由预定存储器存取宽度设置; 所述第二数量小于所述操作数字长度，并且所述直接存储器存取电路被配置为在处理之前将所述第二数量位直接传送到所述处理位置而不进行聚合。读取和写入单元是可控的，以在操作数的当前部分在所述操作单元中被处理的同时，对长操作数的另外的第二数目的位执行取指操作，从而隐藏存储器访问等待时间。

47. 发明申请

US20080195851A1 Multi-Threaded Processor 有权
标题翻译：多线程处理器
公开(公告)号：US20080195851A1
公开(公告)日：2008-08-14
申请号：US11814801
申请日：2006-01-17
申请人： Jan Hoogerbrugge
发明人： Jan Hoogerbrugge
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/325
摘要： A multi-threaded processor comprises a processing unit (PU) for concurrently processing multiple threads. A register file means (RF) is provided having a plurality of registers, wherein a first register (LI) is used for storing loop invariant values and N second registers (LVI-LVN) are each used for storing loop variant values. Furthermore N program counters (PCI-PCN) are provided each being associated to one of the multiple threads, wherein N being the number of threads being processed.
摘要翻译：多线程处理器包括用于同时处理多个线程的处理单元（PU）。提供具有多个寄存器的寄存器文件装置（RF），其中第一寄存器（LI）用于存储循环不变值，并且N个第二寄存器（LVI-LVN）分别用于存储循环变量值。此外，提供N个程序计数器（PCI-PCN），每个程序计数器（PCI-PCN）与多个线程中的一个相关联，其中N是被处理的线程数。

48. 发明申请

US20080155237A1 System and method for implementing and utilizing a zero overhead loop 有权
标题翻译：用于实现和利用零开销循环的系统和方法
公开(公告)号：US20080155237A1
公开(公告)日：2008-06-26
申请号：US11644000
申请日：2006-12-22
申请人： Timothy Martin Dobson , Mark Taunton
发明人： Timothy Martin Dobson , Mark Taunton
IPC分类号： G06F9/28
CPC分类号： G06F9/325 , G06F9/381 , G06F9/3851
摘要： A system and method for implementing a zero overhead loop in a microprocessor or microprocessor based system/chip.
摘要翻译：一种用于在微处理器或基于微处理器的系统/芯片中实现零开销环路的系统和方法。

49. 发明申请

US20080155236A1 System and method for implementing a zero overhead loop 有权
标题翻译：用于实现零开销循环的系统和方法
公开(公告)号：US20080155236A1
公开(公告)日：2008-06-26
申请号：US11643998
申请日：2006-12-22
申请人： Sophie Mary Wilson , Timothy Martin Dobson
发明人： Sophie Mary Wilson , Timothy Martin Dobson
IPC分类号： G06F9/30
CPC分类号： G06F9/325 , G06F9/381 , G06F11/36
摘要： A system and method for implementing a zero overhead loop in a microprocessor or microprocessor based system/chip.
摘要翻译：一种用于在微处理器或基于微处理器的系统/芯片中实现零开销环路的系统和方法。

50. 发明申请

US20080109646A1 DATA PROCESSING APPARATUS FOR LOOP STRUCTURE AND METHOD THEREOF 审中-公开
标题翻译：环路结构的数据处理装置及其方法
公开(公告)号：US20080109646A1
公开(公告)日：2008-05-08
申请号：US11624222
申请日：2007-01-18
申请人： Ching-Min Hou , Kung-Hsien Chu
发明人： Ching-Min Hou , Kung-Hsien Chu
IPC分类号： G06F9/38
CPC分类号： G06F9/381 , G06F9/325
摘要： A data processing apparatus for loop structure is provided. The apparatus includes a fast memory device and a loop detector. The loop detector is coupled to a processor to detect whether the processor performs a loop structure or not. When the processor performs the loop structure, the loop detector outputs a control signal. According to the control signal, the apparatus stores a loop structure data corresponding to the loop structure in the fast memory device for the processor to perform the loop structure.
摘要翻译：提供一种用于环路结构的数据处理装置。该装置包括快速存储装置和环路检测器。环路检测器耦合到处理器以检测处理器是否执行环路结构。当处理器执行环路结构时，环路检测器输出一个控制信号。根据控制信号，该设备将与循环结构相对应的循环结构数据存储在快速存储器件中用于处理器执行循环结构。

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