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41. 发明授权

US4979018A Semiconductor device with parallel multiplier using at least three wiring layers 失效
标题翻译：具有并联乘法器的半导体器件使用至少三个布线层
公开(公告)号：US4979018A
公开(公告)日：1990-12-18
申请号：US407152
申请日：1989-09-14
申请人： Shigeru Tanaka
发明人： Shigeru Tanaka
IPC分类号： G06F7/53 , G06F7/52 , H01L21/3205 , H01L21/822 , H01L23/52 , H01L27/04
CPC分类号： G06F7/533 , G06F2207/4802
摘要： In a semiconductor device of the present invention, partial products of a multiplicand and a specific bit of a multiplier are formed by a plurality of partial product producing circuits. The results of multiplication obtained from the partial product producing circuits are output to one of full adders serving as first partial sum producing circuits through a first connection wire formed of a first metal wiring layer and a second metal wiring layer formed above the first layer. In the first full adders, specific bits of the partial product producing circuits are grouped for addition. The result of this addition is output to a second full adder through a second connection wire formed of a third metal wiring layer formed above the second layer. In the second full adder, the results of addition obtained from the first full adders are added together, and then the result obtained from the second full adder is output to other full adders and a final full adder to obtain the product of the multiplicand and the multiplier.
摘要翻译：在本发明的半导体器件中，通过多个部分积产生电路形成乘法器的乘法器和特定位的部分积。通过由形成在第一层上的第一金属布线层和第二金属布线层形成的第一连接线，将从部分积产生电路获得的相乘结果输出到用作第一部分和产生电路的全加法器之一。在第一个全加法器中，部分乘积生成电路的特定位被分组以进行加法。该添加的结果通过由形成在第二层上方的第三金属布线层形成的第二连接线输出到第二全加器。在第二个全加器中，将从第一个全加法器获得的相加结果相加在一起，然后从第二个全加器得到的结果输出到其他全加器，最终的全加法器得到被乘数乘积乘数。

42. 发明授权

US4075704A Floating point data processor for high speech operation 失效
标题翻译：浮动点数据处理器，用于高语音操作
公开(公告)号：US4075704A
公开(公告)日：1978-02-21
申请号：US702148
申请日：1976-07-02
申请人： George P. O'Leary
发明人： George P. O'Leary
IPC分类号： G06F7/00 , G06F7/50 , G06F7/52 , G06F7/57 , G06F7/76 , G06F9/38 , G06F7/38
CPC分类号： G06F7/5312 , G06F7/483 , G06F7/485 , G06F7/4876 , G06F7/533 , G06F9/3879 , G06F2207/3884 , G06F2207/3896 , G06F7/49936 , G06F7/49947
摘要： A digital data processor includes a plurality of memory registers, a floating point adder and a floating point multiplier intercoupled by a plurality of simultaneously operable parallel buses facilitating multiple parallel operations during one clock cycle or instruction. The floating adder and multiplier each include a number of stages separated by intermediate temporary storage registers which receive the partial results of a computation for use by the next stage during the next clock period. Floating point additions, multiplications and other arithmetic and logical results are produced during each clock cycle.

43. 发明授权

US09503747B2 Threshold filtering of compressed domain data using steering vector 有权
标题翻译：使用导向矢量对压缩域数据进行阈值滤波
公开(公告)号：US09503747B2
公开(公告)日：2016-11-22
申请号：US14607113
申请日：2015-01-28
申请人： Intel Corporation
发明人： Sudhir K. Satpathy , Sanu K. Mathew , Ram K. Krishnamurthy
IPC分类号： G06F7/544 , H04N19/48 , G06F7/24 , G06T7/00 , H04N19/85
CPC分类号： G06F7/533 , G06F7/24 , G06F7/5443 , G06T7/74 , G06T7/97 , H04N19/48 , H04N19/85
摘要： In an embodiment, a processor includes a compression domain threshold filter coupled to a plurality of cores. The compression domain threshold filter is to: receive a sample vector of compressed data to be filtered; calculate, based at least on a first subset of the elements of the sample vector, an estimated upper bound value of a dot product of the sample vector and a steering vector; determine whether the estimated upper bound value of the dot product satisfies a filter threshold value; and in response to a determination that the estimated upper bound value of the dot product does not satisfy the filter threshold value, discard the sample vector without completion of a calculation of the dot product of the sample vector and the steering vector. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括耦合到多个核的压缩域阈值滤波器。压缩域阈值滤波器是：接收要滤波的压缩数据的采样向量; 至少基于样本矢量的元素的第一子集计算样本矢量和导向矢量的点积的估计上限值; 确定点积的估计上限值是否满足滤波器阈值; 并且响应于确定点积的估计上限值不满足滤波器阈值，而不完成样本矢量和导向矢量的点乘积的计算而丢弃样本矢量。描述和要求保护其他实施例。

44. 发明授权

US09465579B2 Variable-latency speculating pipelined booth multiplier with statistical carry estimation for error detection and recovery 有权
标题翻译：可变延迟推测流水线展位乘数，具有用于错误检测和恢复的统计进位估计
公开(公告)号：US09465579B2
公开(公告)日：2016-10-11
申请号：US14204133
申请日：2014-03-11
申请人： National Chiao Tung University
发明人： Chih-Wei Liu , Shin-Kai Chen , Kuo-Chiang Chang , Tsung-Yi Wu , An-Chi Tsai
IPC分类号： G06F7/52 , G06F7/533
CPC分类号： G06F7/533
摘要： Provided is a method for processing pipelined data using a variable-latency speculating booth multiplier (VLSBM), including a first operation and a second operation. The first operation has the steps of partitioning partial products into a least significant part (LSP) and a most significant part (MSP), estimating a carry of the LSP, computing the MSP based on the estimated carry, computing the LSP independently to obtain a true carry and detecting a computation error by comparing the estimated carry with the true carry. Also, the second operation has the step of correcting the computation error based on the difference between the estimated carry and the true carry. Further, a VLSBM for processing pipelined data is also provided.
摘要翻译：提供了一种使用可变延迟推测展位乘数（VLSBM）处理流水线数据的方法，包括第一操作和第二操作。第一操作具有将部分产品划分为最不重要部分（LSP）和最重要部分（MSP）的步骤，估计LSP的进位，基于估计的进位计算MSP，独立地计算LSP以获得通过将估计的进位与真实进位进行比较来真实携带并检测计算误差。此外，第二操作具有基于估计的进位和真实进位之间的差来校正计算误差的步骤。此外，还提供了用于处理流水线数据的VLSBM。

45. 发明授权

US07912891B2 High speed low power fixed-point multiplier and method thereof 失效
标题翻译：高速低功率定点倍增器及其方法
公开(公告)号：US07912891B2
公开(公告)日：2011-03-22
申请号：US11636242
申请日：2006-12-08
申请人： Sang-In Cho , Cheol-Ho Shin , Kyu-Min Kang , Sung-Woo Choi , Sang-Sung Choi , Jin-Gyun Chung , Yong-Eun Kim
发明人： Sang-In Cho , Cheol-Ho Shin , Kyu-Min Kang , Sung-Woo Choi , Sang-Sung Choi , Jin-Gyun Chung , Yong-Eun Kim
IPC分类号： G06F7/52
CPC分类号： G06F7/533
摘要： Provided are a high speed and low power fixed-point multiplier and method thereof. The multiplier includes: a partial product calculation unit for dividing input data into a plurality of bit groups, each bit group having a predetermined number of bits, generating partial products by independently multiplying a fixed coefficient for each bit group, and summing partial products included in a corresponding bit group, to thereby generate a summed partial products; and an adding unit for adding the summed partial products of each bit group generated from the partial product calculation unit.
摘要翻译：提供了一种高速和低功率定点倍增器及其方法。乘法器包括：部分乘积计算单元，用于将输入数据分成多个比特组，每个比特组具有预定数量的比特，通过独立地乘以每个比特组的固定系数产生部分乘积，并将包括在相应的位组，从而产生相加的部分积; 以及添加单元，用于添加从所述部分乘积计算单元生成的每个位组的相加的部分乘积。

46. 发明申请

US20090228540A1 FILTER OPERATION UNIT AND MOTION-COMPENSATING DEVICE 有权
标题翻译：过滤器操作单元和运动补偿装置
公开(公告)号：US20090228540A1
公开(公告)日：2009-09-10
申请号：US12392755
申请日：2009-02-25
申请人： Yoichi KATAYAMA
发明人： Yoichi KATAYAMA
IPC分类号： G06F7/533
CPC分类号： G06F7/533 , G06F7/5338 , H04N19/436
摘要： A multiplier includes an operation unit that adds or subtracts a first group selected from a current input data, and a second group selected from a next input data corresponding to the first group to generate an operation result, a Booth's encoder that encodes the operation result according to Booth's algorithm, and generates code data, a partial product generation unit that calculates a partial product from the code data as a first partial product, and calculates, in a case where the first group and the second group are specific combination, a second partial product, and an adder that cumulatively adds an output from the partial product generation unit. The specific combination is a combination in which the highest-order bit of each of the first group and the second group is the same value, and the third least significant bit obtained after the subtraction operation is 1.
摘要翻译：乘法器包括：加法或减法从当前输入数据中选择的第一组的操作单元和从与第一组相对应的下一个输入数据中选择的第二组以产生运算结果;布斯编码器，根据并且生成代码数据，部分乘积生成单元，其从代码数据计算作为第一部分乘积的部分乘积，并且在第一组和第二组是特定组合的情况下，计算第二部分乘积和累积地从部分乘积生成单元输出的加法器。特定组合是第一组和第二组中的每一个的最高位是相同值的组合，并且在减法运算之后获得的第三最低有效位是1。

47. 发明申请

US20090063599A1 FAST COMPUTATION OF PRODUCTS BY DYADIC FRACTIONS WITH SIGN-SYMMETRIC ROUNDING ERRORS 有权
标题翻译：通过具有符号对称错误的DYADIC分段快速计算产品
公开(公告)号：US20090063599A1
公开(公告)日：2009-03-05
申请号：US12139957
申请日：2008-06-16
申请人： Yuriy Reznik
发明人： Yuriy Reznik
IPC分类号： G06F7/485 , G06F17/10
CPC分类号： G06F7/483 , G06F7/49942 , G06F7/533 , G06F17/147 , H04N19/42 , H04N19/60
摘要： A product of an integer value and an irrational value may be determined by a sign-symmetric algorithm. A process may determine possible algorithms that minimize metrics such as mean asymmetry, mean error, variance of error, and magnitude of error. Given an integer variable x and rational dyadic constants that approximate the irrational fraction, a series of intermediate values may be produced that are sign-symmetric. The intermediate values may include a sequence of addition, subtraction and right shift operations the when summed together approximate the product of the integer and irrational value. Other operations, such as additions or subtractions of 0s or shifts by 0 bits may be removed.
摘要翻译：可以通过符号对称算法来确定整数值和非理性值的乘积。过程可以确定最小化度量的可能算法，例如平均不对称性，平均误差，误差方差和误差大小。给定一个整数变量x和近似非理性分数的有理二元常数，可以产生一系列中间值，这些中间值是符号对称的。中间值可以包括加法，减法和右移操作的序列，当加在一起近似整数和非理性值的乘积时。可以删除其他操作，例如0的加法或减法或0位的移位。

48. 发明授权

US07272624B2 Fused booth encoder multiplexer 失效
标题翻译：熔模展位编码器多路复用器
公开(公告)号：US07272624B2
公开(公告)日：2007-09-18
申请号：US10675674
申请日：2003-09-30
申请人： Wendy Ann Belluomini , Hung Cai Ngo , Jun Sawada
发明人： Wendy Ann Belluomini , Hung Cai Ngo , Jun Sawada
IPC分类号： G06F7/52
CPC分类号： G06F7/5338 , G06F7/483 , G06F7/533 , G06F7/5443 , G06F2207/3872
摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.
摘要翻译：乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器，在输出节点维护该值。编码器选择器单元并行操作以通常同时产生部分乘积位。编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。

49. 发明申请

US20070180015A1 High speed low power fixed-point multiplier and method thereof 失效
标题翻译：高速低功率定点倍增器及其方法
公开(公告)号：US20070180015A1
公开(公告)日：2007-08-02
申请号：US11636242
申请日：2006-12-08
申请人： Sang-In Cho , Cheol-Ho Shin , Kyu-Min Kang , Sung-Woo Choi , Sang-Sung Choi , Jin-Gyun Chung , Yong-Eun Kim
发明人： Sang-In Cho , Cheol-Ho Shin , Kyu-Min Kang , Sung-Woo Choi , Sang-Sung Choi , Jin-Gyun Chung , Yong-Eun Kim
IPC分类号： G06F7/52
CPC分类号： G06F7/533
摘要： Provided are a high speed and low power fixed-point multiplier and method thereof. The multiplier includes: a partial product calculation unit for dividing input data into a plurality of bit groups, each bit group having a predetermined number of bits, generating partial products by independently multiplying a fixed coefficient for each bit group, and summing partial products included in a corresponding bit group, to thereby generate a summed partial products; and an adding unit for adding the summed partial products of each bit group generated from the partial product calculation unit.
摘要翻译：提供了一种高速和低功率定点倍增器及其方法。乘法器包括：部分乘积计算单元，用于将输入数据分成多个比特组，每个比特组具有预定数量的比特，通过独立地乘以每个比特组的固定系数产生部分乘积，并将包括在相应的位组，从而产生相加的部分积; 以及添加单元，用于添加从所述部分乘积计算单元生成的每个位组的相加的部分乘积。

50. 发明授权

US07177894B2 Switching activity reduced coding for low-power digital signal processing circuitry 失效
标题翻译：开关活动减少了低功耗数字信号处理电路的编码
公开(公告)号：US07177894B2
公开(公告)日：2007-02-13
申请号：US10650641
申请日：2003-08-28
申请人： Christian Lutkemeyer
发明人： Christian Lutkemeyer
IPC分类号： G06F7/52
CPC分类号： G06F7/533 , G06F7/5336 , H03H17/0236 , H03H2017/0692
摘要： A system and method for reducing power consumption in digital circuitry by reducing the amount of unnecessary switching in such circuitry. An aspect of the present invention provides a switching-reduction circuit that outputs a signal to a subsequent digital circuit. The value of the signal may depend on the relevance of the signal value to a next output of the subsequent digital circuit. A method according to various aspects of the present invention includes receiving a next input signal. The method further includes determining whether the next input signal may be relevant to a next output of a subsequent digital circuit. The method further includes providing the next input signal to the subsequent digital circuit when the next input signal may be relevant to the next output of the subsequent digital circuit, and providing a previous signal to the subsequent digital circuit when the next input signal will not be relevant to the next output of the subsequent digital circuit.
摘要翻译：一种通过减少这种电路中不必要的切换量来减少数字电路中的功耗的系统和方法。本发明的一个方面提供一种将信号输出到随后的数字电路的开关降低电路。信号的值可以取决于信号值与后续数字电路的下一个输出的相关性。根据本发明的各个方面的方法包括接收下一个输入信号。该方法还包括确定下一个输入信号是否可能与随后数字电路的下一个输出有关。该方法还包括当下一个输入信号可能与随后的数字电路的下一个输出相关时，向随后的数字电路提供下一个输入信号，并且当下一个输入信号不会与后续数字电路的下一个输出相关。

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