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41. 发明申请

US20080010333A1 FUSED BOOTH ENCODER MULTIPLEXER 审中-公开
标题翻译： FUSED BOOTH编码器多路复用器
公开(公告)号：US20080010333A1
公开(公告)日：2008-01-10
申请号：US11776454
申请日：2007-07-11
申请人： Wendy Belluomini , Hung Ngo , Jun Sawada
发明人： Wendy Belluomini , Hung Ngo , Jun Sawada
IPC分类号： G06F7/52
CPC分类号： G06F7/5338 , G06F7/483 , G06F7/533 , G06F7/5443 , G06F2207/3872
摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.
摘要翻译：乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器，在输出节点维护该值。编码器选择器单元并行操作以通常同时产生部分乘积位。编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。

42. 发明申请

US20070244954A1 FUSED BOOTH ENCODER MULTIPLEXER 失效
标题翻译： FUSED BOOTH编码器多路复用器
公开(公告)号：US20070244954A1
公开(公告)日：2007-10-18
申请号：US11670357
申请日：2007-02-01
申请人： Wendy Belluomini , Hung Ngo , Jun Sawada
发明人： Wendy Belluomini , Hung Ngo , Jun Sawada
IPC分类号： G06F7/52
CPC分类号： G06F7/5338 , G06F7/483 , G06F7/533 , G06F7/5443 , G06F2207/3872
摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit. The fused Booth encoder multiplexer unit, tree unit and adder unit function in a pipeline manner with the units operating on sequential data sets during a given processing cycle. The fused Booth encoder multiplexer unit may be advantageously laid out in a design of an integrated circuit chip with no gap present in the layout, which allows uniform wire length and avoids the necessity of large transistors to drive long interconnection wires.
摘要翻译：乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器，在输出节点维护该值。编码器选择器单元并行操作以通常同时产生部分乘积位。编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。融合的布尔编码器多路复用器单元，树形单元和加法器单元在给定的处理周期内以流水线方式与在顺序数据集上操作的单元进行功能。融合布尔编码器多路复用器单元可有利地布置在集成电路芯片的设计中，布局中不存在间隙，这允许均匀的导线长度，并避免了大晶体管驱动长互连线的必要性。

43. 发明申请

US20040153489A1 Multiply execution unit for preforming integer and XOR multiplication 有权
标题翻译：乘以执行单元进行整数和XOR乘法
公开(公告)号：US20040153489A1
公开(公告)日：2004-08-05
申请号：US10354354
申请日：2003-01-30
发明人： Leonard D. Rarick , Sheueling Chang Shantz , Shreyas Sundaram
IPC分类号： G06F009/44
CPC分类号： G06F7/724 , G06F7/533
摘要： A multiply execution unit that is operable to generate the integer product and the XOR product of a multiplicand and a multiplier. The multiply execution unit includes a summing circuit for summing a plurality of partial products. The partial products may be Booth encoded. The summing circuit can generate an integer sum of the plurality of partial products and can generate an XOR sum of the plurality of partial products. The summing circuit includes a first plurality of full adders. The first plurality of full adders each has three inputs, a carry output, and a sum output. The sum outputs of the first plurality of full adders are independent of the value of any carry output in the summing circuit. The summing circuit also includes a second plurality of full adders. The second plurality of full adders each has three inputs, a carry output, and a sum output. The XOR sum is dependent upon at least one of the sum outputs of the first plurality of full adders but is independent of the sum outputs of the second plurality of full adders. The integer sum is dependent upon the sum outputs of at least one of the first plurality of full adders and is also dependent on at least one of the sum outputs of the second plurality of full adders.
摘要翻译：乘法执行单元，其可操作以生成乘积和乘法器和乘法器的XOR乘积。乘法执行单元包括用于求和多个部分乘积的求和电路。部分产品可能是布斯编码的。求和电路可以生成多个部分乘积的整数，并且可以产生多个部分乘积的XOR和。求和电路包括第一多个完全加法器。第一组多个全加器各有三个输入，一个进位输出和一个和输出。第一多个完全加法器的和输出与求和电路中的任何进位输出的值无关。求和电路还包括第二多个完全加法器。第二组多个全加器各具有三个输入，一个进位输出和一个和输出。 XOR和取决于第一多个完全加法器的和输出中的至少一个，但是与第二多个完全加法器的和输出无关。整数和取决于第一多个全加法器中的至少一个的总和输出，并且还取决于第二多个全加器的和输出中的至少一个。

44. 发明授权

US5974435A Reconfigurable arithmetic datapath 失效
标题翻译：可重构算术数据路径
公开(公告)号：US5974435A
公开(公告)日：1999-10-26
申请号：US953766
申请日：1997-10-17
申请人： Curtis Abbott
发明人： Curtis Abbott
IPC分类号： G06F7/52 , G06F7/533 , G06F7/544
CPC分类号： G06F7/5324 , G06F7/544 , G06F2207/382 , G06F2207/3828 , G06F2207/3884 , G06F7/533
摘要： A method and apparatus that combines the same basic hardware elements in several ways to perform a plurality of arithmetic operations over different numbers of operands of different lengths. The allowed options include the multiplication and summing of several operands in a single operation. The reuse of hardware elements is obtained by the use of a multiplication hardware structure together with multiplexer logic (or similar selection logic) at appropriate points in the hardware structure, which allows a minimum of extra hardware and a small number of extra gate delays along any critical path, thereby ensuring that the flexibility to use different operand lengths and numbers of operands incurs only a small penalty in processing speed and/or chip area in a VLSI circuit implementation.
摘要翻译：一种方法和装置，其以若干方式组合相同的基本硬件元件以对不同长度的不同数量的操作数执行多个算术运算。允许的选项包括在单个操作中的几个操作数的乘法和求和。通过在硬件结构中的适当点处使用乘法硬件结构与多路复用器逻辑（或类似的选择逻辑）来获得硬件元件的重新使用，其允许沿着任何方式的最小额外的硬件和少量额外的门延迟从而确保使用不同操作数长度和操作数的灵活性在VLSI电路实现中在处理速度和/或芯片面积方面仅产生小的惩罚。

45. 发明授权

US5524090A Apparatus for multiplying long integers 失效
标题翻译：用于乘以长整数的装置
公开(公告)号：US5524090A
公开(公告)日：1996-06-04
申请号：US512620
申请日：1995-08-08
申请人： Keiichi Iwamura
发明人： Keiichi Iwamura
IPC分类号： G06F7/52 , G06F7/72
CPC分类号： G06F7/5324 , G06F7/533 , G06F7/722 , G06F2207/3852 , G06F2207/3892 , G06F7/723
摘要： A multiplier apparatus designed to multiply integers of many figures with a small circuit scale in such a manner that an input value is partitioned and multiplication is performed by taking account of carries. With respect to partitioned input values, partial multiplications are repeatedly performed in parallel with each other, and results of the partial multiplications are added by a plurality of adders. A carry occurring at each adder is added in the same adder or in an upper adder in the next cycle of addition. A circuit for this operation may be formed as a systolic array of identical processing elements to perform the operation in a pipe line processing manner.
摘要翻译：一种乘法器装置，被设计为以一种小的电路规模乘以多个数字的整数，使得输入值被分割并且通过考虑运算来执行乘法。对于分割输入值，部分乘法相互并行重复执行，部分乘法的结果由多个加法器相加。在下一个加法循环中，在相同的加法器或上加法器中，加法出现在每个加法器。用于该操作的电路可以形成为相同处理元件的收缩阵列，以管线处理方式执行操作。

46. 发明授权

US5289399A Multiplier for processing multi-valued data 失效
标题翻译：用于处理多值数据的乘数
公开(公告)号：US5289399A
公开(公告)日：1994-02-22
申请号：US984695
申请日：1992-12-02
申请人： Yukihiro Yoshida
发明人： Yukihiro Yoshida
IPC分类号： G06F7/483 , G06F7/49 , G06F7/506 , G06F7/52 , G06F7/523 , G06F7/527
CPC分类号： G06F7/533 , G06F7/49
摘要： A multiplier, which is capable of processing a multiplication of multi-valued data, includes a register transforming circuit (RC) for shifting data stored and outputting a plurality of data, a multiplying circuit connected to the register transforming circuit (RC) for multiplying the outputs from the register transforming circuit (RC) and an adding circuit connected to the multiplying circuit for adding the multiplied results according to a predetermined arithmetic rule based on logic to be used. The multiplier further includes an AND circuit element connected to the adding circuit for shifting and sending out the outputs from the adding circuit. A W register is connected to the adding circuit for storing the shifted outputs from the adding circuit according to the AND circuit element, and a further AND circuit element is connected to the W register for shifting and sending out the outputs from the W register. Another AND circuit element is connected to the further AND circuit element for further shifting the outputs from the further AND circuit element. Finally, a W register is connected to the further AND circuit element for storing the shifted output from the W register.
摘要翻译：能够处理多值数据相乘的乘法器包括用于移位存储的数据并输出多个数据的寄存器变换电路（RC），连接到寄存器变换电路（RC）的乘法电路，用于将来自寄存器变换电路（RC）的输出和连接到乘法电路的加法电路，用于根据要使用的逻辑的预定算术规则相加乘法结果。乘法器还包括连接到加法电路的AND电路元件，用于从加法电路移出和发出输出。 W寄存器连接到加法电路，用于根据AND电路元件存储来自加法电路的移位输出，另一个AND电路元件连接到W寄存器，用于移位和发送W寄存器的输出。另一AND电路元件连接到另一AND电路元件，用于进一步移位另一AND电路元件的输出。最后，W寄存器连接到另外的AND电路元件，用于存储从W寄存器移位的输出。

47. 发明授权

US5283755A Multiplier employing carry select or carry look-ahead adders in hierarchical tree configuration 失效
标题翻译：乘法器采用进位选择或携带预先加法器在分层树配置
公开(公告)号：US5283755A
公开(公告)日：1994-02-01
申请号：US48396
申请日：1993-04-14
申请人： Roland A. Bechade
发明人： Roland A. Bechade
IPC分类号： G06F7/52
CPC分类号： G06F7/533
摘要： A multiplication circuit for a floating point digital processing system includes a partial products generator and a carry adder circuit for determining a product resulting from multiplication of an M bit multiplicand and an N bit multiplier. The partial products generator outputs to the carry adder circuit partial products based on the M bit multiplicand and N bit multiplier. The carry adder circuit contains a plurality of carry adders connected in a hierarchical tree structure such that a plurality of carry adder stages are defined, with each carry adder stage except a first carry adder stage receiving adder sums from a next adjacent, lower carry adder stage in the hierarchical tree structure. The first carry adder stage receives the partial products output from the partial products generator. The multiplication circuit is optimized by employing carry select adders or carry look-ahead adders in the hierarchical tree structure.
摘要翻译：用于浮点数字处理系统的乘法电路包括部分乘积发生器和进位加法器电路，用于确定由M位被乘数和N位乘法器相乘产生的乘积。基于M位被乘数和N位乘法器，部分乘积发生器输出到进位加法器电路部分乘积。进位加法器电路包含多个以分层树结构连接的进位加法器，从而定义多个进位加法器级，除了第一进位加法器级之外的每个进位加法器级接收来自下一个相邻的低进位加法器级的加法器在分层树结构中。第一进位加法器级接收来自部分积发生器的部分积输出。乘法电路通过采用进位选择加法器或在分层树结构中携带预先加法器进行优化。

48. 发明授权

US4979018A Semiconductor device with parallel multiplier using at least three wiring layers 失效
标题翻译：具有并联乘法器的半导体器件使用至少三个布线层
公开(公告)号：US4979018A
公开(公告)日：1990-12-18
申请号：US407152
申请日：1989-09-14
申请人： Shigeru Tanaka
发明人： Shigeru Tanaka
IPC分类号： G06F7/53 , G06F7/52 , H01L21/3205 , H01L21/822 , H01L23/52 , H01L27/04
CPC分类号： G06F7/533 , G06F2207/4802
摘要： In a semiconductor device of the present invention, partial products of a multiplicand and a specific bit of a multiplier are formed by a plurality of partial product producing circuits. The results of multiplication obtained from the partial product producing circuits are output to one of full adders serving as first partial sum producing circuits through a first connection wire formed of a first metal wiring layer and a second metal wiring layer formed above the first layer. In the first full adders, specific bits of the partial product producing circuits are grouped for addition. The result of this addition is output to a second full adder through a second connection wire formed of a third metal wiring layer formed above the second layer. In the second full adder, the results of addition obtained from the first full adders are added together, and then the result obtained from the second full adder is output to other full adders and a final full adder to obtain the product of the multiplicand and the multiplier.
摘要翻译：在本发明的半导体器件中，通过多个部分积产生电路形成乘法器的乘法器和特定位的部分积。通过由形成在第一层上的第一金属布线层和第二金属布线层形成的第一连接线，将从部分积产生电路获得的相乘结果输出到用作第一部分和产生电路的全加法器之一。在第一个全加法器中，部分乘积生成电路的特定位被分组以进行加法。该添加的结果通过由形成在第二层上方的第三金属布线层形成的第二连接线输出到第二全加器。在第二个全加器中，将从第一个全加法器获得的相加结果相加在一起，然后从第二个全加器得到的结果输出到其他全加器，最终的全加法器得到被乘数乘积乘数。

49. 发明授权

US4075704A Floating point data processor for high speech operation 失效
标题翻译：浮动点数据处理器，用于高语音操作
公开(公告)号：US4075704A
公开(公告)日：1978-02-21
申请号：US702148
申请日：1976-07-02
申请人： George P. O'Leary
发明人： George P. O'Leary
IPC分类号： G06F7/00 , G06F7/50 , G06F7/52 , G06F7/57 , G06F7/76 , G06F9/38 , G06F7/38
CPC分类号： G06F7/5312 , G06F7/483 , G06F7/485 , G06F7/4876 , G06F7/533 , G06F9/3879 , G06F2207/3884 , G06F2207/3896 , G06F7/49936 , G06F7/49947
摘要： A digital data processor includes a plurality of memory registers, a floating point adder and a floating point multiplier intercoupled by a plurality of simultaneously operable parallel buses facilitating multiple parallel operations during one clock cycle or instruction. The floating adder and multiplier each include a number of stages separated by intermediate temporary storage registers which receive the partial results of a computation for use by the next stage during the next clock period. Floating point additions, multiplications and other arithmetic and logical results are produced during each clock cycle.

50. 发明公开

US20240329932A1 MULTIPLICATION CIRCUITRY, APPARATUS, SYSTEM, CHIP-CONTAINING PRODUCT, METHOD AND COMPUTER-READABLE MEDIUM 审中-公开
公开(公告)号：US20240329932A1
公开(公告)日：2024-10-03
申请号：US18129973
申请日：2023-04-03
申请人： Arm Limited
发明人： Nicholas Andrew PFISTER
IPC分类号： G06F7/527 , G06F7/501 , G06F7/533
CPC分类号： G06F7/5272 , G06F7/501 , G06F7/533
摘要： Multiplication circuitry comprises at least two adder arrays each to add a respective set—of partial products to generate a respective product representing value representing a result of multiplication of a respective pair of portions of bits selected from first and second operands. The adder arrays comprise separate instances of hardware circuitry having at least two separate enable control signals for independently controlling whether at least two subsets of adder arrays are enabled or disabled. Booth encoding circuitry is shared between the adder arrays, to Booth encode the first operand to generate partial product selection indicators each corresponding to a Booth encoding of a respective Booth digit of the first operand. At least two adder arrays operate on respective partial products selected by partial product selection circuitry based on a same partial product selection indicator generated by the shared Booth encoding circuitry based on a same Booth digit of the first operand.

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