专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20030191912A1 Integrated memory having a memory cell array containing a plurality of memory banks, and circuit configuration having an integrated memory 有权
标题翻译：具有包含多个存储体的存储单元阵列的集成存储器以及具有集成存储器的电路配置
公开(公告)号：US20030191912A1
公开(公告)日：2003-10-09
申请号：US10409012
申请日：2003-04-08
发明人： Jean-Marc Dortu
IPC分类号： G06F012/00
CPC分类号： G06F13/1647 , G06F15/7857
摘要： An integrated memory has at least two connection panels, which can be operated independently of one another, for external communication by the memory. In addition, a control circuit produces a number of first control signals and a number of second control signals for external tap-off. The number of first control signals corresponds to a number of memory banks. The first control signals are each associated with a memory bank and indicate that an associated memory bank is being accessed. The number of second control signals corresponds to the number of connection panels. One of the second control signals is produced if an access collision occurs between access to one of the memory banks via one connection panel and access to the same memory bank via another connection panel. Two processor units are connected to the connection panels and access the memory independently of one another on the basis of the control signals.
摘要翻译：集成存储器具有至少两个连接面板，其可以彼此独立地操作，用于存储器的外部通信。此外，控制电路产生多个第一控制信号和多个用于外部分接的第二控制信号。第一控制信号的数量对应于多个存储体。第一控制信号各自与存储体相关联并且指示正在访问相关联的存储体。第二控制信号的数量对应于连接面板的数量。如果在通过一个连接面板访问一个存储体之间并且经由另一个连接面板访问相同的存储体时发生访问冲突，则产生第二控制信号之一。两个处理器单元连接到连接面板，并且基于控制信号彼此独立地访问存储器。

42. 发明授权

US06518972B1 3-D graphics chip with embedded DRAM buffers 有权
标题翻译：具有嵌入式DRAM缓冲器的3-D图形芯片
公开(公告)号：US06518972B1
公开(公告)日：2003-02-11
申请号：US09969450
申请日：2001-10-01
申请人： Tsailai Terry Wu , Yudianto Halim
发明人： Tsailai Terry Wu , Yudianto Halim
IPC分类号： G06F1576
CPC分类号： G06F9/5016 , G06F9/3879 , G06F15/7857
摘要： A 3-D graphics chip includes independent internal DRAM buffers each having a wide bandwidth access bus for connection to a 3-D texture rendering drawing engine. The 3-D drawing engine takes advantage of a flexible embedded memory interface to reduce the traditional 3-D pipeline delay by a factor of 3. In a specific embodiment, each of three drawing processes—texture, Z, pixel—retrieves and stores information in a separate embedded drawing buffer via separate wide bandwidth access busses. Access to an external memory is provided via a separate external access bus. In another specific embodiment, the 3-D drawing engine accesses the embedded drawing buffers via read and write FIFO's to maximize the drawing process throughput.
摘要翻译： 3-D图形芯片包括独立的内部DRAM缓冲器，每个缓冲器具有用于连接到3-D纹理渲染绘图引擎的宽带宽存取总线。 3-D绘图引擎利用灵活的嵌入式存储器接口来将传统的3-D流水线延迟降低3倍。在具体实施例中，三个绘制过程中的每一个 - 纹理，Z，像素 - 检索和存储信息在单独的嵌入式绘图缓冲区中通过单独的宽带宽访问总线。通过单独的外部访问总线提供对外部存储器的访问。在另一个具体实施例中，3-D绘图引擎通过读写FIFO访问嵌入式绘图缓冲器，以最大化绘制过程的吞吐量。

43. 发明申请

US20020184284A1 Single precision array processor 有权
标题翻译：单精度阵列处理器
公开(公告)号：US20020184284A1
公开(公告)日：2002-12-05
申请号：US10167004
申请日：2002-06-10
申请人： HYNIX SEMICONDUCTOR INC.
发明人： Earle W. Jennings III
IPC分类号： G06F007/38
CPC分类号： G06F15/7857 , G06F7/483 , G06F7/5443
摘要： A digital electronic circuit for performing single precision floating point arithmetic involving multiple operations of multiplication, and addition or subtraction. Multiple operations may occur within each time unit of operation.
摘要翻译：一种用于执行单精度浮点运算的数字电子电路，涉及乘法和加法或减法的多个运算。在每个时间操作单元内可能会发生多个操作。

44. 发明授权

US06430589B1 Single precision array processor 失效
标题翻译：单精度阵列处理器
公开(公告)号：US06430589B1
公开(公告)日：2002-08-06
申请号：US09100448
申请日：1998-06-19
申请人： Earle W. Jennings, III
发明人： Earle W. Jennings, III
IPC分类号： G06F752
CPC分类号： G06F15/7857 , G06F7/483 , G06F7/5443
摘要： A device for performing single precision floating point arithmetic. The device includes a shared operand generator that receives an operand and outputs a result that is a fixed function of the operand. It also includes an arithmetic circuit comprising a plurality of multiply circuits that calculate partial products of a first and second operand and the result of the shared operand generator. It also includes circuitry to calculate the sum of the partial products and a third operand to produce the arithmetic result.
摘要翻译：用于执行单精度浮点运算的装置。该设备包括一个共享操作数发生器，它接收一个操作数并输出作为操作数的固定功能的结果。它还包括一个算术电路，它包括计算第一和第二操作数的部分乘积的多个乘法电路以及共享操作数发生器的结果。它还包括计算部分乘积和第三个操作数之和以产生算术结果的电路。

45. 发明授权

US06085314A Central processing unit including APX and DSP cores and including selectable APX and DSP execution modes 失效
标题翻译：中央处理单元包括APX和DSP内核，包括可选的APX和DSP执行模式
公开(公告)号：US06085314A
公开(公告)日：2000-07-04
申请号：US969858
申请日：1997-11-14
申请人： Saf Asghar , Andrew Mills
发明人： Saf Asghar , Andrew Mills
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F15/78 , G06F15/163
CPC分类号： G06F9/3822 , G06F15/7857 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/30196 , G06F9/382 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. In a first embodiment, the CPU receives general purpose instructions, such as X86 instructions, wherein certain X86 instruction sequences implement DSP functions. The CPU includes a processor mode register which is written with one or more processor mode bits to indicate whether an instruction sequence implements a DSP function. The CPU also includes an intelligent DSP function decoder or preprocessor which examines the processor mode bits and determines if a DSP function is being executed. If a DSP function is being implemented by an instruction sequence, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. If the processor mode bits indicate that X86 instructions in the instruction memory do not implement a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. In a second embodiment, the CPU receives sequences of instructions comprising X86 instructions and DSP instructions. The processor mode register is written with one or more processor mode bits to indicate whether an instruction sequence comprises X86 or DSP instructions, and the instructions are routed to the X86 core or to the DSP core accordingly.
摘要翻译：包括通用CPU组件（例如X86内核）的CPU或微处理器，还包括DSP内核。在第一实施例中，CPU接收诸如X86指令的通用指令，其中某些X86指令序列实现DSP功能。 CPU包括处理器模式寄存器，其被写入一个或多个处理器模式位以指示指令序列是否实现DSP功能。 CPU还包括智能DSP功能解码器或预处理器，它检查处理器模式位，并确定DSP功能是否正在执行。如果通过指令序列实现DSP功能，则DSP功能解码器将操作码转换或映射到提供给DSP内核的DSP宏指令。 DSP内核执行一个或多个DSP指令以响应于宏指令来实现所需的DSP功能。如果处理器模式位指示指令存储器中的X86指令不实现DSP类型功能，则将操作码提供给当前现有技术计算机系统中发生的X86内核。在第二实施例中，CPU接收包括X86指令和DSP指令的指令序列。处理器模式寄存器用一个或多个处理器模式位写入，以指示指令序列是否包括X86或DSP指令，并将指令相应地路由到X86内核或DSP内核。

46. 发明授权

US5864706A Digital signal processing apparatus and information processing system 失效
标题翻译：数字信号处理装置及信息处理系统
公开(公告)号：US5864706A
公开(公告)日：1999-01-26
申请号：US693005
申请日：1996-08-06
申请人： Masuyoshi Kurokawa , Seiichiro Iwase , Takao Yamazaki , Kenichiro Nakamura
发明人： Masuyoshi Kurokawa , Seiichiro Iwase , Takao Yamazaki , Kenichiro Nakamura
IPC分类号： G06F15/80 , G06F15/78 , G06F12/00
CPC分类号： G06F15/7857
摘要： A digital signal processing apparatus and information processing system provide sufficient arithmetic operation performance to process high rate signals in real time and high programming performance to deal with various applications. A group of processor elements is constituted by individual processor elements each formed by disposing an arithmetic and logic unit on the bit lines of a multiport memory wherein their number is equal to or larger than the number of the data bits in a series of serial data, and the plurality of processor elements constituting the group of processor elements are uniformly controlled by controllers mounted on the same silicon chip. Consequently, the multiport memory functioning as a buffer for input data and the arithmetic and logic unit are closely joined together, so data can be communicated smoothly between them. Since the plurality of processor elements are controlled by a single controller so as to operate as a parallel computer, a digital signal processor with a high processing speed can be implemented.
摘要翻译：数字信号处理装置和信息处理系统提供足够的算术运算性能，以实时处理高速率信号和高编程性能来处理各种应用。一组处理器元件由各个处理器元件构成，每个处理器元件通过在多端口存储器的位线上设置算术和逻辑单元而形成，其中它们的数量等于或大于一系列串行数据中的数据位数，并且构成处理器元件组的多个处理器元件由安装在同一硅芯片上的控制器均匀地控制。因此，用作输入数据的缓冲器的多端口存储器和算术和逻辑单元紧密地连接在一起，因此可以在它们之间平滑地传送数据。由于多个处理器元件由单个控制器控制以便作为并行计算机操作，因此可以实现具有高处理速度的数字信号处理器。

47. 发明授权

US5794068A CPU with DSP having function preprocessor that converts instruction sequences intended to perform DSP function into DSP function identifier 失效
标题翻译：具有DSP功能预处理器的CPU将用于执行DSP功能的指令序列转换为DSP功能标识符
公开(公告)号：US5794068A
公开(公告)日：1998-08-11
申请号：US618243
申请日：1996-03-18
申请人： Saf Asghar , Mark Ireton , John Bartkowiak
发明人： Saf Asghar , Mark Ireton , John Bartkowiak
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F15/78 , G06F15/163
CPC分类号： G06F9/3822 , G06F15/7857 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/382 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3877 , G06F9/3879 , G06F9/3885
摘要： A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. If the DSP function decoder determines that a DSP function is being executed, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. The DSP core implements or performs the DSP function using a lesser number of instructions and also in reduced number of clock cycles, thus increasing system performance. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. The X86 core and the DSP core are coupled to each other and communicate data and timing signals for synchronization purposes. Thus, the DSP core offloads these mathematical functions from the X86 core, thereby increasing system performance. The DSP core also operates in parallel with the X86 core, providing further performance benefits. The CPU of the present invention thus implements DSP functions more efficiently than X86 logic while requiring no additional X86 opcodes. The present invention also generates code that operates transparently on an X86 only CPU or a CPU according to the present invention which includes X86 and DSP cores. Thus the present invention is backwards compatible with existing software.
摘要翻译：包括通用CPU组件（例如X86内核）的CPU或微处理器，还包括DSP内核。 CPU还包括智能DSP功能解码器或预处理器，用于检查X86操作码序列，并确定DSP功能是否正在执行。如果DSP功能解码器确定正在执行DSP功能，则DSP功能解码器将操作码转换或映射到提供给DSP内核的DSP宏指令。 DSP内核执行一个或多个DSP指令以响应于宏指令来实现所需的DSP功能。 DSP内核使用较少数量的指令实现或执行DSP功能，同时也减少了数量的时钟周期，从而提高了系统性能。如果指令高速缓存或指令存储器中的X86操作码不指示或不旨在执行DSP类型功能，则将操作码提供给当前现有技术计算机系统中发生的X86内核。 X86内核和DSP内核相互耦合，并传送数据和定时信号以实现同步。因此，DSP核心从X86内核中卸载了这些数学函数，从而提高了系统性能。 DSP内核还与X86内核并行运行，提供了更多的性能优势。因此，本发明的CPU比X86逻辑更有效地实现DSP功能，而不需要额外的X86操作码。本发明还生成根据包括X86和DSP内核的本发明的仅在X86仅CPU或CPU上透明地操作的代码。因此，本发明与现有软件向后兼容。

48. 发明授权

US5781792A CPU with DSP having decoder that detects and converts instruction sequences intended to perform DSP function into DSP function identifier 失效
标题翻译：具有DSP的CPU具有检测并转换旨在执行DSP功能的指令序列到DSP功能标识符的解码器
公开(公告)号：US5781792A
公开(公告)日：1998-07-14
申请号：US618000
申请日：1996-03-18
申请人： Saf Asghar , Mark Ireton , John Bartkowiak
发明人： Saf Asghar , Mark Ireton , John Bartkowiak
IPC分类号： G06F9/318 , G06F9/38 , G06F15/78 , G06F9/30 , G06F15/163
CPC分类号： G06F9/3017 , G06F15/7857 , G06F9/3879 , G06F9/3885
摘要： A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. If the DSP function decoder determines that a DSP function is being executed, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. The DSP core implements or performs the DSP function using a lesser number of instructions and also in reduced number of clock cycles, thus increasing system performance. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. The X86 core and the DSP core are coupled to each other and communicate data and timing signals for synchronization purposes. Thus, the DSP core offloads these mathematical functions from the X86 core, thereby increasing system performance. The DSP core also operates in parallel with the X86 core, providing further performance benefits. The CPU of the present invention thus implements DSP functions more efficiently than X86 logic while requiring no additional X86 opcodes. The present invention also generates code that operates transparently on an X86 only CPU or a CPU according to the present invention which includes X86 and DSP cores. Thus the present invention is backwards compatible with existing software.
摘要翻译：包括通用CPU组件（例如X86内核）的CPU或微处理器，还包括DSP内核。 CPU还包括智能DSP功能解码器或预处理器，用于检查X86操作码序列，并确定DSP功能是否正在执行。如果DSP功能解码器确定正在执行DSP功能，则DSP功能解码器将操作码转换或映射到提供给DSP内核的DSP宏指令。 DSP内核执行一个或多个DSP指令以响应于宏指令来实现所需的DSP功能。 DSP内核使用较少数量的指令实现或执行DSP功能，同时也减少了数量的时钟周期，从而提高了系统性能。如果指令高速缓存或指令存储器中的X86操作码不指示或不旨在执行DSP类型功能，则将操作码提供给当前现有技术计算机系统中发生的X86内核。 X86内核和DSP内核相互耦合，并传送数据和定时信号以实现同步。因此，DSP核心从X86内核中卸载了这些数学函数，从而提高了系统性能。 DSP内核还与X86内核并行运行，提供了更多的性能优势。因此，本发明的CPU比X86逻辑更有效地实现DSP功能，而不需要额外的X86操作码。本发明还生成根据包括X86和DSP内核的本发明的仅在X86仅CPU或CPU上透明地操作的代码。因此，本发明与现有软件向后兼容。

49. 发明授权

US5689695A Conditional processor operation based upon result of two consecutive prior processor operations 失效
标题翻译：基于两个连续的现有处理器操作的结果的条件处理器操作
公开(公告)号：US5689695A
公开(公告)日：1997-11-18
申请号：US482697
申请日：1995-06-07
申请人： Christopher J. Read
发明人： Christopher J. Read
IPC分类号： G06F9/318 , G06F9/32 , G06F9/38 , G06F15/78 , G06T1/20 , G06F9/30
CPC分类号： G06F9/30094 , G06F15/7857 , G06F9/30072 , G06F9/30189 , G06F9/30192 , G06F9/34 , G06F9/3842 , G06T1/20
摘要： This invention performs conditional operations and conditional branches based upon mixed conditions. The invention performs a first arithmetic/logical operation via an arithmetic logic unit (230). At least one status bit in a status register (210) is set based upon the results. This status bit could be a negative status bit, a carry out status bit, an overflow status bit or a zero status bit. In a first embodiment, the arithmetic logic unit (230) performs a second operation conditional upon a selected one of the status bits. The status bits are then set based upon the results of this second operation. A third operation, which could be an arithmetic logic unit operation, a memory load, memory store, a register to register move, a subroutine call, subroutine return or program branch, is conditional upon the selected status bit, thus performing upon the logical AND of the results of the first and second operations. In a second embodiment, the second operation is conditioned on the inverse of the selected status bit. The result of this second operation also sets the status bits. The third operation is conditional upon the selected status bit. Thus the third operation is performed if either the first operation or the second operation sets the selected status bit forming a logical OR of the results of the first and second operations.
摘要翻译：本发明基于混合条件执行条件操作和条件分支。本发明通过算术逻辑单元（230）执行第一运算/逻辑运算。基于结果来设置状态寄存器（210）中的至少一个状态位。该状态位可以是负状态位，进位状态位，溢出状态位或零状态位。在第一实施例中，算术逻辑单元（230）根据选择的一个状态位执行第二操作。然后基于该第二操作的结果来设置状态位。可以是算术逻辑单元操作，存储器负载，存储器存储器，寄存器移位寄存器，子程序调用，子程序返回或程序分支的第三操作，取决于所选择的状态位，因此在逻辑“与” 的第一和第二操作的结果。在第二实施例中，第二操作根据所选状态位的倒数进行调节。该第二操作的结果也设置状态位。第三个操作取决于选定的状态位。因此，如果第一操作或第二操作将选择的状态位设置为形成第一和第二操作的结果的逻辑或，则执行第三操作。

50. 发明授权

US5633808A Digital signal processor 失效
标题翻译：数字信号处理器
公开(公告)号：US5633808A
公开(公告)日：1997-05-27
申请号：US674216
申请日：1996-07-01
申请人： Morito Morishima
发明人： Morito Morishima
IPC分类号： G06F9/28 , G06F9/38 , G06F15/78 , G06F15/76
CPC分类号： G06F15/7857
摘要： A digital signal processor is mainly configured by a parallel-processing unit, a plurality of memory portions and a micro-code producing portion. Each of the memory portions accompanies with an input circuit and an output circuit, while the parallel-processing unit contains a plurality of operating elements such as multipliers, adders and the like. An interconnection manner among the operating elements is changed responsive to the micro code so as to embody a desired configuration by which a desired parallel processing can be carried out. One of the micro codes is selected in accordance with an operational result of the parallel-processing unit, so that the micro code to be supplied to the parallel-processing unit can be changed by one sampling period. In accordance with the micro code, data is read from a desired memory portion so that the read data is supplied to a desired operating element, while the operational result obtained from each operating element is written into a desired memory portion. Preferably, the parallel-processing unit is configured by an arithmetic and logic unit (ALU) and/or a programmable logic array.
摘要翻译：数字信号处理器主要由并行处理单元，多个存储器部分和微码产生部分构成。每个存储器部分伴随着输入电路和输出电路，而并行处理单元包含多个操作元件，例如乘法器，加法器等。操作元件之间的互连方式响应于微代码而改变，以体现所期望的配置，通过该配置可以执行所需的并行处理。根据并行处理单元的运算结果来选择其中一个微码，使得提供给并行处理单元的微码可以改变一个采样周期。根据微码，从期望的存储器部分读取数据，使得将读取的数据提供给期望的操作元件，同时将从每个操作元件获得的操作结果写入期望的存储器部分。优选地，并行处理单元由算术和逻辑单元（ALU）和/或可编程逻辑阵列构成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式