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41. 发明申请

US20030163562A1 Remote information logging and selective reflections of loggable information 审中-公开
标题翻译：远程信息记录和可选信息的选择性反映
公开(公告)号：US20030163562A1
公开(公告)日：2003-08-28
申请号：US10082245
申请日：2002-02-26
发明人： Daniel E. Ford , Steven V. Britt
IPC分类号： G06F015/173
CPC分类号： G06F11/2268 , G06F11/0727 , G06F11/0781
摘要： Methods (as well as apparatus and software that implement the methods) of remote information logging and selective reflections of loggable information are disclosed. One such method comprises: receiving a notice of locally-originated loggable information; determining whether said information satisfies a first criterion; and notifying, if said first criterion is satisfied, a remote logger service of said information. Another such method comprises: receiving multiple instances of remotely-originated loggable information; and making entries in a local log for said multiple instances of remotely-originated loggable information. And yet another such method comprises: providing access to a local log of remotely-originated information; determining whether information corresponding to an entry in said local log satisfies a first criterion; and notifying, if said first criterion is satisfied, a remote service of said information.
摘要翻译：公开了远程信息记录的方法（以及实现方法的设备和软件）以及可读信息的选择性反映。一种这样的方法包括：接收本地发送的可登录信息的通知; 确定所述信息是否满足第一标准; 并且如果满足所述第一标准，则通知所述信息的远程记录器服务。另一种方法包括：接收远程发送的可登录信息的多个实例; 并在本地日志中为所述多个远程发起的可登录信息的实例进行输入。而另一种这样的方法包括：提供对远程发起的信息的本地日志的访问; 确定与所述本地日志中的条目相对应的信息是否满足第一准则; 并且如果满足所述第一标准，则通知所述信息的远程服务。

42. 发明申请

US20020078401A1 Test coverage analysis system 审中-公开
标题翻译：测试覆盖分析系统
公开(公告)号：US20020078401A1
公开(公告)日：2002-06-20
申请号：US09738068
申请日：2000-12-15
发明人： Michael Andrew Fry
IPC分类号： G06F011/263
CPC分类号： G06F11/2268 , G06F11/263
摘要： The present invention provides a system, apparatus and method for determining a test coverage for a device by receiving test data from a test platform or development tool, processing the test data to determine or predict the test coverage for the device, and storing the test data and test coverage in a standard format. The test data includes the results of two or more tests on the device.
摘要翻译：本发明提供一种用于通过从测试平台或开发工具接收测试数据来确定设备的测试覆盖范围的系统，装置和方法，处理测试数据以确定或预测该设备的测试覆盖范围，以及存储测试数据并以标准格式测试覆盖。测试数据包括设备上的两个或多个测试结果。

43. 发明授权

US06327668B1 Determinism in a multiprocessor computer system and monitor and processor therefor 失效
标题翻译：多处理器计算机系统中的确定性及其监视和处理器
公开(公告)号：US06327668B1
公开(公告)日：2001-12-04
申请号：US09106883
申请日：1998-06-30
申请人： Emrys J. Williams
发明人： Emrys J. Williams
IPC分类号： G06F1100
CPC分类号： G06F9/526 , G06F9/52 , G06F11/004 , G06F11/0724 , G06F11/0745 , G06F11/0793 , G06F11/1641 , G06F11/165 , G06F11/1654 , G06F11/1679 , G06F11/1683 , G06F11/1691 , G06F11/184 , G06F11/187 , G06F11/22 , G06F11/2268 , G06F11/30 , G06F2201/88
摘要： A multiprocessor computer system which provides fault tolerance includes a number of processing sets. At least one of the processing sets is operable asynchronously of a second processing set. A monitor is connected to receive I/O operations output from the processing sets for identifying faulty operation of those units. The monitor is also operable to synchronise operation of the processing sets by signalling the processing sets on receipt of outputs from those units indicative of a plurality of them being at an equivalent stage of processing. The monitor provides for buffering of I/O operations output from the processing sets and for selective forwarding of those I/O operations to an external I/O bus. The processing set may be formed from a single processor or from multiple processors.
摘要翻译：提供容错的多处理器计算机系统包括多个处理集合。至少一个处理组可与第二处理集合异步地操作。连接监视器以接收从处理集输出的I / O操作，以识别这些单元的故障操作。监视器还可操作以通过在接收到来自那些指示多个处理器处于相同处理阶段的那些单元的输出时发信号通知处理集来同步处理集合的操作。监视器用于缓冲来自处理集的I / O操作输出，以及将这些I / O操作选择性地转发到外部I / O总线。处理集可以由单个处理器或多个处理器形成。

44. 发明授权

US6098182A Apparatus for monitoring tests run on a personal computer 失效
标题翻译：用于监控测试的装置在个人计算机上运行
公开(公告)号：US6098182A
公开(公告)日：2000-08-01
申请号：US994372
申请日：1997-12-19
申请人： Jeffrey Cowan
发明人： Jeffrey Cowan
IPC分类号： G06F11/00 , G06F11/22 , G06F11/273 , G06F11/30 , G06F11/32 , H02H3/05
CPC分类号： G06F11/0757 , G06F11/2268 , G06F11/273 , G06F11/2294 , G06F11/325
摘要： A personal computer monitoring device includes a reporting device and a processing unit. The reporting device is adapted to take a fail action responsive to a first signal. The processing unit is adapted to receive the first signal from an under test personal computer and to send the first signal to the reporting device when the processing unit does not receive a new result signal from the under test computer system during a preselected time period. One illustrative use of the monitoring device is during the assembly and pre-sale testing of personal computers.
摘要翻译：个人计算机监视装置包括报告装置和处理单元。报告设备适于响应于第一信号采取失败动作。所述处理单元适于从未被测试的个人计算机接收所述第一信号，并且当所述处理单元在预选时间段期间未从所述待测计算机系统接收到新的结果信号时，将所述第一信号发送到所述报告装置。在个人计算机的组装和预售测试期间，监视装置的一个说明性的使用。

45. 发明授权

US6085337A Method and system for reliably indicating test results during a self-check operation 有权
标题翻译：在自检操作期间可靠地指示测试结果的方法和系统
公开(公告)号：US6085337A
公开(公告)日：2000-07-04
申请号：US157752
申请日：1998-09-21
申请人： Karl-Heinz Mattheis , Tommaso Bacigalupo
发明人： Karl-Heinz Mattheis , Tommaso Bacigalupo
IPC分类号： G06F11/22 , G06F11/267 , G06F11/27
CPC分类号： G06F11/2268 , G06F11/267
摘要： A method and system for accurately indicating test results from testing routines of a self-check operation during initialization or reset of the system utilize test result bits in a secure status register that must be sequentially reset to indicate a successful completion of the self-check operation. The system is a microcontroller that can be incorporated into various consumer products requiring digital processing. Each test result bit represents a distinct component of the system that is tested during the self-check operation. The test result bits in the status register can only be reset one at a time, by activating a demultiplexer which resets a particular test result bit in response to a successful testing of a component. However, the demultiplexer can only be activated by modifying a control bit in an access register that is protected by a double password scheme. To modify the control bit, the CPU must provide two valid passwords. The activation of the demultiplexer is repeated for each component of the system that is tested to reset a corresponding test result bit in the status register. Consequently, the CPU must write a different device designation value into the control register for each component that is tested. When all the test result bits have been reset, a confirmation signal is generated.
摘要翻译：用于在系统初始化或复位期间从自检操作的测试例程准确地指示测试结果的方法和系统利用必须顺序重置以指示自检操作成功完成的安全状态寄存器中的测试结果位。该系统是可以并入需要数字处理的各种消费产品中的微控制器。每个测试结果位表示在自检操作期间测试的系统的不同组件。状态寄存器中的测试结果位只能通过激活一个复用特定测试结果位的解复用器来响应成功测试组件而一次重置。然而，解复用器只能通过修改由双密码方案保护的访问寄存器中的控制位来激活。要修改控制位，CPU必须提供两个有效的密码。对被测试的系统的每个组件重复解复用器的激活，以重置状态寄存器中相应的测试结果位。因此，CPU必须为测试的每个组件向控制寄存器写入不同的设备指定值。当所有测试结果位都被复位时，产生一个确认信号。

46. 发明授权

US5884023A Method for testing an integrated circuit with user definable trace function 失效
标题翻译：用户可定义的跟踪功能测试集成电路的方法
公开(公告)号：US5884023A
公开(公告)日：1999-03-16
申请号：US762487
申请日：1996-12-09
申请人： Gary L. Swoboda , Eric J. Stotzer
发明人： Gary L. Swoboda , Eric J. Stotzer
IPC分类号： G06F11/28 , G06F11/22 , G06F11/34 , G06F11/36 , G06F11/00
CPC分类号： G06F11/2268 , G06F11/3466 , G06F11/3636
摘要： A method for testing a digital processor 11 in which a test port 1149 is used to transfer trace data from the digital processor to a test host processor 1101 under control of a user definable program which executes in response to predetermined events on the digital processor. Trace data is gathered while an application program loaded in program memory 61 is executed by the digital processor. Trace data is temporarily stored in a trace region 99 of data memory 25 by user definable code which is executed in a background manner by the digital processor in response to trigger events. The trigger events are also enabled by user definable code which enables various portions of analysis hardware 1217. Trace data is transferred from the digital processor to the test host processor through test port 1149 by sending a notification signal to the test host processor by means of message passing register 1216. The digital processor then monitors the message passing register for a handshake signal from the test host processor. When a handshake signal is received, trace data is written into the message passing register by user definable code in a background manner and transferred to the test host processor.
摘要翻译：一种用于测试数字处理器11的方法，其中测试端口1149用于在根据数字处理器上的预定事件执行的用户可定义程序的控制下将跟踪数据从数字处理器传送到测试主机处理器1101。当由数字处理器执行加载在程序存储器61中的应用程序时，收集跟踪数据。跟踪数据通过数字处理器响应于触发事件以后台方式执行的用户可定义码临时存储在数据存储器25的跟踪区域99中。触发事件也由用户定义的代码启用，其允许分析硬件1217的各个部分。跟踪数据通过测试端口1149从数字处理器传送到测试主机处理器，通过消息的方式向测试主处理器发送通知信号通过寄存器1216.然后，数字处理器监视消息传递寄存器以获得来自测试主机处理器的握手信号。当接收到握手信号时，跟踪数据以后台方式由用户定义的代码写入消息传递寄存器，并传送到测试主机处理器。

47. 发明授权

US4713758A Computer testing arrangement 失效
标题翻译：电脑测试安排
公开(公告)号：US4713758A
公开(公告)日：1987-12-15
申请号：US728671
申请日：1985-04-29
申请人： Nergal R. De Kelaita , Joe T. Hall , Barrie D. Kletscher
发明人： Nergal R. De Kelaita , Joe T. Hall , Barrie D. Kletscher
IPC分类号： G06F11/34 , G06F11/00 , G06F11/22 , G06F11/36
CPC分类号： G06F11/3672 , G06F11/2268 , G06F11/3476 , G06F11/348
摘要： In the disclosed system, the operation of a target computer is monitored by a terminal controller connected to one or more of the computer's input/output ports. The controller can send data on one of the computer's ports and simultaneously record and monitor computer response at several of the computer's input/output ports. Two data queues are provided for each monitored port and received data is stored in a first queue, referred to as a spooler queue, and may be searched for a specified character string before it is transferred to the second queue called the demux queue. Received information, in addition to being searched for a specified character string, is also examined for message type and a message type designation is added to each data word or message transferred to the demux queue. From the demux queue the data is transferred to different storage files depending upon the message type designation. The transfer of data through the queues is controlled by several processes which communicate via a shared memory area. Such a set of queues and processes is provided for each monitored port, operating independently from processes for other ports.
摘要翻译：在所公开的系统中，目标计算机的操作由连接到计算机的一个或多个输入/输出端口的终端控制器进行监视。控制器可以在其中一台计算机的端口上发送数据，同时记录并监视计算机的几个输入/输出端口的计算机响应。为每个被监控的端口提供两个数据队列，并且接收的数据被存储在被称为后台处理程序队列的第一个队列中，并且可以在将其传送到被称为解复用队列的第二队列之前搜索指定的字符串。接收到的信息，除了搜索指定的字符串之外，还检查消息类型，并且将消息类型标识添加到传送到解复用队列的每个数据字或消息。根据消息类型指定，从解码队列将数据传输到不同的存储文件。通过队列的数据传输由通过共享存储区进行通信的几个进程控制。为每个被监控的端口提供这样的一组队列和进程，独立于其他端口的进程操作。

48. 发明公开

US20240378125A1 METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR NETWORK TESTING AND COLLECTING GENERATIVE ARTIFICIAL INTELLIGENCE TRAINING DATA 审中-公开
公开(公告)号：US20240378125A1
公开(公告)日：2024-11-14
申请号：US18233270
申请日：2023-08-11
申请人： Keysight Technologies, Inc.
发明人： Christian Paul Sommers , Peter J. Marsico
IPC分类号： G06F11/22 , G06F11/263
CPC分类号： G06F11/2268 , G06F11/263
摘要： In some examples, a system includes a test controller and a training data collector. The test controller is configured for receiving a test case including test case definition information defining a network test for a system under test (SUT); determining test system resource information for test system resources configured to execute the test case; and executing the test case on the SUT. The training data collector is configured for collecting at least a portion of the test case definition information; collecting SUT status information or SUT configuration information or both for the SUT; collecting metadata associated with the test case including at least one test context label; and processing collected data to produce artificial intelligence training data.

49. 发明授权

US12079097B2 Techniques for testing semiconductor devices 有权
公开(公告)号：US12079097B2
公开(公告)日：2024-09-03
申请号：US17075628
申请日：2020-10-20
申请人： NVIDIA CORPORATION
发明人： Animesh Khare , Ashish Kumar , Shantanu Sarangi , Rahul Garg
IPC分类号： G06F11/273 , G06F11/22 , G06F13/28 , G06F13/42
CPC分类号： G06F11/2733 , G06F11/2268 , G06F13/28 , G06F13/4282 , G06F2213/0026
摘要： Techniques for testing semiconductor devices include a semiconductor device having a plurality of components, a test bus, and a test data transfer unit. The test data transfer unit receives, from a host computer, configuration information for performing a test of the semiconductor device, reads, via a high-speed data transfer link, test data associated with the test from memory of the host computer using direct memory access, sends the test data to the plurality of components via the test bus, causes one or more operations to be performed on the semiconductor device to effect at least a portion of the test, and after the one or more operations have completed, retrieves test results of the at least a portion of the test from the test bus and stores, via the high-speed data transfer link, the test results in the memory of the host computer using direct memory access.

50. 发明授权

US12045148B2 Verification system of basic input output system and verification method thereof 有权
公开(公告)号：US12045148B2
公开(公告)日：2024-07-23
申请号：US17964942
申请日：2022-10-13
申请人： Cheng-Hung Lin , Chang-Yu Tu , Wen-Shyan Lai
发明人： Cheng-Hung Lin , Chang-Yu Tu , Wen-Shyan Lai
IPC分类号： G06F11/22
CPC分类号： G06F11/2284 , G06F11/2268
摘要： A verification system of a basic input output system and a verification method thereof are provided. The verification system includes a server, a microcontroller, and a verification device. The server includes a platform controller hub and the basic input output system. The server outputs a log file of the basic input output system by a system management bus controller in the platform controller hub. The microcontroller is coupled to the server. The microcontroller receives the log file and converts the log file into a readable character. The verification device is coupled to the microcontroller. The verification device receives and displays the readable character.

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