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1. 发明授权

US07085681B1 Symbiotic interrupt/polling approach for monitoring physical sensors 有权
标题翻译：用于监控物理传感器的共享中断/轮询方法
公开(公告)号：US07085681B1
公开(公告)日：2006-08-01
申请号：US11021145
申请日：2004-12-22
申请人： Emrys J. Williams , Kenneth C. Gross
发明人： Emrys J. Williams , Kenneth C. Gross
IPC分类号： G06F11/30 , G06F15/00 , G21C17/00
CPC分类号： G06F11/3058 , G06F11/0724 , G06F11/076 , G06F11/0766 , G06F11/3065
摘要： One embodiment of the present invention provides a system that monitors a computer system using a plurality of physical sensors. The system operates by polling the plurality of physical sensors in a given sequence at a given rate, wherein each physical sensor monitors a specific physical parameter of the computer system. The system then provides a plurality of measurements from the plurality of physical sensors to a monitoring system. If a given physical sensor detects a parameter that is not within a pre-determined operating range, the system receives an interrupt from the given physical sensor. In response to receiving this interrupt, the system raises an alarm.
摘要翻译：本发明的一个实施例提供一种使用多个物理传感器监视计算机系统的系统。系统通过以给定的速率以给定的顺序轮询多个物理传感器来操作，其中每个物理传感器监测计算机系统的特定物理参数。系统然后将多个测量从多个物理传感器提供给监控系统。如果给定的物理传感器检测到不在预定的工作范围内的参数，则系统从给定的物理传感器接收中断。响应收到此中断，系统发出报警。

2. 发明授权

US06256753B1 Bus error handling in a computer system 失效
标题翻译：计算机系统中的总线错误处理
公开(公告)号：US06256753B1
公开(公告)日：2001-07-03
申请号：US09106882
申请日：1998-06-30
申请人： Emrys J. Williams
发明人： Emrys J. Williams
IPC分类号： G06F1100
CPC分类号： G06F9/526 , G06F9/52 , G06F11/004 , G06F11/0724 , G06F11/0745 , G06F11/0793 , G06F11/1641 , G06F11/165 , G06F11/1654 , G06F11/1679 , G06F11/1683 , G06F11/1691 , G06F11/184 , G06F11/187 , G06F11/22 , G06F11/2268 , G06F11/30 , G06F2201/88
摘要： An I/O monitor includes an interface mechanism for connection between a processor and an I/O bus and an error signal modifier. The error signal modifier responds to an error signal from the I/O bus by substituting a determined response for passing to the processor. By returning a determined response to the processor, as opposed to the bus error signal, the need for bus error exception processing by the processor software is removed. The monitor determines a resource forming the source of the bus error and labels the resource as defective in a status register for the resource in the monitor. The monitor generates an interrupt when a resource is first labelled as defective. Subsequently, further access to the resource by the processor are handled by the monitor. The monitor responds to an I/O read operation to a resource labelled as defective to prevent the I/O read operation from being passed to the bus and to return a determined data response. It responds to an I/O write operation to a resource labelled as defective to discard the I/O write operation and to terminate with an acknowledgement as the determined response.
摘要翻译： I / O监视器包括用于处理器和I / O总线之间连接的接口机制和误差信号修改器。误差信号修正器通过将确定的响应替换为处理器来响应来自I / O总线的错误信号。通过将确定的响应返回到处理器，与总线错误信号相反，消除了处理器软件对总线错误异常处理的需要。监视器确定形成总线错误源的资源，并将资源标记为监视器中的资源的状态寄存器中的缺陷。当资源首次被标记为有缺陷时，监视器会产生中断。随后，由处理器进一步访问资源由监视器处理。监视器对被标记为有缺陷的资源对I / O读操作进行响应，以防止I / O读操作传递到总线并返回确定的数据响应。它响应对标记为有缺陷的资源的I / O写操作来丢弃I / O写操作，并以确认的响应终止确认。

3. 发明授权

US6138198A Processor bridge with dissimilar data registers which is operable to disregard data differences for dissimilar data write accesses 失效
标题翻译：具有不同数据寄存器的处理器桥，其可操作以忽略不同数据写访问的数据差异
公开(公告)号：US6138198A
公开(公告)日：2000-10-24
申请号：US97467
申请日：1998-06-15
申请人： Paul J. Garnett , Stephen Rowlinson , Femi A. Oyelakin , Emrys J. Williams
发明人： Paul J. Garnett , Stephen Rowlinson , Femi A. Oyelakin , Emrys J. Williams
IPC分类号： G06F11/18 , G06F11/16 , G06F11/20 , G06F13/36 , G06F13/40
CPC分类号： G06F11/1658 , G06F11/1641 , G06F13/4027 , G06F11/1683 , G06F2201/845
摘要： A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism is configured to compare address and data phases of I/O accesses by the first and second processing sets. At least one dissimilar data register is provided for each processing set. The bridge control mechanism is operable in response to an address phase of a dissimilar data register write access to disregard any differences in the data phase for the dissimilar data write access. Non-deterministic data (for example relating to a real time clock) can be output from the processing sets in a combined (lockstep comparison) mode. A read destination address supplied in common by the first and second processing sets for a dissimilar data read access can cause data read from a determined one of the dissimilar data registers to be supplied the first and second processing sets. In this manner, the processing sets may have the dissimilar data replaced by the same data. The read destination address supplied in common by the first and second processing sets can determine the dissimilar data register from which data is read.
摘要翻译：用于多处理器系统的桥接器包括用于连接到第一处理集合的I / O总线，第二处理集合的I / O总线和设备总线的总线接口。桥接控制机制被配置为比较第一和第二处理集合的I / O访问的地址和数据阶段。为每个处理集提供至少一个不同的数据寄存器。桥接控制机制可响应于不同数据寄存器写访问的地址相位而操作，以忽略不同数据写访问的数据阶段中的任何差异。可以以组合（锁步比较）模式从处理集合输出非确定性数据（例如与实时时钟有关的数据）。通过第一和第二处理集合共同提供的用于不同数据读取访问的读取目的地地址可以使得从所确定的一个不同数据寄存器读取的数据被提供给第一和第二处理集合。以这种方式，处理集可以具有被相同数据替换的不同数据。由第一和第二处理集合共同提供的读取目标地址可以确定从其读取数据的不同数据寄存器。

4. 发明授权

US07681247B2 Anti-theft system and method for semiconductor devices and other electronic components 有权
标题翻译：半导体装置及其他电子元件的防盗系统及方法
公开(公告)号：US07681247B2
公开(公告)日：2010-03-16
申请号：US10375158
申请日：2003-02-27
申请人： Emrys J. Williams
发明人： Emrys J. Williams
IPC分类号： G06F1/26 , G11C29/00
CPC分类号： G06F21/73 , G06F21/88
摘要： A semiconductor device includes a stored device identifier that is accessible to external systems, and a stored secret key that is inaccessible to external systems. The device also includes an input, which in operation receives a system identifier, representing the system into which the device is to be incorporated, and an authorization key. An authorization unit within the device is then used for enabling or disabling the device in accordance with the values of the stored secret key, the received system identifier and the authorization key. The authorization key is typically supplied by a support center in response to being notified of the device identifier. In one embodiment, the authorization unit encrypts the system identifier using the stored secret key as the encryption key and then compares the result against the authorization key.
摘要翻译：半导体器件包括可由外部系统访问的存储的设备标识符和外部系统不可访问的存储的秘密密钥。该设备还包括输入，其在操作中接收表示将要并入设备的系统的系统标识符和授权密钥。然后根据所存储的秘密密钥，接收到的系统标识符和授权密钥的值，使用设备内的授权单元来启用或禁用该设备。响应于通知设备标识符，授权密钥通常由支持中心提供。在一个实施例中，授权单元使用所存储的秘密密钥作为加密密钥加密系统标识符，然后将该结果与授权密钥进行比较。

5. 发明授权

US07231550B1 Event protocol and resource naming scheme 有权
标题翻译：事件协议和资源命名方案
公开(公告)号：US07231550B1
公开(公告)日：2007-06-12
申请号：US10699634
申请日：2003-10-31
申请人： Cynthia A. McGuire , Michael W. Shapiro , Andrew M. Rudoff , Emrys J. Williams
发明人： Cynthia A. McGuire , Michael W. Shapiro , Andrew M. Rudoff , Emrys J. Williams
IPC分类号： G06F11/00
CPC分类号： G06F11/0775 , G06F11/0709 , G06F11/079 , H04L29/12594 , H04L41/065 , H04L41/0654 , H04L41/0816 , H04L41/0853 , H04L61/30 , H04L61/303
摘要： A method for managing a fault involves detecting an error, gathering data associated with the error to generate an error event, and categorizing the error event using a hierarchical organization of the error event.
摘要翻译：用于管理故障的方法包括检测错误，收集与错误相关联的数据以生成错误事件，以及使用错误事件的分级组织对错误事件进行分类。

6. 发明授权

US07200763B2 Method and apparatus for controlling the power consumption of a semiconductor device 有权
标题翻译：用于控制半导体器件的功耗的方法和装置
公开(公告)号：US07200763B2
公开(公告)日：2007-04-03
申请号：US10682758
申请日：2003-10-09
申请人： Emrys J. Williams
发明人： Emrys J. Williams
IPC分类号： G06F1/26 , G06F1/28 , G06F1/30 , G06F1/32
CPC分类号： G06F9/30083 , G06F9/30076 , G06F9/38 , G06F9/3836 , G06F9/3869
摘要： A method and apparatus are provided for controlling the power consumption of a semiconductor device such as a CPU or other form of processor that is operable to process a sequence of instructions. The device includes a monitor for checking the power consumption of the device, in order to detect any significant change in power consumption (which can cause problems for the power supply circuitry). In order to mitigate such change, one or more dummy instructions are inserted into the sequence of instructions. The dummy instructions do not affect the logical processing, but are selected in order to limit the change in power consumption. Thus if the change in power consumption represents an increase, then dummy instructions are selected that do not require much current. Conversely, if the change in power consumption represents a decrease, then dummy instructions are selected that draw a relatively large amount of current.
摘要翻译：提供了一种方法和装置，用于控制可操作以处理指令序列的诸如CPU或其他形式的处理器的半导体器件的功耗。该设备包括用于检查设备的功耗的监视器，以便检测功率消耗的任何显着变化（这可能导致电源电路的问题）。为了减轻这种变化，一个或多个虚拟指令被插入指令序列中。虚拟指令不影响逻辑处理，但是为了限制功耗的变化而被选择。因此，如果功耗的变化表示增加，则选择不需要太多电流的虚拟指令。相反，如果功耗的变化表示减少，则选择绘制相当大量电流的虚拟指令。

7. 发明授权

US06519702B1 Method and apparatus for limiting security attacks via data copied into computer memory 有权
标题翻译：用于通过复制到计算机存储器中的数据来限制安全攻击的方法和装置
公开(公告)号：US06519702B1
公开(公告)日：2003-02-11
申请号：US09235880
申请日：1999-01-22
申请人： Emrys J. Williams
发明人： Emrys J. Williams
IPC分类号： G06F1300
CPC分类号： G06F9/3824 , G06F21/51 , G06F2221/2143 , G06F2221/2153
摘要： A system for limiting security attacks on a computer system that operate by executing computer instructions embedded in data received from an external source. The system receives the data from the external source and performs a transformation on the data that causes any computer instructions encoded in the data to be unexecutable. After the data is transformed, the system stores the data in the computer system's memory. When the data is needed, the system retrieves the data and reverses the transformation. In this way, data from an external source is stored in memory in an unexecutable form, thereby making it impossible to execute malicious code embedded in the data. According to one aspect of the present invention, the data is transformed using a random number, so that the data can only be converted back to its original form with an inverse transformation using the same random number.
摘要翻译：一种用于限制对嵌入在从外部源接收的数据中的计算机指令进行操作的计算机系统上的安全攻击的系统。系统从外部源接收数据，并对数据执行变换，使得在数据中编码的任何计算机指令都将不可执行。数据变换后，系统将数据存储在计算机系统的存储器中。当需要数据时，系统检索数据并反转转换。以这种方式，来自外部源的数据以不可执行形式存储在存储器中，从而使得不可能执行嵌入在数据中的恶意代码。根据本发明的一个方面，使用随机数来转换数据，使得数据只能使用相同的随机数通过逆变换被转换回其原始形式。

8. 发明授权

US6049893A System and method for synchronously resetting a plurality of microprocessors 有权
标题翻译：用于同步复位多个微处理器的系统和方法
公开(公告)号：US6049893A
公开(公告)日：2000-04-11
申请号：US273776
申请日：1999-03-22
申请人： David C. Liddell , Emrys J. Williams
发明人： David C. Liddell , Emrys J. Williams
IPC分类号： G06F11/16 , G05B9/02 , G06F1/26 , G06F11/00 , G06F11/07 , G06F11/10 , G06F11/14 , G06F11/20 , G06F13/00 , H02H3/05 , H03K19/003 , H03K19/007
CPC分类号： G06F11/1654 , G06F11/0709 , G06F11/1604 , G06F11/165 , G06F11/1658 , G06F11/181 , G06F11/185 , G06F11/079 , G06F11/10 , G06F11/1415 , G06F11/1645 , G06F11/1679 , G06F11/20
摘要： A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules. Each central processing module contains a means by which the module can compare data on the main data bus with data on a secondary bus within each module in order to determine if there is an inconsistency indicating a hardware fault. If such an inconsistency is detected, each module generates state outputs which reflect the probability that a particular module is the source of the fault. A synchronization bus which is separate from the main data bus interconnects the central processing modules and transmits the state outputs from each module to every other central processing module.
摘要翻译：描述了容错计算机体系结构，其中硬件故障的影响减弱。该架构采用具有用于互连常规计算机子系统的多个接口槽的主数据总线。子系统的数量和类型可能会有很大变化，但是，包含本发明的创造性要素的中央处理器子系统总是包括在内。中央处理器子系统采用以基本上同步的方式并行操作的多个中央处理模块。中央处理模块之一作为主中央处理模块，是能够从主数据总线读取数据并将数据写入主数据总线的唯一模块。主中央处理模块最初是从中央处理模块中任意选择的。每个中央处理模块包含一个装置，通过该装置，模块可以将主数据总线上的数据与每个模块中的辅助总线上的数据进行比较，以便确定是否存在指示硬件故障的不一致。如果检测到这种不一致，则每个模块产生反映特定模块是故障源的概率的状态输出。与主数据总线分离的同步总线将中央处理模块互连，并将每个模块的状态输出传送到每个其他中央处理模块。

9. 发明授权

US6038684A System and method for diagnosing errors in a multiprocessor system 有权
标题翻译：用于诊断多处理器系统中的错误的系统和方法
公开(公告)号：US6038684A
公开(公告)日：2000-03-14
申请号：US273778
申请日：1999-03-22
申请人： David C. Liddell , Emrys J. Williams
发明人： David C. Liddell , Emrys J. Williams
IPC分类号： G06F11/16 , G05B9/02 , G06F1/26 , G06F11/00 , G06F11/07 , G06F11/10 , G06F11/14 , G06F11/20 , G06F13/00 , H02H3/05 , H03K19/003 , H03K19/007
CPC分类号： G06F11/1654 , G06F11/0709 , G06F11/1604 , G06F11/165 , G06F11/1658 , G06F11/181 , G06F11/185 , G06F11/079 , G06F11/10 , G06F11/1415 , G06F11/1645 , G06F11/1679 , G06F11/20
摘要： A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules. Each central processing module contains a means by which the module can compare data on the main data bus with data on a secondary bus within each module in order to determine if there is an inconsistency indicating a hardware fault. If such an inconsistency is detected, each module generates state outputs which reflect the probability that a particular module is the source of the fault. A synchronization bus which is separate from the main data bus interconnects the central processing modules and transmits the state outputs from each module to every other central processing module.
摘要翻译：描述了容错计算机体系结构，其中硬件故障的影响减弱。该架构采用具有用于互连常规计算机子系统的多个接口槽的主数据总线。子系统的数量和类型可能会有很大变化，但是，包含本发明的创造性要素的中央处理器子系统总是包括在内。中央处理器子系统采用以基本上同步的方式并行操作的多个中央处理模块。中央处理模块之一作为主中央处理模块，是能够从主数据总线读取数据并将数据写入主数据总线的唯一模块。主中央处理模块最初是从中央处理模块中任意选择的。每个中央处理模块包含一个装置，通过该装置，模块可以将主数据总线上的数据与每个模块中的辅助总线上的数据进行比较，以便确定是否存在指示硬件故障的不一致。如果检测到这种不一致，则每个模块产生反映特定模块是故障源的概率的状态输出。与主数据总线分离的同步总线将中央处理模块互连，并将每个模块的状态输出传送到每个其他中央处理模块。

10. 发明授权

US10679452B2 Method and apparatus having multiple identifiers for use in making transactions 有权
公开(公告)号：US10679452B2
公开(公告)日：2020-06-09
申请号：US10654733
申请日：2003-09-04
申请人： Emrys J. Williams
发明人： Emrys J. Williams
IPC分类号： G07F7/10 , G06Q20/36 , G06Q20/34 , G06Q20/40 , G06Q20/24 , G07F7/12
摘要： A payment device is provided for use in transactions such as credit purchases at a retail store. The device includes a non-volatile memory containing a set of multiple identifiers that are associated with a customer account. The multiple identifiers are also known to an agency that provides the customer account. The device further includes a processor operable to select one identifier out of the set of multiple identifiers for use with any particular transaction involving the device and the customer account. This identifier is then conveyed from the device, typically via a store terminal, to the agency that maintains the account.

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