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    • 43. 发明授权
    • Memory programmable controller with word and bit processors
    • 具有字和位处理器的存储器可编程控制器
    • US4627025A
    • 1986-12-02
    • US568105
    • 1984-01-04
    • Peter NinnemannDieter Wollscheid
    • Peter NinnemannDieter Wollscheid
    • G06F9/45G05B19/05G06F9/38G06F15/16G06F15/177G06F15/46
    • G05B19/052
    • A memory-programmable controller of the multiprocessor type, has both a fast bit processor for processing bit oriented operations and a slower word processor for processing word oriented operations. The bit and word operations are stored in a user program memory by the user. These operations are the program which controls the peripheral process controlled by the controller. The bit processor reads the user program memory and sequentially stops when a word command is recognized. The bit processor furnishes information which the word processor uses as the entry address for a program routine associated with the word command in an operating system memory. This provides freedom in the choice of the word processor and in the design of the bit processor to a high degree.
    • 多处理器类型的存储器可编程控制器具有用于处理面向位的操作的快速位处理器和用于处理面向字操作的较慢文字处理器。 位和字操作由用户存储在用户程序存储器中。 这些操作是控制由控制器控制的外围过程的程序。 位处理器读取用户程序存储器,并且当识别出单词命令时,该程序存储器依次停止。 位处理器提供字处理器使用的信息作为与操作系统存储器中的字命令相关联的程序例程的入口地址。 这提供了对字处理器的选择和在位处理器的高度设计中的自由度。
    • 46. 发明授权
    • Special function control system for a dual microprocessor programmable
process control system
    • 特殊功能控制系统,用于双微处理器可编程控制系统
    • US4215399A
    • 1980-07-29
    • US936532
    • 1978-08-24
    • Mark J. PavicicJack L. Mahaffey, II
    • Mark J. PavicicJack L. Mahaffey, II
    • G05B19/05G06F15/16G06F15/46
    • G05B19/052G05B2219/1204G05B2219/13001G05B2219/15048G05B2219/15127
    • An intelligent programmable process control system including a first microprocessor which scans and executes a sequence of boolean logic functions and a second microprocessor which performs complex operations including arithmetic computations beyond the capabilities of the first microprocessor. The first microprocessor transmits interrupt requests to the second microprocessor when a scanned sequence instruction requires complex operations to be performed. First flag bit register indicates to the first microprocessor that a requested operation has been queued-up. Second flag bit register indicates to the first microprocessor that the requested operation has been completed. When the first microprocessor requires complex operations, it checks the state of a respective first flag bit register to determine whether the complex operation has already been queued-up and if so, checks the state of a respective second flag bit register to determine whether the queued-up function has been completed by the second microprocessor. If the complex operation has been queued-up and the second flag bit indicates that the operation has not been completed, the first microprocessor continues scanning and executing its sequence of functions asynchronously with respect to the second microprocessor. If the first flag bit indicates that the operation has not been queued-up, then the first microprocessor transmits an interrupt request to the second microprocessor.
    • 一种智能可编程序过程控制系统,包括扫描并执行一系列布尔逻辑功能的第一微处理器,以及执行包括第一微处理器能力之外的算术计算的复杂操作的第二微处理器。 当扫描的序列指令需要执行复杂的操作时,第一个微处理器将中断请求发送到第二个微处理器。 第一标志位寄存器向第一微处理器指示所请求的操作已被排队。 第二标志位寄存器向第一微处理器指示所请求的操作已经完成。 当第一微处理器需要复杂的操作时,它检查相应的第一标志位寄存器的状态以确定复合操作是否已经被排队,如果是,则检查相应的第二标志位寄存器的状态以确定排队的 -up功能已由第二个微处理器完成。 如果复杂操作已排队,并且第二标志位指示操作尚未完成,则第一微处理器相对于第二微处理器继续扫描并执行其功能序列。 如果第一标志位指示操作尚未排队,则第一微处理器向第二微处理器发送中断请求。
    • 47. 发明授权
    • Random access memory with bit or byte addressing capability
    • 具有位或字节寻址能力的随机存取存储器
    • US4099253A
    • 1978-07-04
    • US722886
    • 1976-09-13
    • Philip G. Dooley, Jr.
    • Philip G. Dooley, Jr.
    • G05B19/05G06F12/04G11C7/00G11C8/00
    • G05B19/052G06F12/04G05B2219/15127
    • Disclosed is a random access memory particularly adapted for use in a programmable controller or other similar application wherein some data is preferably handled in the form of multi-bit words or bytes and other data is preferably handled in the form of single bits (one-bit words). The memory is comprised of at least one bank of chips or similar memory units each capable of storing one bit at each of a plurality (2.sup.N) of locations addressed through N address terminals. Through the agency of control signals, the chips of the bank may be accessed either in parallel to read or write a multi-bit word or individually to read or write a single bit.
    • 公开了一种特别适用于可编程控制器或其他类似应用的随机存取存储器,其中一些数据优选地以多位字或字节的形式处理,并且其他数据优选地以单位(1位)的形式 话)。 存储器包括至少一组芯片或类似的存储器单元,每个存储器单元能够通过N个地址端子寻址的多个(2N)个位置中的每一个存储一个位。 通过控制信号的代理,可以并行访问存储体的芯片,以读取或写入多位字或单独读取或写入单个位。