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41. 发明授权

US4931722A Flexible imbedded test system for VLSI circuits 失效
标题翻译：用于VLSI电路的灵活嵌入式测试系统
公开(公告)号：US4931722A
公开(公告)日：1990-06-05
申请号：US327938
申请日：1989-03-23
申请人： Susana Stoica
发明人： Susana Stoica
IPC分类号： G01R31/3185
CPC分类号： G01R31/318561 , G01R31/318536 , G01R31/318555
摘要： A logic chip contains a plurality of ranks of flip-flops with combinational logic elements connected in between the flip-flop ranks. Each flip-flop has at least two distinct data paths. The first path is for the normal passage of data to combinational logic units following the rank of flip-flops, and the second path is a test path which is connected directly with the next rank of flip-flops. Operands may be shifted in parallel to bypass combinational logic units and may be directed to selected combinational logic for test purposes. The flip-flops in a rank may be serially scanned or operate in parallel to send specific operands through selected combinational logic units. It is adaptable to custom or semi-custom VLSI chip design and it teaches that any "component" (for example, a logic unit or a single element) may be tested individually using two data paths (one for test and one for operation or normal data). The test data output can be transmitted in parallel between the flip flop ranks, or it can go serially through the flip flop components of a given rank.
摘要翻译：逻辑芯片包含多个触发器等级，其触发器等级之间连接有组合逻辑元件。每个触发器具有至少两个不同的数据路径。第一条路径是将数据正常通过触发器等级之后的组合逻辑单元，第二路径是直接与下一级触发器连接的测试路径。操作数可以并行移位以绕组合逻辑单元，并且可以被引导到用于测试目的的所选择的组合逻辑。等级中的触发器可以被串行扫描或并行操作，以通过所选择的组合逻辑单元发送特定的操作数。它适用于定制或半定制VLSI芯片设计，并且教导任何“组件”（例如，逻辑单元或单个元件）可以使用两个数据路径单独测试（一个用于测试，一个用于操作或正常数据）。测试数据输出可以在触发器等级之间并行发送，或者可以通过给定等级的触发器组件串行地传送。

42. 发明授权

US4799004A Transfer circuit for operation test of LSI systems 失效
标题翻译： LSI系统运行测试传输电路
公开(公告)号：US4799004A
公开(公告)日：1989-01-17
申请号：US148385
申请日：1988-01-25
申请人： Shojiro Mori
发明人： Shojiro Mori
IPC分类号： H03K19/00 , G01R31/28 , G01R31/3185 , G01R15/12
CPC分类号： G01R31/318561
摘要： A transfer circuit for the operation test of an LSI system inlcudes a mode setting section for selectively setting a first or second operation mode, a plurality of first shift register circuits connected to the input terminals of function blocks of the LSI system to respectively latch input data to the function blocks in a parallel fashion in the first operation mode and shift the input data in the second operation mode, a plurality of second shift register circuits connected to the output terminals of the function blocks of the LSI system to respectively latch output data of the function blocks in a parallel fashion in the first operation mode and shift the output data in the second operation mode, and a serial transfer line for serially connecting the first and second shift register circuits.
摘要翻译：用于LSI系统的操作测试的传送电路包括用于选择性地设置第一或第二操作模式的模式设置部分，连接到LSI系统的功能块的输入端的多个第一移位寄存器电路，以分别锁存输入数据在第一操作模式中以并行方式连接到功能块并在第二操作模式中移位输入数据，多个第二移位寄存器电路连接到LSI系统的功能块的输出端，以分别锁存该功能在第一操作模式中以并行方式块并且在第二操作模式中移位输出数据，以及用于串行连接第一和第二移位寄存器电路的串行传输线。

43. 发明授权

US10054637B2 Testing multi-core integrated circuit with parallel scan test data inputs and outputs 有权
公开(公告)号：US10054637B2
公开(公告)日：2018-08-21
申请号：US15254993
申请日：2016-09-01
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Zhiyong Hao , Yuliang Zhou , Yongfeng Zhu
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/317 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/31703 , G01R31/31713 , G01R31/31723 , G01R31/318561 , G01R31/318563 , G01R31/318572
摘要： Testing an integrated circuit (IC) that has a set of nominally similar cores and pairs of test data input (TDI) and test data output (TDO) pads common to the different cores. Similar scan chains in parallel in the different cores provide response signals as functions of corresponding TDI signals. Respective combined TDO signals are provided to the TDO pads. In the absence of a defect, the combined TDO signals are asserted and de-asserted like the response signals from corresponding chains in the different cores and like corresponding expected response signals. The combined TDO signals are different from the corresponding expected response signals in the presence of a defect in at least one of the cores. If the result is a fail, the ATE may identify a defective core using a diagnosis module in the IC providing response signals from a selected core.

44. 发明授权

US09791510B2 Circuit and method for diagnosing scan chain failures 有权
公开(公告)号：US09791510B2
公开(公告)日：2017-10-17
申请号：US14920718
申请日：2015-10-22
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Sandeep Kumar Goel
IPC分类号： G01R31/3185 , G01R31/3177
CPC分类号： G01R31/318541 , G01R31/3177 , G01R31/318536 , G01R31/318544 , G01R31/318561
摘要： A circuit includes a plurality of scan chains arranged in a ring network topology. Each scan chain includes a plurality of scan blocks, each of the plurality of scan blocks including a storage element and a switching device. Each switching device includes a first input configured to receive an output of a storage element in a different scan chain from the scan chain in which the switching device is disposed, and a second input configured to receive one of a function logic signal or a test scan signal. The switching device configured to selectively couple the first input or the second input to an input of the storage element.

45. 发明申请

US20170131351A1 TESTING MULTI-CORE INTEGRATED CIRCUIT WITH PARALLEL SCAN TEST DATA INPUTS AND OUTPUTS 审中-公开
公开(公告)号：US20170131351A1
公开(公告)日：2017-05-11
申请号：US15254993
申请日：2016-09-01
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： ZHIYONG HAO , YULIANG ZHOU , YONGFENG ZHU
IPC分类号： G01R31/3177 , G01R31/317
CPC分类号： G01R31/3177 , G01R31/31703 , G01R31/31713 , G01R31/31723 , G01R31/318561 , G01R31/318563 , G01R31/318572
摘要： Testing an integrated circuit (IC) that has a set of nominally similar cores and pairs of test data input (TDI) and test data output (TDO) pads common to the different cores. Similar scan chains in parallel in the different cores provide response signals as functions of corresponding TDI signals. Respective combined TDO signals are provided to the TDO pads. In the absence of a defect, the combined TDO signals are asserted and de-asserted like the response signals from corresponding chains in the different cores and like corresponding expected response signals. The combined TDO signals are different from the corresponding expected response signals in the presence of a defect in at least one of the cores. If the result is a fail, the ATE may identify a defective core using a diagnosis module in the IC providing response signals from a selected core.

46. 发明授权

US08935585B2 Tap controller having TMS, TCK, enable inputs and control outputs 有权
标题翻译：分接控制器具有TMS，TCK，使能输入和控制输出
公开(公告)号：US08935585B2
公开(公告)日：2015-01-13
申请号：US14258691
申请日：2014-04-22
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/318555 , G01R31/318558 , G01R31/318561 , G01R31/318563 , G01R31/318572
摘要： An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.
摘要翻译：集成电路可以具有多个核心电路，每个核心电路具有在IEEE标准1149.1中定义的测试访问端口。这些端口的访问和控制是一个测试链接模块。集成电路上的测试访问端口可以以一个测试链接模块来控制对多个辅助测试链接模块和测试访问端口的访问的层次结构。每个次级测试链接模块依次也可以控制对三级测试链接模块和测试访问端口的访问。测试链接模块也可用于仿真。

47. 发明授权

US08656235B2 Verifying and detecting boundary scan cells to input/output mapping 失效
标题翻译：验证和检测边界扫描单元到输入/输出映射
公开(公告)号：US08656235B2
公开(公告)日：2014-02-18
申请号：US13305498
申请日：2011-11-28
申请人： Benedikt Geukes , Matteo Michel , Carsten Schmitt , Manfred H. Walz
发明人： Benedikt Geukes , Matteo Michel , Carsten Schmitt , Manfred H. Walz
IPC分类号： G01R31/28
CPC分类号： G01R31/318572 , G01R31/318561
摘要： In some embodiments, a computer-implemented method includes receiving, in a processor, a device description code identifying components of a device and connections between the components, wherein some of the components and connections form boundary cells used for testing the device. The method can include processing, in the processor, the device description code to determine that the components and the connections meet a standard governing components and connections necessary for the boundary cells. The method can also include traversing the connections between the components to determine that the connections meet the standard, and reporting, via one or more output devices, that the device complies with the standard.
摘要翻译：在一些实施例中，计算机实现的方法包括在处理器中接收识别设备的组件和组件之间的连接的设备描述代码，其中组件和连接中的一些形成用于测试设备的边界单元。该方法可以包括在处理器中处理设备描述码以确定组件和连接满足边界单元所必需的标准控制组件和连接。该方法还可以包括遍历组件之间的连接以确定连接符合标准，并且经由一个或多个输出设备报告设备符合标准。

48. 发明申请

US20140013171A1 INTEGRATED DEFECT DETECTION AND LOCATION SYSTEMS AND METHODS IN SEMICONDUCTOR CHIP DEVICES 审中-公开
标题翻译：集成缺陷检测和位置系统和半导体芯片设备的方法
公开(公告)号：US20140013171A1
公开(公告)日：2014-01-09
申请号：US13541063
申请日：2012-07-03
申请人： Cheow Guan Lim , Giovanni Ferrara
发明人： Cheow Guan Lim , Giovanni Ferrara
IPC分类号： G01R31/3177
CPC分类号： G01R31/3187 , G01R31/318533 , G01R31/318558 , G01R31/318561 , G01R31/318563 , G01R31/318566 , G01R31/319 , G01R31/31903 , G01R31/31915
摘要： Embodiments relate to systems and methods for defect detection and localization in semiconductor chips. In an embodiment, a plurality of registers is arranged in a semiconductor chip. The particular number of registers can vary according to a desired level of localization, and the plurality of registers are geometrically distributed such that defect detection and localization over the entire chip area or a desired chip area, such as a central active region, is achieved in embodiments. In operation, a defect detection and localization routine can be run in parallel with other normal chip functions during a power-up or other phase. In embodiments, the registers can be multi-functional in that they can be used for other operational functions of the chip when not used for defect detection and localization, and vice-versa. Embodiments thereby provide fast, localized defect detection.
摘要翻译：实施例涉及用于半导体芯片中的缺陷检测和定位的系统和方法。在一个实施例中，多个寄存器布置在半导体芯片中。特定数量的寄存器可以根据所需的定位水平而变化，并且多个寄存器是几何分布的，使得在整个芯片区域或期望的芯片区域（例如中心有源区域）上的缺陷检测和定位在实施例。在运行中，缺陷检测和定位程序可以在上电或其他阶段与其他正常芯片功能并行运行。在实施例中，寄存器可以是多功能的，因为当不用于缺陷检测和定位时，它们可以用于芯片的其他操作功能，反之亦然。因此，实施例提供了快速的局部缺陷检测。

49. 发明授权

US08234529B2 HTMLS with first and second select outputs and enable inputs 有权
标题翻译：具有第一和第二选择输出和启用输入的HTMLS
公开(公告)号：US08234529B2
公开(公告)日：2012-07-31
申请号：US13103540
申请日：2011-05-09
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/318555 , G01R31/318558 , G01R31/318561 , G01R31/318563 , G01R31/318572
摘要： An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.
摘要翻译：集成电路可以具有多个核心电路，每个核心电路具有在IEEE标准1149.1中定义的测试访问端口。这些端口的访问和控制是一个测试链接模块。集成电路上的测试访问端口可以布置成层次结构，其中一个测试链接模块控制对多个次级测试链接模块和测试访问端口的访问。每个次级测试链接模块依次也可以控制对三级测试链接模块和测试访问端口的访问。测试链接模块也可用于仿真。

50. 发明申请

US20110279160A1 SEMICONDUCTOR DEVICE HAVING INPUT/OUTPUT WRAPPERS, AND A METHOD OF CONTROLLING THE WRAPPERS 有权
标题翻译：具有输入/输出封装的半导体器件和控制封装的方法
公开(公告)号：US20110279160A1
公开(公告)日：2011-11-17
申请号：US13107123
申请日：2011-05-13
申请人： JongPil Lee , Jae Young Lee , Mookyung Kang
发明人： JongPil Lee , Jae Young Lee , Mookyung Kang
IPC分类号： H03K3/00
CPC分类号： G01R31/318572 , G01R31/318561 , H03K19/17744
摘要： A semiconductor device include a first wrapper including a first scan flip-flop, first control flip-flops and a first pad, the first scan flip-flop receiving a first value and second values and storing the second value for determining a function of the first pad; a second wrapper including a second scan flip-flop, second control flip-flops and a second pad, the second scan flip-flop receiving the first value from the first wrapper and storing the first value for determining a function of the second pad; and an input/output controller configured to provide a shift input signal having the first and second values to the first wrapper.
摘要翻译：一种半导体器件包括：第一封装件，包括第一扫描触发器，第一控制触发器和第一焊盘，第一扫描触发器接收第一值和第二值，并存储用于确定第一值的功能的第二值垫; 包括第二扫描触发器，第二控制触发器和第二焊盘的第二封装件，所述第二扫描触发器从所述第一封装件接收所述第一值，并存储所述第一值以确定所述第二焊盘的功能; 以及输入/输出控制器，被配置为向第一包装提供具有第一和第二值的移位输入信号。

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