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41. 发明授权

US08681301B2 Liquid crystal on silicon display panel and method for manufacturing the same 有权
标题翻译：硅液晶显示面板及其制造方法
公开(公告)号：US08681301B2
公开(公告)日：2014-03-25
申请号：US13428019
申请日：2012-03-23
申请人： Ching-Huei Tsai
发明人： Ching-Huei Tsai
IPC分类号： G02F1/1345 , G02F1/136
CPC分类号： G02F1/136277 , G02F1/13452 , G02F2201/38
摘要： A liquid crystal on silicon display panel and a method for manufacturing the same are disclosed. The method includes the following steps. First, a semiconductor substrate having a pixel region with at least one first top metal pattern and a first anti-reflection coating structure substantially disposed thereon and a circuit region with is at least one second top metal pattern and a second anti-reflection coating structure substantially disposed thereon is provided. Moreover, the circuit region surrounds the pixel region. Next, the first anti-reflection coating structure is removed. Afterward, a dielectric layer is formed on the semiconductor substrate and covering the first top metal pattern. Then, a passivation layer is formed on the dielectric layer. After that, a portion of the passivation layer and a portion of the second anti-reflection coating structure thereunder are removed to form an opening exposing a portion of the second top metal pattern.
摘要翻译：公开了一种硅液晶显示面板及其制造方法。该方法包括以下步骤。首先，具有具有至少一个第一顶部金属图案的像素区域和基本上设置在其上的第一防反射涂层结构的半导体衬底和具有至少一个第二顶部金属图案和第二防反射涂层结构的电路区域，设置在其上。此外，电路区域围绕像素区域。接下来，去除第一防反射涂层结构。之后，在半导体衬底上形成介电层并覆盖第一顶部金属图案。然后，在电介质层上形成钝化层。之后，去除钝化层的一部分和其下面的第二抗反射涂层结构的一部分，以形成露出第二顶部金属图案的一部分的开口。

42. 发明申请

US20140035070A1 METAL OXIDE SEMICONDUCTOR TRANSISTOR 审中-公开
标题翻译：金属氧化物半导体晶体管
公开(公告)号：US20140035070A1
公开(公告)日：2014-02-06
申请号：US14045798
申请日：2013-10-04
申请人： UNITED MICROELECTRONICS CORPORATION
发明人： Tsuo-Wen Lu , Tzung-Ying Lee , Jei-Ming Chen , Chun-Wei Hsu , Yu-Min Lin , Chia-Lung Chang , Chin-Cheng Chien , Shu-Yen Chan
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L21/28088 , H01L21/823842 , H01L21/823864 , H01L29/4966 , H01L29/513 , H01L29/66545 , H01L29/66553 , H01L29/6659 , H01L29/7833
摘要： A MOS transistor including a silicon substrate, a first gate structure and a second gate structure disposed on the silicon substrate is provided. The first gate structure and the second gate structure each includes a high-k dielectric layer disposed on the silicon substrate, a barrier layer disposed on the high-k dielectric layer, and a work function layer disposed on and contacted with the barrier layer. The MOS transistor further includes a dielectric material spacer. The dielectric material spacer is disposed on the barrier layer of each of the first gate structure and the second gate structure and surrounding the work function layer of each of the first gate structure and the second gate structure.
摘要翻译：提供了一种MOS晶体管，其包括硅衬底，设置在硅衬底上的第一栅极结构和第二栅极结构。第一栅极结构和第二栅极结构各自包括设置在硅衬底上的高k电介质层，设置在高k电介质层上的阻挡层和设置在阻挡层上并与阻挡层接触的功函数层。 MOS晶体管还包括电介质材料间隔物。电介质材料间隔物设置在第一栅极结构和第二栅极结构中的每一个的势垒层上并且围绕第一栅极结构和第二栅极结构中的每一个的功函数层。

43. 发明授权

US08642485B2 Method for fabricating patterned polyimide film and applications thereof 有权
标题翻译：图案化聚酰亚胺膜的制造方法及其应用
公开(公告)号：US08642485B2
公开(公告)日：2014-02-04
申请号：US13517804
申请日：2012-06-14
申请人： Chin-Yi Lin
发明人： Chin-Yi Lin
IPC分类号： H01L21/302
CPC分类号： H04R19/04 , B81B2201/0257 , B81C1/00182 , C09D179/08 , G01H11/00 , H01L21/31058 , H01L21/31144 , H04R19/005 , H04R31/00
摘要： A method for fabricating a patterned polyimide film, wherein the method comprises steps as follows: Firstly, a polyimide film is provided on a substrate. A wet planarization process is then performed to remove a portion of the polyimide film. Subsequently the planarized polyimide film is patterned.
摘要翻译：一种图案化聚酰亚胺膜的制造方法，其特征在于，该方法包括以下步骤：首先，在基板上设置聚酰亚胺膜。然后进行湿平坦化处理以去除一部分聚酰亚胺膜。随后平面化的聚酰亚胺膜被图案化。

44. 发明申请

US20130330919A1 MANUFACTURING PROCESS OF GATE STACK STRUCTURE WITH ETCH STOP LAYER 有权
公开(公告)号：US20130330919A1
公开(公告)日：2013-12-12
申请号：US13960812
申请日：2013-08-07
申请人： UNITED MICROELECTRONICS CORPORATION
发明人： Kun-Hsien LIN , Hsin-Fu Huang , Chi-Mao Hsu , Chin-Fu Lin , Chun-Yuan Wu
IPC分类号： H01L21/28 , H01L29/40
CPC分类号： H01L21/31144 , H01L21/28008 , H01L29/401 , H01L29/4966 , H01L29/66545 , H01L29/78
摘要： A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench.

45. 发明申请

US20130323908A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130323908A1
公开(公告)日：2013-12-05
申请号：US13483129
申请日：2012-05-30
申请人： Chine-Li WANG , Chun-Yen Chen , Wei-Hua Fang , Hung-Hsien Chang , Yung-Chin Yen
发明人： Chine-Li WANG , Chun-Yen Chen , Wei-Hua Fang , Hung-Hsien Chang , Yung-Chin Yen
IPC分类号： H01L21/78
CPC分类号： B81C1/00873 , H01L21/78
摘要： A method for fabricating a semiconductor device, wherein the method comprises steps as follows: Firstly, a device wafer is provided and a patterned bonding layer is then formed within a scribe line region of the device wafer. Subsequently a handle wafer is bonded to the device wafer by the patterned bonding layer. Next, a dicing process is performed along the scribe line region in order to divide the device wafer into a plurality of dices and remove the patterned bonding layer simultaneously, whereby the divided dices can be separated from the handle wafer.
摘要翻译：一种制造半导体器件的方法，其中所述方法包括以下步骤：首先，提供器件晶片，然后在器件晶片的划线区域内形成图案化结合层。随后，通过图案化的接合层将处理晶片结合到器件晶片。接下来，沿着划线区域进行切割处理，以便将器件晶片分成多个骰子并同时移除图案化的接合层，从而可以将分割的骰子与手柄晶片分离。

46. 发明申请

US20130248484A1 METHOD FOR FABRICATING PATTERNED DICHROIC FILM 有权
标题翻译：用于制作图案二色膜的方法
公开(公告)号：US20130248484A1
公开(公告)日：2013-09-26
申请号：US13427985
申请日：2012-03-23
申请人： Yi-Tyng WU
发明人： Yi-Tyng WU
IPC分类号： B05D5/06 , B44C1/22
CPC分类号： G02B5/201 , G02B5/285
摘要： A method for fabricating a patterned dichroic film is provided, wherein the method comprises steps as follows: A patterned material layer comprising at least one inorganic layer is firstly provided on a substrate. A film deposition process is then performed to form a dichroic film on the patterned material layer and the substrate. The patterned material layer is subsequently removed, whereby a portion of the dichroic film disposed on the patterned material layer can be removed simultaneously.
摘要翻译：提供了一种用于制造图案化二向色膜的方法，其中该方法包括以下步骤：首先在衬底上提供包含至少一个无机层的图案化材料层。然后进行膜沉积工艺以在图案化材料层和衬底上形成二向色膜。随后去除图案化的材料层，由此可以同时去除布置在图案化材料层上的二向色膜的一部分。

47. 发明申请

US20130240956A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130240956A1
公开(公告)日：2013-09-19
申请号：US13419530
申请日：2012-03-14
申请人： Hsin-Ming Hou , Yu-Cheng Tung , Ji-Fu Kung , Wai-Yi Lien , Ming-Tsung Chen
发明人： Hsin-Ming Hou , Yu-Cheng Tung , Ji-Fu Kung , Wai-Yi Lien , Ming-Tsung Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , H01L21/76224 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device including a substrate, a plurality of isolation structures, at least a gate structure, a plurality of dummy gate structures and a plurality of epitaxial structures is provided. The substrate has an active area defined by the isolation structures disposed within the substrate. That is, the active area is defined between the isolation structures. The gate structure is disposed on the substrate and located within the active area. The dummy gate structures are disposed on the substrate and located out of the active area. The edge of each dummy gate structure is separated from the boundary of the active area with a distance smaller than 135 angstroms. The epitaxial structures are disposed within the active area and in a portion of the substrate on two sides of the gate structure. The invention also provided a method for fabricating semiconductor device.
摘要翻译：提供了包括衬底，多个隔离结构，至少栅极结构，多个虚拟栅极结构和多个外延结构的半导体器件。衬底具有由设置在衬底内的隔离结构限定的有源区。也就是说，在隔离结构之间限定有源区。栅极结构设置在基板上并且位于有源区域内。虚拟栅极结构设置在基板上并且位于有源区域之外。每个虚拟栅极结构的边缘与有效区域的边界分开，距离小于135埃。外延结构被布置在栅极结构的两侧的有源区域内和衬底的一部分中。本发明还提供了一种制造半导体器件的方法。

48. 发明申请

US20130208379A1 ELECTROSTATIC DISCHARGE PROTECTION APPARATUS 有权
标题翻译：静电放电保护装置
公开(公告)号：US20130208379A1
公开(公告)日：2013-08-15
申请号：US13369455
申请日：2012-02-09
申请人： Chang-Tzu WANG , Tien-Hao TANG , Kuan-Cheng SU
发明人： Chang-Tzu WANG , Tien-Hao TANG , Kuan-Cheng SU
IPC分类号： H02H9/04
CPC分类号： H01L27/0262 , H01L29/7436 , H01L29/87
摘要： A semiconductor ESD protection apparatus comprises a substrate; a first doped well disposed in the substrate and having a first conductivity; a first doped area having the first conductivity disposed in the first doped well; a second doped area having a second conductivity disposed in the first doped well; and an epitaxial layer disposed in the substrate, wherein the epitaxial layer has a third doped area with the first conductivity and a fourth doped area with the second conductivity separated from each other. Whereby a first bipolar junction transistor (BJT) equivalent circuit is formed between the first doped area, the first doped well and the third doped area; a second BJT equivalent circuit is formed between the second doped area, the first doped well and the fourth doped area; and the first BJT equivalent circuit and the second BJT equivalent circuit have different majority carriers.
摘要翻译：半导体ESD保护装置包括基板; 第一掺杂阱，其设置在所述衬底中并且具有第一导电性; 具有第一导电性的第一掺杂区域设置在第一掺杂阱中; 第二掺杂区域，具有设置在第一掺杂阱中的第二导电体; 以及设置在所述衬底中的外延层，其中所述外延层具有具有第一导电性的第三掺杂区域和具有第二导电性的第四掺杂区域彼此分离。由此在第一掺杂区，第一掺杂阱和第三掺杂区之间形成第一双极结型晶体管（BJT）等效电路; 在第二掺杂区，第一掺杂阱和第四掺杂区之间形成第二BJT等效电路; 并且第一BJT等效电路和第二BJT等效电路具有不同的多数载波。

49. 发明申请

US20130182519A1 MEMORY DEVICE AND VOLTAGE INTERPRETING METHOD FOR READ BIT LINE 有权
标题翻译：用于读取位线的存储器件和电压解码方法
公开(公告)号：US20130182519A1
公开(公告)日：2013-07-18
申请号：US13352411
申请日：2012-01-18
申请人： Shi-Wen CHEN , Tsan-Tang Chen , Chi-Chang Shuai
发明人： Shi-Wen CHEN , Tsan-Tang Chen , Chi-Chang Shuai
IPC分类号： G11C7/12
CPC分类号： G11C7/12 , G11C7/14
摘要： A memory device comprises a memory cell array, a first and a second pre-charging switch circuits, a selecting circuit, an auxiliary memory cell array, a dynamic voltage controller and a sense amplifier. The auxiliary memory cell array comprises an auxiliary read bit line and a plurality of memory cells arranged in a column and electrically connected to the auxiliary read bit line. The second pre-charging switch circuit determines whether or not to supply a reference voltage to each of the aforementioned memory cells according to a pre-charging control signal. The dynamic voltage controller determines whether or not to supply a voltage to the auxiliary read bit line according to the voltage level of the output signal of the selecting circuit. The sense amplifier compares the voltage levels of the output signal of the selecting circuit and the voltage on the auxiliary read bit line to output a sensing result accordingly.
摘要翻译：存储器件包括存储单元阵列，第一和第二预充电开关电路，选择电路，辅助存储单元阵列，动态电压控制器和读出放大器。辅助存储单元阵列包括辅助读位线和布置在列中并电连接到辅助读位线的多个存储单元。第二预充电开关电路根据预充电控制信号来确定是否向每个上述存储单元提供参考电压。动态电压控制器根据选择电路的输出信号的电压决定是否向辅助读取位线提供电压。读出放大器将选择电路的输出信号的电压电平和辅助读取位线上的电压进行比较，从而相应地输出感测结果。

50. 发明授权

US08482063B2 High voltage semiconductor device 有权
标题翻译：高压半导体器件
公开(公告)号：US08482063B2
公开(公告)日：2013-07-09
申请号：US13299446
申请日：2011-11-18
申请人： An-Hung Lin , Hong-Ze Lin , Bo-Jui Huang , Wei-Shan Liao , Ting-Zhou Yan , Wei-Chun Chang , Chun-Yao Lee , Kun-Yi Chou
发明人： An-Hung Lin , Hong-Ze Lin , Bo-Jui Huang , Wei-Shan Liao , Ting-Zhou Yan , Wei-Chun Chang , Chun-Yao Lee , Kun-Yi Chou
IPC分类号： H01L29/66
CPC分类号： H01L29/0696 , H01L29/0634 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/4238 , H01L29/7816 , H01L29/7835
摘要： A high voltage semiconductor device is provided. A first-polarity buried layer is formed in the substrate. A first high voltage second-polarity well region is located over the first-polarity buried layer. A second-polarity base region is disposed within the first high voltage second-polarity well region. A source region is disposed within the second-polarity base region. A high voltage deep first-polarity well region is located over the first-polarity buried layer and closely around the first high voltage second-polarity well region. A first-polarity drift region is disposed within the high voltage deep first-polarity well region. A gate structure is disposed over the substrate. A second high voltage second-polarity well region is located over the first-polarity buried layer and closely around the high voltage deep first-polarity well region. A deep first-polarity well region is located over the first-polarity buried layer and closely around the second high voltage second-polarity well region.
摘要翻译：提供高压半导体器件。在衬底中形成第一极性掩埋层。第一高电压第二极性阱区位于第一极性掩埋层的上方。第二极性基极区域设置在第一高电压第二极性阱区域内。源极区域设置在第二极性基极区域内。高电压深的第一极性极区位于第一极性埋层之上，紧邻第一高电压第二极性阱区。第一极性漂移区域设置在高电压深第一极性阱区域内。栅极结构设置在衬底上。第二高电压第二极性阱区域位于第一极性掩埋层上方并且紧邻高电压深第一极性阱区域。深第一极性阱区域位于第一极性掩埋层上并且紧邻第二高电压第二极性阱区域。

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