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41. 发明授权

US09543379B2 Semiconductor device with peripheral breakdown protection 有权
标题翻译：具有外围故障保护的半导体器件
公开(公告)号：US09543379B2
公开(公告)日：2017-01-10
申请号：US14218330
申请日：2014-03-18
申请人： Hongning Yang , Xin Lin , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Xin Lin , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/66 , H01L29/06 , H01L29/78 , H01L29/36 , H01L21/8234 , H01L27/12
CPC分类号： H01L29/063 , H01L21/76283 , H01L21/823418 , H01L21/823481 , H01L27/1203 , H01L29/0619 , H01L29/0649 , H01L29/0653 , H01L29/0688 , H01L29/0878 , H01L29/0886 , H01L29/1087 , H01L29/36 , H01L29/66659 , H01L29/66681 , H01L29/66689 , H01L29/7823 , H01L29/7824 , H01L29/7835
摘要： A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate and having a first conductivity type, a body region disposed in the semiconductor substrate, having a second conductivity type, and in which the source region is disposed, a drift region disposed in the semiconductor substrate, having the first conductivity type, and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions, a device isolation region disposed in the semiconductor substrate and laterally surrounding the body region and the drift region, and a breakdown protection region disposed between the device isolation region and the body region and having the first conductivity type.
摘要翻译：一种器件包括半导体衬底，设置在半导体衬底中并具有第一导电类型的源极和漏极区域，设置在半导体衬底中的体区，具有第二导电类型，并且其中设置源极区，漂移区设置在具有第一导电类型的半导体衬底中，并且在施加源极和漏极区域之间的偏置电压时，电荷载体在工作期间漂移，设置在半导体衬底中并横向围绕身体区域的器件隔离区域和漂移区域和设置在器件隔离区域和体区之间并具有第一导电类型的击穿保护区域。

42. 发明申请

US20150097238A1 Mergeable Semiconductor Device with Improved Reliability 有权
标题翻译：具有提高可靠性的可合并半导体器件
公开(公告)号：US20150097238A1
公开(公告)日：2015-04-09
申请号：US14047348
申请日：2013-10-07
申请人： Zhihong Zhang , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
发明人： Zhihong Zhang , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/66 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66659 , H01L21/26513 , H01L21/761 , H01L21/76224 , H01L21/823418 , H01L21/823481 , H01L27/088 , H01L29/0642 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1095 , H01L29/36 , H01L29/66575 , H01L29/6659 , H01L29/7833 , H01L29/7835 , H01L29/786 , H01L29/78615 , H01L29/78624 , H01L29/78654
摘要： A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite body region disposed in the semiconductor substrate and having a second conductivity type. The composite body region includes a first well region that extends laterally across the source and drain regions and a second well region disposed in the first well region. The drain region is disposed in the second well region such that charge carriers flow from the first well region into the second well region to reach the drain region. The second well region includes dopant of the first conductivity type to have a lower net dopant concentration level than the first well region. A pocket may be disposed in a drain extension region and configured to establish a depletion region along an edge of a gate structure.
摘要翻译：一种器件包括半导体衬底，设置在半导体衬底中的源极和漏极区域，具有第一导电类型，并且彼此横向间隔开;以及复合体区域，设置在半导体衬底中并且具有第二导电类型。复合体区域包括沿着源极和漏极区域横向延伸的第一阱区域和设置在第一阱区域中的第二阱区域。漏极区域设置在第二阱区域中，使得载流子从第一阱区域流入第二阱区域以到达漏极区域。第二阱区域包括具有比第一阱区域更低的净掺杂剂浓度水平的第一导电类型的掺杂剂。凹槽可以设置在漏极延伸区域中并且被配置成沿着栅极结构的边缘建立耗尽区域。

43. 发明申请

US20130292764A1 Semiconductor Device with Drain-End Drift Diminution 有权
标题翻译：具有排水端漂移的半导体器件
公开(公告)号：US20130292764A1
公开(公告)日：2013-11-07
申请号：US13465761
申请日：2012-05-07
申请人： Hongning Yang , Daniel J. Blomberg , Xu Cheng , Xin Lin , Won Gi Min , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Daniel J. Blomberg , Xu Cheng , Xin Lin , Won Gi Min , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/063 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate, a channel region in the semiconductor substrate between the source and drain regions through which charge carriers flow during operation from the source region to the drain region, and a drift region in the semiconductor substrate, on which the drain region is disposed, and through which the charge carriers drift under an electric field arising from application of a bias voltage between the source and drain regions. A PN junction along the drift region includes a first section at the drain region and a second section not at the drain region. The drift region has a lateral profile that varies such that the first section of the PN junction is shallower than the second section of the PN junction.
摘要翻译：一种器件包括半导体衬底，半导体衬底中的源极和漏极区域，在源极和漏极区域之间的半导体衬底中的沟道区域，电荷载体在从源极区域到漏极区域的工作期间流过该沟道区域，以及漂移区域其上设置有漏极区的半导体衬底，并且电荷载流子在源极和漏极区域之间施加偏压产生的电场下漂移。沿着漂移区域的PN结包括在漏极区域处的第一部分和不在漏极区域的第二部分。漂移区域具有变化的横向轮廓，使得PN结的第一部分比PN结的第二部分浅。

44. 发明申请

US20130285201A1 MIM CAPACITOR FORMATION METHOD AND STRUCTURE 审中-公开
标题翻译： MIM电容器形成方法和结构
公开(公告)号：US20130285201A1
公开(公告)日：2013-10-31
申请号：US13458947
申请日：2012-04-27
申请人： Zhihong Zhang , Xu Cheng , Todd C. Roggenbauer , Jiang-Kai Zuo
发明人： Zhihong Zhang , Xu Cheng , Todd C. Roggenbauer , Jiang-Kai Zuo
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L28/92 , H01L29/92
摘要： Metal-insulator metal (MIM) capacitors are formed by providing a substrate having a first surface, forming thereon a first electrode having conductive and insulating regions wherein the conductive regions desirably have an area density DA less than 100%. A first dielectric is formed over the first electrode. A cavity is formed in the first dielectric, having a sidewall extending to the first electrode and exposing thereon some of the first electrode conductive and insulating regions. An electrically conductive barrier layer is formed covering the sidewall and the some of the first electrode conductive and insulating regions. A capacitor dielectric layer is formed in the cavity covering the barrier layer. A counter electrode is formed in the cavity covering the capacitor dielectric layer. External connections are formed to a portion of the first electrode laterally outside the cavity and to the counter electrode within the cavity.
摘要翻译：通过提供具有第一表面的基板形成金属绝缘体金属（MIM）电容器，在其上形成具有导电和绝缘区域的第一电极，其中导电区域希望具有小于100％的面密度DA。第一电介质形成在第一电极上。在第一电介质中形成空腔，其具有延伸到第一电极并在其上暴露第一电极导电和绝缘区域的一些的侧壁。形成覆盖侧壁和一些第一电极导电绝缘区域的导电阻挡层。在覆盖阻挡层的空腔中形成电容器电介质层。在覆盖电容器介电层的空腔中形成对电极。外部连接形成在腔的横向外侧的第一电极的一部分和腔内的对电极。

45. 发明申请

US20100024013A1 Authenticating a Client Using Linked Authentication Credentials 有权
标题翻译：使用链接的身份验证凭据验证客户端
公开(公告)号：US20100024013A1
公开(公告)日：2010-01-28
申请号：US12575121
申请日：2009-10-07
申请人： Yan Cheng , Zhihong Zhang
发明人： Yan Cheng , Zhihong Zhang
IPC分类号： H04L29/06
CPC分类号： H04L63/08 , G06F21/41 , H04L9/3271 , H04L63/0428 , H04L63/18
摘要： Techniques are provided for improving security in a single-sign-on context by providing, to a user's client system, two linked authentication credentials in separate logical communication sessions and requiring that both credentials be presented to a host system. Only after presentation of both credentials is the user authenticated and permitted to access applications on the host system.
摘要翻译：提供技术用于通过在单独的逻辑通信会话中向用户的客户端系统提供两个链接的认证凭证并且要求将这两个凭证提供给主机系统来提高单点登录上下文中的安全性。只有在显示两个凭据之后，用户才能通过身份验证并允许访问主机系统上的应用程序。

46. 发明申请

US20050084619A1 Method to deposit an impermeable film on porous low-k dielectric film 审中-公开
标题翻译：在多孔低k电介质膜上沉积不渗透膜的方法
公开(公告)号：US20050084619A1
公开(公告)日：2005-04-21
申请号：US10963192
申请日：2004-10-12
申请人： Zhihong Zhang , Tai Nguyen , Tue Nguyen
发明人： Zhihong Zhang , Tai Nguyen , Tue Nguyen
IPC分类号： H01L21/285 , H01L21/316 , H01L21/318 , H01L21/768 , C23C16/00 , B05D3/04
CPC分类号： H01L21/76838 , H01L21/02203 , H01L21/28556 , H01L21/28568 , H01L21/3105
摘要： A method for improving the adhesion of an impermeable film on a porous low-k dielectric film in an interconnect structure is disclosed. The method provides an in-situ annealing step before the deposition of the impermeable film to release the volatile trapped molecules such as water, alcohol, HCl, and HF vapor, inside the pores of the porous low-k dielectric film. The method also provides an in-situ deposition step of the impermeable film right after the deposition of the porous low dielectric film without exposure to an atmosphere containing trappable molecules. The method further provides an in-situ deposition step of the impermeable film right after the removal a portion of the porous low-k dielectric film without exposure to an atmosphere containing trappable molecules. By the removal of all trapped molecules inside the porous low-k dielectric film, the adhesion between the deposited impermeable film and the low-k dielectric film is improved. This method is applicable to many porous low-k dielectric films such as porous hydrosilsesquioxane or porous methyl silsesquioxane, porous silica structures such as aerogel, low temperature deposited silicon carbon films, low temperature deposited Si—O—C films, and methyl doped porous silica.
摘要翻译：公开了一种用于改善互连结构中的多孔低k电介质膜上的不渗透膜的粘附性的方法。该方法提供在沉积不渗透膜以在多孔低k电介质膜的孔隙内释放挥发性捕获分子如水，醇，HCl和HF蒸气的原位退火步骤。该方法还提供了在不暴露于含有可捕获分子的气氛之后立即沉积多孔低介电膜之后的不渗透膜的原位沉积步骤。该方法进一步提供了在不暴露于含有可捕获分子的气氛之后移除多孔低k电介质膜的一部分之后的不渗透膜的原位沉积步骤。通过去除多孔低k电介质膜内的所有被捕获的分子，提高了沉积的不可渗透膜和低k电介质膜之间的粘附性。该方法适用于多孔低k介电膜，例如多孔氢硅倍半氧烷或多孔甲基硅倍半氧烷，多孔二氧化硅结构如气凝胶，低温沉积硅碳膜，低温沉积Si-O-C膜和甲基掺杂多孔二氧化硅。

47. 发明授权

US09640635B2 Reliability in mergeable semiconductor devices 有权
公开(公告)号：US09640635B2
公开(公告)日：2017-05-02
申请号：US14832139
申请日：2015-08-21
申请人： Zhihong Zhang , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
发明人： Zhihong Zhang , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L27/01 , H01L21/336 , H01L29/66 , H01L29/786 , H01L21/265 , H01L29/06 , H01L29/08 , H01L29/10 , H01L21/8234 , H01L29/36 , H01L27/088 , H01L21/761 , H01L21/762
CPC分类号： H01L29/66659 , H01L21/26513 , H01L21/761 , H01L21/76224 , H01L21/823418 , H01L21/823481 , H01L27/088 , H01L29/0642 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1095 , H01L29/36 , H01L29/66575 , H01L29/6659 , H01L29/7833 , H01L29/7835 , H01L29/786 , H01L29/78615 , H01L29/78624 , H01L29/78654
摘要： A method of fabricating a transistor device having a channel of a first conductivity type formed during operation in a body region having a second conductivity type includes forming a first well region of the body region in a semiconductor substrate, performing a first implantation procedure to counter-dope the first well region with dopant of the first conductivity type to define a second well region of the body region, and performing a second implantation procedure to form a source region in the first well region and a drain region in the second well region.

48. 发明授权

US09490322B2 Semiconductor device with enhanced 3D resurf 有权
标题翻译：具有增强3D复现功能的半导体器件
公开(公告)号：US09490322B2
公开(公告)日：2016-11-08
申请号：US13748076
申请日：2013-01-23
申请人： Hongning Yang , Xin Lin , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Xin Lin , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/94 , H01L29/08 , H01L29/78 , H01L29/06 , H01L29/10
CPC分类号： H01L29/66681 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/0847 , H01L29/1045 , H01L29/1095 , H01L29/7835
摘要： A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region.
摘要翻译：一种器件包括半导体衬底，半导体衬底中的源极和漏极区域以及沿着第一横向尺寸彼此间隔开的半导体衬底中的漂移区域，并且在施加偏置电压之前电荷载体在操作期间漂移源极和漏极区域。漂移区域沿着漂移区域和漏极区域之间的界面在第二横向维度上具有缺口掺杂剂分布。

49. 发明申请

US20150325565A1 Composite Semiconductor Device with Multiple Threshold Voltages 有权
标题翻译：具有多个阈值电压的复合半导体器件
公开(公告)号：US20150325565A1
公开(公告)日：2015-11-12
申请号：US14272027
申请日：2014-05-07
申请人： Hongning Yang , Xin Lin , Pete Rodriguez , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Xin Lin , Pete Rodriguez , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L27/02 , H01L29/08 , H01L21/265 , H01L29/66 , H01L27/088 , H01L21/8234 , H01L29/78 , H01L29/10
CPC分类号： H01L27/0248 , H01L21/26513 , H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L27/0266 , H01L27/088 , H01L29/0653 , H01L29/0696 , H01L29/0865 , H01L29/0882 , H01L29/1045 , H01L29/1079 , H01L29/1095 , H01L29/66575 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. Each transistor structure of the first plurality of transistor structures includes a non-uniform channel such that the first constituent transistor has a higher threshold voltage level than the second constituent transistor.
摘要翻译：一种器件包括半导体衬底，第一组成晶体管，其包括彼此并联连接的半导体衬底中的第一多个晶体管结构;以及第二组成晶体管，包括在半导体衬底中并联连接的第二多个晶体管结构，另一个。第一和第二组成晶体管彼此横向相邻设置并彼此并联连接。第一多个晶体管结构的每个晶体管结构包括非均匀沟道，使得第一构成晶体管具有比第二构成晶体管更高的阈值电压电平。

50. 发明授权

US09117841B2 Mergeable semiconductor device with improved reliability 有权
标题翻译：合并半导体器件具有可靠性提高
公开(公告)号：US09117841B2
公开(公告)日：2015-08-25
申请号：US14047348
申请日：2013-10-07
申请人： Zhihong Zhang , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
发明人： Zhihong Zhang , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L27/01 , H01L21/336 , H01L29/66 , H01L29/786
CPC分类号： H01L29/66659 , H01L21/26513 , H01L21/761 , H01L21/76224 , H01L21/823418 , H01L21/823481 , H01L27/088 , H01L29/0642 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1095 , H01L29/36 , H01L29/66575 , H01L29/6659 , H01L29/7833 , H01L29/7835 , H01L29/786 , H01L29/78615 , H01L29/78624 , H01L29/78654
摘要： A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite body region disposed in the semiconductor substrate and having a second conductivity type. The composite body region includes a first well region that extends laterally across the source and drain regions and a second well region disposed in the first well region. The drain region is disposed in the second well region such that charge carriers flow from the first well region into the second well region to reach the drain region. The second well region includes dopant of the first conductivity type to have a lower net dopant concentration level than the first well region. A pocket may be disposed in a drain extension region and configured to establish a depletion region along an edge of a gate structure.
摘要翻译：一种器件包括半导体衬底，设置在半导体衬底中的源极和漏极区域，具有第一导电类型，并且彼此横向间隔开;以及复合体区域，设置在半导体衬底中并且具有第二导电类型。复合体区域包括沿着源极和漏极区域横向延伸的第一阱区域和设置在第一阱区域中的第二阱区域。漏极区域设置在第二阱区域中，使得载流子从第一阱区域流入第二阱区域以到达漏极区域。第二阱区域包括具有比第一阱区域更低的净掺杂剂浓度水平的第一导电类型的掺杂剂。凹槽可以设置在漏极延伸区域中并且被配置成沿着栅极结构的边缘建立耗尽区域。

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