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    • 41. 发明授权
    • Coated hard alloy
    • 涂层硬质合金
    • US06756111B1
    • 2004-06-29
    • US09980820
    • 2001-12-07
    • Yoshio OkadaHideki MoriguchiAkihiko Ikegaya
    • Yoshio OkadaHideki MoriguchiAkihiko Ikegaya
    • B32B900
    • C23C30/005C23C16/36Y10T428/24364Y10T428/24628Y10T428/24975Y10T428/265
    • A coated hard metal which has high resistance against wear, chipping, welding, and flaking is offered. The coated hard metal is provided with an inner layer, intermediate layer, and outer layer on the surface of the hard metal. The inner layer includes a layer comprising at least one member selected from the group consisting of (a) the carbides, nitrides, borides, and oxides of the elements belonging to the IVa, Va, and VIa groups in the periodic table and (b) the solid solutions of these. The intermediate layer includes a layer comprising at least one member selected from the group consisting of aluminum oxide, zirconium oxide, and their solid solution. The outer layer includes a layer of titanium carbonitride having a columnar structure. In a cross section showing the structure of the coated hard metal, the relation between “Amax,” which signifies the maximum roughness at the outer face of the intermediate layer, and “Bmax,” which signifies the maximum roughness at the outer face of the layer carbonitride having a columnar structure in the outer layer, satisfies equation 1. (BmaxfAmax)
    • 提供了耐磨损,切屑,焊接和剥落的高耐磨性的涂层硬质合金。 涂覆的硬金属在硬金属表面上设置有内层,中间层和外层。 内层包括包含选自(a)属于周期表中的IVa,Va和VIa族的元素的碳化物,氮化物,硼化物和氧化物中的至少一种的层,和(b) 这些的固体解决方案。 中间层包括包含选自氧化铝,氧化锆及其固溶体中的至少一种的层。 外层包括具有柱状结构的碳氮化钛层。 在表示涂覆的硬质合金的结构的剖视图中,表示中间层的外表面的最大粗糙度的“Amax”和“Bmax”之间的关系,其表示外表面的最大粗糙度 在外层中具有柱状结构的层碳氮化物满足等式1.其中0.5μm
    • 44. 发明授权
    • Semiconductor memory device having redundancy memory cells
    • 具有冗余存储单元的半导体存储器件
    • US5357470A
    • 1994-10-18
    • US35196
    • 1993-03-22
    • Toshimasa NamekawaYoshio Okada
    • Toshimasa NamekawaYoshio Okada
    • G11C11/413G11C11/401G11C29/00G11C29/04H01L21/822H01L27/04H01L27/10G11C7/00
    • G11C29/84
    • A semiconductor memory device includes a plurality of memory cell arrays, a plurality of decoders for decoding a first address of memory addresses, each of the decoders being connected to a corresponding memory cell array, and a plurality of sense amplifiers, each connected to a corresponding memory cell array. Also included are a decoder for decoding a second address of the memory addresses, the decoder being connected to every memory cell array, to be shared by every memory cell array, a plurality of redundancy memory cells, each of which is arranged for a corresponding memory cell array, and a plurality of programming circuits, each, arranged relative to a corresponding memory cell array to receive the first memory address and output a signal of a predetermined logic level corresponding to a defective memory cell in a memory cell array. Further, there is included a programmable decoder for receiving the second address and signal from the programming circuits, for changing a decoding state of the second address according to the logic level of the output signal from the programming circuits and for outputting a redundancy memory cell select signal which selects a redundancy memory cell in place of a specified defective memory cell.
    • 半导体存储器件包括多个存储单元阵列,多个解码器,用于解码存储器地址的第一地址,每个解码器连接到相应的存储单元阵列,以及多个读出放大器,每个读出放大器连接到相应的 存储单元阵列。 还包括解码器,用于对存储器地址的第二地址进行解码,解码器连接到每个存储单元阵列,由每个存储单元阵列共享;多个冗余存储单元,每个冗余存储单元被布置用于相应的存储器 单元阵列和多个编程电路,每个编程电路相对于相应的存储单元阵列布置以接收第一存储器地址,并且输出与存储单元阵列中的有缺陷的存储单元相对应的预定逻辑电平的信号。 此外,包括用于从编程电路接收第二地址和信号的可编程解码器,用于根据来自编程电路的输出信号的逻辑电平改变第二地址的解码状态,并输出冗余存储单元选择 信号,其选择冗余存储单元来代替指定的有缺陷的存储单元。