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41. 发明申请

US20100176451A1 Semiconductor 有权
标题翻译：半导体
公开(公告)号：US20100176451A1
公开(公告)日：2010-07-15
申请号：US12683179
申请日：2010-01-06
申请人： Hoon Jeong , Yong-Chul Oh , Sung-In Hong , Sung-Hwan Kim , Yong-Lack Choi , Ho-Ju Song
发明人： Hoon Jeong , Yong-Chul Oh , Sung-In Hong , Sung-Hwan Kim , Yong-Lack Choi , Ho-Ju Song
IPC分类号： H01L29/78
CPC分类号： H01L27/108 , H01L27/10802 , H01L29/7841
摘要： A memory device includes an insulation layer, an active pattern, a gate insulation layer and a gate electrode. The insulation layer is formed on a substrate. The active pattern is formed on the insulation layer, and includes two protrusions and a recess between the protrusions. The active pattern includes a first impurity region and a second impurity region at upper portions of the protrusions distal from the substrate, respectively, and a base region at the other portions serving as a floating body for storing data. The gate insulation layer is formed on a surface of the active pattern. The gate electrode is formed on the gate insulation layer, and surrounds a lower portion of the active pattern and partially fills the recess.
摘要翻译：存储器件包括绝缘层，有源图案，栅极绝缘层和栅电极。绝缘层形成在基板上。活性图案形成在绝缘层上，并且在突起之间包括两个突起和凹部。有源图案分别在远离基板的突起的上部分别包括第一杂质区域和第二杂质区域，以及用作用于存储数据的浮体的其它部分的基极区域。栅极绝缘层形成在活性图案的表面上。栅电极形成在栅绝缘层上，并且围绕有源图案的下部并且部分地填充凹部。

42. 发明授权

US06372606B1 Method of forming isolation trenches in a semiconductor device 失效
标题翻译：在半导体器件中形成隔离沟槽的方法
公开(公告)号：US06372606B1
公开(公告)日：2002-04-16
申请号：US09368426
申请日：1999-08-05
申请人： Yong-Chul Oh
发明人： Yong-Chul Oh
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： A method of forming an isolation trench in a semiconductor substrate includes the steps of sequentially depositing first and second insulating layers over the substrate, subsequently etching the second and first insulating layers to define active and non-active regions according to a patterned masking photoresist layer, excessively etching a part of the thickness of the substrate, removing parts of the first insulating layer by undercutting the sides of the non-active region so as to expose parts of the substrate in the active region, etching the substrate by using the second insulating layer as a trench patterned masking layer to form a trench in which the edges of the exposed parts of the substrate are rounded, depositing a third insulating layer on the bottom and side walls of the trench and the rounded parts of the substrate to repair the parts of the substrate damaged when forming the trench, depositing a fourth insulating layer over the second insulating layer so as to completely fill the trench, etching the fourth and second insulating layers plane until a part of the thickness of the second insulating layer is exposed so as to generate the trench isolation region, and sequentially removing the second and first insulating layers along the sides of the isolation trench.
摘要翻译：在半导体衬底中形成隔离沟槽的方法包括以下步骤：在衬底上依次沉积第一和第二绝缘层，随后蚀刻第二和第一绝缘层以根据图案化掩模光致抗蚀剂层限定有源和非有源区，过度蚀刻基板的一部分厚度，通过对非有源区的侧面进行底切而去除部分第一绝缘层，以便使有源区中的基板部分露出，通过使用第二绝缘层蚀刻基板作为沟槽图案化掩模层以形成沟槽，其中衬底的暴露部分的边缘是圆形的，在沟槽的底部和侧壁以及衬底的圆形部分上沉积第三绝缘层以修复衬底在形成沟槽时损坏，在第二绝缘层上沉积第四绝缘层以完全地形成填充沟槽，蚀刻第四绝缘层和第二绝缘层平面，直到露出第二绝缘层的厚度的一部分，以便产生沟槽隔离区域，并且沿隔离沟槽的侧面依次移除第二绝缘层和第一绝缘层。

43. 发明授权

US07872302B2 Semiconductor device having vertical transistor formed on an active pattern protruding from a substrate 有权
标题翻译：具有垂直晶体管的半导体器件形成在从衬底突出的有源图案上
公开(公告)号：US07872302B2
公开(公告)日：2011-01-18
申请号：US12014370
申请日：2008-01-15
申请人： Hui-Jung Kim , Jae-Man Yoon , Yong-Chul Oh , Hyun-Woo Chung
发明人： Hui-Jung Kim , Jae-Man Yoon , Yong-Chul Oh , Hyun-Woo Chung
IPC分类号： H01L29/78 , H01L21/335
CPC分类号： H01L29/66666 , H01L29/7827
摘要： A semiconductor device includes a first active pattern protruding from a substrate, a second active pattern on the first active pattern, a gate electrode enclosing a sidewall of the second active pattern, a conductive layer pattern on the first active pattern, a first impurity region in the first active pattern, and a second impurity region at a surface portion of the second active pattern. The first active pattern extending along a predetermined direction may have a first region and a second region. The second active pattern may have a pillar structure and the conductive layer pattern may include a metal or a metal compound.
摘要翻译：半导体器件包括从衬底突出的第一有源图案，第一有源图案上的第二有源图案，封闭第二有源图案的侧壁的栅极电极，第一有源图案上的导电层图案，第一有源图案上的第一杂质区域第一有源图案和第二有源图案的表面部分处的第二杂质区域。沿着预定方向延伸的第一有源图案可以具有第一区域和第二区域。第二活性图案可以具有柱结构，并且导电层图案可以包括金属或金属化合物。

44. 发明申请

US20100159650A1 Methods of fabricating semiconductor device having capacitorless one-transistor memory cell 有权
标题翻译：制造具有无电容的单晶体管存储单元的半导体器件的方法
公开(公告)号：US20100159650A1
公开(公告)日：2010-06-24
申请号：US12654333
申请日：2009-12-17
申请人： Ho-Ju Song , Sung-Hwan Kim , Yong-Chul Oh
发明人： Ho-Ju Song , Sung-Hwan Kim , Yong-Chul Oh
IPC分类号： H01L21/782
CPC分类号： H01L29/7841 , H01L27/108 , H01L27/10802 , H01L27/10894
摘要： A method of fabricating a semiconductor device having a capacitorless one-transistor memory cell includes forming a first floating body pattern on a lower insulating layer of a substrate and a first gate pattern crossing over the first floating body pattern and covering sidewalls of the first floating body pattern is formed. The first floating body pattern at both sides of the first gate pattern is partially etched to form a protrusion portion extending between and above the partially etched regions, and first impurity regions are formed in the partially etched regions of the first floating body pattern.
摘要翻译：一种制造具有无电容的一晶体管存储单元的半导体器件的方法包括在衬底的下绝缘层上形成第一浮体图案和在第一浮体图案上交叉并覆盖第一浮体的侧壁的第一栅极图案形成图案。第一栅极图案的两侧的第一浮体图案被部分地蚀刻以形成在部分蚀刻区域之间和之上延伸的突出部分，并且第一杂质区域形成在第一浮体图案的部分蚀刻区域中。

45. 发明申请

US20050042832A1 Method of fabricating transistor of DRAM semiconductor device 有权
标题翻译：制造DRAM半导体器件晶体管的方法
公开(公告)号：US20050042832A1
公开(公告)日：2005-02-24
申请号：US10922055
申请日：2004-08-18
申请人： Yong-Chul Oh , Wook-Je Kim , Nak-Jin Son , Se-Myeong Jang , Gyo-Young Jin
发明人： Yong-Chul Oh , Wook-Je Kim , Nak-Jin Son , Se-Myeong Jang , Gyo-Young Jin
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8238 , H01L21/8242 , H01L29/51 , H01L21/3205 , H01L29/76 , H01L31/062
CPC分类号： H01L21/823878 , H01L21/28185 , H01L21/28202 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L27/10873 , H01L27/10894 , H01L29/513 , H01L29/518
摘要： Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.
摘要翻译：实施例防止或基本上减少P型杂质扩散到具有双栅极的PMOS晶体管中的沟道区域中。一些实施例包括在半导体衬底上形成器件隔离膜，在半导体衬底的有源区中形成沟道杂质区，并在半导体衬底上形成包括氧化硅层和氧化硅氮化物层的栅极绝缘层。此外，实施例可以包括在栅极绝缘层上形成含有N型杂质的多晶硅层，并且通过选择性地将P型杂质离子注入形成在电路的PMOS晶体管区域中的多晶硅层中来形成栅电极地区。实施例还包括在栅电极上形成导电金属层和栅极上绝缘层，以及在栅极区域中形成栅叠层。

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