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41. 发明授权

US06232175B1 Method of manufacturing double-recess crown-shaped DRAM capacitor 有权
标题翻译：制造双凹冠状DRAM电容器的方法
公开(公告)号：US06232175B1
公开(公告)日：2001-05-15
申请号：US09466044
申请日：1999-12-17
申请人： Yuan-Hung Liu , Bor-Wen Chan
发明人： Yuan-Hung Liu , Bor-Wen Chan
IPC分类号： H01L218242
CPC分类号： H01L28/92 , H01L21/32139 , H01L27/10852
摘要： A double recess crown-shaped DRAM capacitor is formed in a simplified process. A dielectric layer is formed over a substrate. Using photolithographic and etching techniques, a contact opening is formed in the dielectric layer. A conductive layer is formed over the dielectric layer filling the contact opening to form a conductive plug. A second dielectric layer is formed over the conductive layer. Again using photolithographic and etching techniques, the second dielectric layer is patterned to form a trapezoidal-shaped dielectric layer. An organic bottom anti-reflective coating (organic BARC) is coated over the trapezoidal-shaped dielectric layer and the conductive layer. Organic BARC above the trapezoidal-shaped dielectric layer is removed. Using the organic BARC as an etching mask, the trapezoidal-shaped dielectric layer is etched to form triangular-shaped dielectric layers and a trench in the conductive layer. The residual organic BARC is completely removed. Using the triangular-shaped dielectric layers as a hard etching mask, two types of trenches each having a different depth are formed in the conductive layer. The triangular-shaped dielectric layers are removed to form a double-recess lower electrode. Hemispherical silicon grains are grown over the interior surface of the double-recess lower electrode as well as the external sidewalls. Finally, a conformal dielectric layer and a conformal conductive layer are sequentially formed over the surface of the double-recess lower electrode.
摘要翻译：以简化的工艺形成双凹槽冠状DRAM电容器。介电层形成在衬底上。使用光刻和蚀刻技术，在电介质层中形成接触开口。在填充接触开口的电介质层上形成导电层以形成导电插塞。在导电层上形成第二介电层。再次使用光刻和蚀刻技术，将第二介电层图案化以形成梯形介电层。将有机底部抗反射涂层（有机BARC）涂覆在梯形介电层和导电层上。去除梯形介电层上方的有机BARC。使用有机BARC作为蚀刻掩模，蚀刻梯形介电层以在导电层中形成三角形介电层和沟槽。残留的有机BARC被完全去除。使用三角形介电层作为硬蚀刻掩模，在导电层中形成各具有不同深度的两种类型的沟槽。去除三角形电介质层以形成双凹槽下电极。半球状硅晶粒生长在双凹槽下电极的内表面以及外侧壁上。最后，在双凹槽下电极的表面上依次形成保形电介质层和保形导电层。

42. 发明申请

US20140061924A1 Interconnect Structure and Method 有权
标题翻译：互连结构与方法
公开(公告)号：US20140061924A1
公开(公告)日：2014-03-06
申请号：US13601265
申请日：2012-08-31
申请人： Hsin-Yu Chen , Ku-Feng Yang , Tasi-Jung Wu , Lin-Chih Huang , Yuan-Hung Liu , Tsang-Jiuh Wu , Wen-Chih Chiou
发明人： Hsin-Yu Chen , Ku-Feng Yang , Tasi-Jung Wu , Lin-Chih Huang , Yuan-Hung Liu , Tsang-Jiuh Wu , Wen-Chih Chiou
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/528 , H01L21/76807 , H01L23/3114 , H01L23/3171 , H01L23/481 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/5384 , H01L27/0617 , H01L2221/1031 , H01L2224/13 , H01L2924/13091 , H01L2924/00
摘要： An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first metallization layer formed over the interlayer dielectric layer, wherein the first metallization layer comprises a first metal line and a dielectric layer formed over the first metallization layer, wherein the dielectric layer comprises a metal structure having a bottom surface coplanr with a top surface of the first metal line.
摘要翻译：一种装置包括形成在衬底的第一侧上的层间绝缘层，形成在层间介电层上的第一金属化层，其中第一金属化层包括形成在第一金属化层上的第一金属线和介电层，其中，电介质层包括具有与第一金属线的顶表面共面的底表面的金属结构。

43. 发明申请

US20090051034A1 Semiconductor device and method for the same 审中-公开
标题翻译：半导体装置及其方法相同
公开(公告)号：US20090051034A1
公开(公告)日：2009-02-26
申请号：US11892103
申请日：2007-08-20
申请人： Chih-Yang Pai , Yuan-Hung Liu , Michael Kuang , Kuo-Ching Huang
发明人： Chih-Yang Pai , Yuan-Hung Liu , Michael Kuang , Kuo-Ching Huang
IPC分类号： H01L23/52 , H01L21/44
CPC分类号： H01L27/10888 , H01L21/76844
摘要： A method for forming a semiconductor device is provided. The method includes the following steps. A substrate having a first contact is provided. A layered structure is formed on the substrate. A recess is formed into the layered structure to expose at least a portion of the first contact. A glue layer is formed on the layered structure and the at least a portion of the first contact. The glue layer is removed from the at least a portion of the first contact. A second contact is formed contacting the first contact and the glue layer.
摘要翻译：提供一种形成半导体器件的方法。该方法包括以下步骤。提供具有第一触点的基板。在基板上形成层状结构。形成层状结构中的凹部以暴露第一接触件的至少一部分。在层状结构和第一接触的至少一部分上形成胶层。胶层从第一接触件的至少一部分去除。形成接触第一接触和胶层的第二接触。

44. 发明授权

US08546235B2 Integrated circuits including metal-insulator-metal capacitors and methods of forming the same 有权
标题翻译：包括金属 - 绝缘体 - 金属电容器的集成电路及其形成方法
公开(公告)号：US08546235B2
公开(公告)日：2013-10-01
申请号：US13101788
申请日：2011-05-05
申请人： Sung-Hui Huang , Yuan-Hung Liu , Ming-Fa Chen
发明人： Sung-Hui Huang , Yuan-Hung Liu , Ming-Fa Chen
IPC分类号： H01L21/20
CPC分类号： H01L28/40
摘要： An integrated circuit includes a substrate and a first metal-insulator-metal (MIM) capacitor disposed over the substrate. The MIM capacitor includes a first metallic capacitor plate disposed over the substrate. At least one first insulator layer is disposed over the first metallic capacitor plate. A second metallic capacitor plate is disposed over the at least one first insulator layer. At least one first dielectric layer is disposed over the substrate. At least a portion of the at least one first dielectric layer is disposed between the first metallic capacitor plate and the at least one first insulator layer.
摘要翻译：集成电路包括衬底和设置在衬底上的第一金属 - 绝缘体 - 金属（MIM）电容器。 MIM电容器包括设置在基板上的第一金属电容器板。至少一个第一绝缘体层设置在第一金属电容器板上。第二金属电容器板设置在至少一个第一绝缘体层上。至少一个第一电介质层设置在衬底上。所述至少一个第一介电层的至少一部分设置在所述第一金属电容器板和所述至少一个第一绝缘体层之间。

45. 发明申请

US20110081766A1 METHOD FOR DOPING A SELECTED PORTION OF A DEVICE 有权
标题翻译：用于对设备的选定部分进行排序的方法
公开(公告)号：US20110081766A1
公开(公告)日：2011-04-07
申请号：US12572833
申请日：2009-10-02
申请人： Han-Chi Liu , Dun-Nian Yaung , Jen-Cheng Liu , Yuan-Hung Liu
发明人： Han-Chi Liu , Dun-Nian Yaung , Jen-Cheng Liu , Yuan-Hung Liu
IPC分类号： H01L21/762
CPC分类号： H01L27/14683 , H01L21/2652 , H01L21/266 , H01L21/76232 , H01L27/14627 , H01L27/1463
摘要： A method includes forming a protective layer with an opening over a substrate, thereafter implanting a dopant into a substrate region through the opening, the protective layer protecting a different substrate region, and reducing thickness of the protective layer. A different aspect includes etching a substrate to form a recess therein, thereafter implanting a dopant into a substrate region within the recess and through an opening in a protective layer provided over the substrate, and reducing thickness of the protective layer. Another aspect includes forming a protective layer over a substrate, forming photoresist having an opening over the protective layer, etching the protective layer through the opening to expose the substrate, etching the substrate to form a recess in the substrate, implanting a dopant into a substrate portion, the protective layer protecting a different substrate portion thereunder, and etching the protective layer to reduce its thickness.
摘要翻译：一种方法包括在衬底上形成具有开口的保护层，然后通过开口将掺杂剂注入到衬底区域中，保护层保护不同的衬底区域，并减小保护层的厚度。不同的方面包括蚀刻衬底以在其中形成凹陷，然后将掺杂剂注入到凹陷内的衬底区域中，并通过设置在衬底上的保护层中的开口，并且减小保护层的厚度。另一方面包括在衬底上形成保护层，在保护层上形成具有开口的光致抗蚀剂，通过开口蚀刻保护层以暴露衬底，蚀刻衬底以在衬底中形成凹陷，将掺杂剂注入到衬底中保护层保护其下的不同基板部分，并蚀刻保护层以减小其厚度。

46. 发明授权

US06218244B1 Method of fabricating transistor 有权
标题翻译：制造晶体管的方法
公开(公告)号：US06218244B1
公开(公告)日：2001-04-17
申请号：US09482757
申请日：2000-01-13
申请人： Bor-Wen Chan , Yuan-Hung Liu
发明人： Bor-Wen Chan , Yuan-Hung Liu
IPC分类号： H01L218242
CPC分类号： H01L28/92 , H01L27/10852
摘要： A method of manufacturing a DRAM capacitor is described. A silicon substrate structure includes an oxide layer over a substrate and a polysilicon layer over the oxide layer. The polysilicon layer also includes a plug that penetrates the oxide layer. A patterned photoresist layer is next formed over the polysilicon layer. Spacers having a low etching rate are formed on the sidewalls of the photoresist layer by carrying out a chemical reaction next to the sidewall of the photoresist layer. A dry etching operation is carried out to etch the unreacted photoresist layer and the polysilicon layer exposed by the openings in the photoresist layer. Using the spacers as an etching mask, a portion of the polysilicon layer under the photoresist layer is removed by continuing the dry etching operation. Lastly, the spacers are removed to form a crown-shaped capacitor.
摘要翻译：描述制造DRAM电容器的方法。硅衬底结构包括在衬底上的氧化物层和氧化物层上的多晶硅层。多晶硅层还包括穿透氧化物层的插塞。随后在多晶硅层上形成图案化的光致抗蚀剂层。通过在光致抗蚀剂层的侧壁附近进行化学反应，在光致抗蚀剂层的侧壁上形成具有低蚀刻速率的间隔物。进行干蚀刻操作以蚀刻由光致抗蚀剂层中的开口暴露的未反应的光致抗蚀剂层和多晶硅层。使用间隔物作为蚀刻掩模，通过继续干蚀刻操作来除去光致抗蚀剂层下面的多晶硅层的一部分。最后，去除间隔物以形成冠状电容器。

47. 发明授权

US08878338B2 Capacitor for interposers and methods of manufacture thereof 有权
标题翻译：插入体用电容器及其制造方法
公开(公告)号：US08878338B2
公开(公告)日：2014-11-04
申请号：US13485340
申请日：2012-05-31
申请人： Chun Hua Chang , Der-Chyang Yeh , Kuang-Wei Cheng , Yuan-Hung Liu , Shang-Yun Hou , Wen-Chih Chiou , Shin-Puu Jeng
发明人： Chun Hua Chang , Der-Chyang Yeh , Kuang-Wei Cheng , Yuan-Hung Liu , Shang-Yun Hou , Wen-Chih Chiou , Shin-Puu Jeng
IPC分类号： H01L29/00 , H01L21/02 , H01L29/02
CPC分类号： H01L28/40 , H01L21/02 , H01L21/768 , H01L23/147 , H01L23/49822 , H01L23/49827 , H01L23/50 , H01L23/5223 , H01L23/53295 , H01L28/60 , H01L29/02 , H01L2924/0002 , H01L2924/00
摘要： Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. A through via is formed in the interposer, and a capacitor is formed between a lower level metallization layer and a higher level metallization layer. The capacitor may be, for example, a planar capacitor with dual capacitor dielectric layers.
摘要翻译：公开了用于衬底的电容器设计，例如插入件及其制造方法。在插入器中形成通孔，并且在下层金属化层和较高级金属化层之间形成电容器。电容器可以是例如具有双电容器电介质层的平面电容器。

48. 发明授权

US08440540B2 Method for doping a selected portion of a device 有权
标题翻译：掺杂设备的选定部分的方法
公开(公告)号：US08440540B2
公开(公告)日：2013-05-14
申请号：US12572833
申请日：2009-10-02
申请人： Han-Chi Liu , Dun-Nian Yaung , Jen-Cheng Liu , Yuan-Hung Liu
发明人： Han-Chi Liu , Dun-Nian Yaung , Jen-Cheng Liu , Yuan-Hung Liu
IPC分类号： H01L21/76
CPC分类号： H01L27/14683 , H01L21/2652 , H01L21/266 , H01L21/76232 , H01L27/14627 , H01L27/1463
摘要： A method includes forming a protective layer with an opening over a substrate, thereafter implanting a dopant into a substrate region through the opening, the protective layer protecting a different substrate region, and reducing thickness of the protective layer. A different aspect includes etching a substrate to form a recess therein, thereafter implanting a dopant into a substrate region within the recess and through an opening in a protective layer provided over the substrate, and reducing thickness of the protective layer. Another aspect includes forming a protective layer over a substrate, forming photoresist having an opening over the protective layer, etching the protective layer through the opening to expose the substrate, etching the substrate to form a recess in the substrate, implanting a dopant into a substrate portion, the protective layer protecting a different substrate portion thereunder, and etching the protective layer to reduce its thickness.
摘要翻译：一种方法包括在衬底上形成具有开口的保护层，然后通过开口将掺杂剂注入到衬底区域中，保护层保护不同的衬底区域，并减小保护层的厚度。不同的方面包括蚀刻衬底以在其中形成凹陷，然后将掺杂剂注入到凹陷内的衬底区域中，并通过设置在衬底上的保护层中的开口，并且减小保护层的厚度。另一方面包括在衬底上形成保护层，在保护层上形成具有开口的光致抗蚀剂，通过开口蚀刻保护层以暴露衬底，蚀刻衬底以在衬底中形成凹陷，将掺杂剂注入到衬底中保护层保护其下的不同基板部分，并蚀刻保护层以减小其厚度。

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