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41. 发明授权

US07876626B2 Semiconductor memory device and semiconductor memory system 有权
标题翻译：半导体存储器件和半导体存储器系统
公开(公告)号：US07876626B2
公开(公告)日：2011-01-25
申请号：US12408232
申请日：2009-03-20
申请人： Hideo Mukai , Hiroshi Maejima , Satoru Takase , Naoya Tokiwa , Katsuaki Isobe
发明人： Hideo Mukai , Hiroshi Maejima , Satoru Takase , Naoya Tokiwa , Katsuaki Isobe
IPC分类号： G11C7/00
CPC分类号： G11C8/10 , G11C7/18 , G11C7/22 , G11C8/08 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0028 , G11C13/0069 , G11C2013/0076 , G11C2207/2263 , G11C2211/5647 , G11C2213/31 , G11C2213/56 , G11C2213/72
摘要： A semiconductor memory device comprises a memory cell array including a plurality of memory cells arranged at intersections of word lines and bit lines; a read/write circuit operative to execute data read/write to the memory cell; and an operational circuit operative to compare certain length data read out by the read/write circuit from plural ones of the memory cells with certain length data to be written in the plural memory cells to make a decision, and create a flag representing the decision result. The read/write circuit inverts each bit in the certain length data to be written in the memory cells in accordance with the flag, and writes only rewrite-intended data of the certain length data and the flag. The read/write circuit reads the certain length data together with the flag corresponding thereto, and inverts each bit in the certain length data in accordance with the flag.
摘要翻译：半导体存储器件包括存储单元阵列，其包括布置在字线和位线的交点处的多个存储单元; 读/写电路，用于执行对存储器单元的数据读/写; 以及操作电路，用于将来自多个存储器单元的读/写电路读出的某些长度数据与要写入多个存储器单元的一定长度数据进行比较，并作出决定，并创建表示决定结果的标志。读/写电路根据该标志反转要写入存储单元的一定长度数据中的每个位，并且仅写入特定长度数据和标志的重写预期数据。读/写电路读取与其对应的标志一定的长度数据，并根据该标志反转一定长度数据中的每一位。

42. 发明申请

US20090109728A1 RESISTANCE CHANGE MEMORY DEVICE 有权
标题翻译：电阻变化存储器件
公开(公告)号：US20090109728A1
公开(公告)日：2009-04-30
申请号：US12252675
申请日：2008-10-16
申请人： Hiroshi MAEJIMA , Katsuaki Isobe , Naoya Tokiwa , Satoru Takase , Yasuyuki Fukuda , Hideo Mukai , Tsuneo Inaba
发明人： Hiroshi MAEJIMA , Katsuaki Isobe , Naoya Tokiwa , Satoru Takase , Yasuyuki Fukuda , Hideo Mukai , Tsuneo Inaba
IPC分类号： G11C11/00 , G11C11/416
CPC分类号： G11C13/0009 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2211/5642 , G11C2213/11 , G11C2213/34 , G11C2213/56 , G11C2213/72
摘要： A resistance change memory device including memory cells arranged, the memory cell having a stable state with a high resistance value and storing in a non-volatile manner such multi-level data that at least three resistance values, R0, R1 and R2 (R0 ΔR2.
摘要翻译：一种包括存储单元的电阻变化存储器件，所述存储器单元具有具有高电阻值的稳定状态并且以非易失性方式存储这样的多电平数据：至少三个电阻值R0，R1和R2（R0 < R1 DeltaR2的关系。

43. 发明授权

US07382651B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07382651B2
公开(公告)日：2008-06-03
申请号：US11616122
申请日：2006-12-26
申请人： Osamu Nagao , Yasuyuki Fukuda , Hideo Mukai
发明人： Osamu Nagao , Yasuyuki Fukuda , Hideo Mukai
IPC分类号： G11C16/00
CPC分类号： G11C16/16 , G11C16/0483
摘要： In a control order of non-selected blocks at the time of data erase operation of one or a plurality of blocks, the control gate line is controlled to ground potential at first, then subsequently, a transfer transistor of the non-selected blocks is set to be an off-state. Next, high voltage is supplied to the well region and the data of the selected block is erased. Then, the control gate line is charged to the voltage which is used, for instance, at the time of reading out, or to the voltage (Vcg) which is used at the verification (Vcg). After the control gate line is charged to Vcg, the erase voltage supplied to the well region is discharged. Then, the control gate line is returned to ground potential after completing the discharge of the well region, and thus the data erase operation of the block is completed.
摘要翻译：在一个或多个块的数据擦除操作时以非选择的块的控制顺序，首先将控制栅极线控制为接地电位，然后设置未选择块的传输晶体管成为一个离开的国家。接下来，向阱区域提供高电压，并且擦除所选块的数据。然后，控制栅极线被充电到例如在读出时使用的电压或者在验证时使用的电压（Vcg）（Vcg）。在控制栅极线被充电到Vcg之后，提供给阱区的擦除电压被放电。然后，在完成了阱区的放电之后，控制栅极线返回到接地电位，从而完成了块的数据擦除操作。

44. 发明申请

US20070147117A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070147117A1
公开(公告)日：2007-06-28
申请号：US11616122
申请日：2006-12-26
申请人： Osamu Nagao , Yasuyuki Fukuda , Hideo Mukai
发明人： Osamu Nagao , Yasuyuki Fukuda , Hideo Mukai
IPC分类号： G11C16/04 , G11C16/06 , G11C11/34
CPC分类号： G11C16/16 , G11C16/0483
摘要： In a control order of non-selected blocks at the time of data erase operation of one or a plurality of blocks, the control gate line is controlled to ground potential at first, then subsequently, a transfer transistor of the non-selected blocks is set to be an off-state. Next, high voltage is supplied to the well region and the data of the selected block is erased. Then, the control gate line is charged to the voltage which is used, for instance, at the time of reading out, or to the voltage (Vcg) which is used at the verification (Vcg). After the control gate line is charged to Vcg, the erase voltage supplied to the well region is discharged. Then, the control gate line is returned to ground potential after completing the discharge of the well region, and thus the data erase operation of the block is completed.
摘要翻译：在一个或多个块的数据擦除操作时以非选择的块的控制顺序，首先将控制栅极线控制为接地电位，然后设置未选择块的传输晶体管成为一个离开的国家。接下来，向阱区域提供高电压，并且擦除所选块的数据。然后，控制栅极线被充电到例如在读出时使用的电压或者在验证时使用的电压（Vcg）（Vcg）。在控制栅极线被充电到Vcg之后，提供给阱区的擦除电压被放电。然后，在完成了阱区的放电之后，控制栅极线返回到接地电位，从而完成了块的数据擦除操作。

45. 发明申请

US20050094428A1 Non-volatile semiconductor memory device, electronic card and electronic device 审中-公开
标题翻译：非易失性半导体存储器件，电子卡和电子器件
公开(公告)号：US20050094428A1
公开(公告)日：2005-05-05
申请号：US10939412
申请日：2004-09-14
申请人： Takuya Futatsuyama , Kenichi Imamiya , Hideo Mukai , Tatsuya Tanaka
发明人： Takuya Futatsuyama , Kenichi Imamiya , Hideo Mukai , Tatsuya Tanaka
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04 , G11C11/22
CPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C2216/18
摘要： A non-volatile semiconductor memory device operative to erase data on a block basis is provided. Each of blocks includes a plurality of NAND cells each having one or more electrically erasable programmable memory cells and selection transistors arranged at both ends thereof. The memory device comprises a plurality of block groups each consisting of the blocks grouped under the number of the memory cells configuring the NAND cell, which is the same as others in one block group and different from those in other block groups. A row selector is arranged to select the memory cells located on the same row in each block in the plurality of block groups. Neighbors of the blocks individually include the selection transistors not shared.
摘要翻译：提供了可操作地以块为单位擦除数据的非易失性半导体存储器件。每个块包括多个NAND单元，每个NAND单元具有一个或多个电可擦除可编程存储单元和布置在其两端的选择晶体管。存储器件包括多个块组，每个块组由分组在配置NAND单元的存储器单元的数量之下的块构成，其与一个块组中的其他块相同，并且与其他块组中的块不同。行选择器被布置为选择位于多个块组中的每个块中位于同一行上的存储器单元。块的相邻单元分别包括不共享的选择晶体管。

46. 发明授权

US06567322B1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06567322B1
公开(公告)日：2003-05-20
申请号：US09528177
申请日：2000-03-17
申请人： Hideo Mukai , Kaoru Nakagawa
发明人： Hideo Mukai , Kaoru Nakagawa
IPC分类号： G11C700
CPC分类号： G11C29/785 , G11C29/81
摘要： In a DRAM semiconductor memory device, a DRAM semiconductor memory device disclosed herein comprises a first spare element SWL provided for each of a plurality of normal banks BANK0-BANK15 formed by dividing a memory cell array into a plurality of sections, a second spare element SWL provided for a spare bank BANKSP different from the normal banks, a plurality of first spare decoders SRD0-SRD3 for selectively operating the first spare element, a plurality of second spare decoders SRD0-SRD3 for selectively operating the second spare element, and a substitution-control circuits FS0a-FS27a, RWLON1-RWLON2, SRDact0-SRDact3 for selectively assigning the second spare elements to arbitrary banks of the plurality of normal banks. With the above structure, the total number of the spare elements of the defective memory cells of the DRAM can be reduced while the relieving ratio is being maintained. As a result, the area efficiency of the redundant circuit on the chip can be improved.
摘要翻译：在DRAM半导体存储器件中，本文公开的DRAM半导体存储器件包括：通过将存储单元阵列划分为多个部分而形成的多个正常库BANK0-BANK15中的每一个设置的第一备用元件SWL，第二备用元件SWL 提供了与正常库不同的备用银行BANKSP，用于选择性地操作第一备用元件的多个第一备用解码器SRD0-SRD3，用于选择性地操作第二备用元件的多个第二备用解码器SRD0-SRD3，控制电路FS0a-FS27a，RWLON1-RWLON2，SRDact0-SRDact3，用于选择性地将第二备用元件分配给多个正常库中的任意组。利用上述结构，可以减小DRAM的有缺陷的存储单元的备用元件的总数，同时保持释放比。结果，能够提高芯片上的冗余电路的面积效率。

47. 发明授权

US6117129A Laser treatment apparatus 失效
标题翻译：激光治疗仪
公开(公告)号：US6117129A
公开(公告)日：2000-09-12
申请号：US85107
申请日：1998-05-28
申请人： Hideo Mukai
发明人： Hideo Mukai
IPC分类号： A61B17/00 , A61B18/00 , A61B18/20 , A61B18/18
CPC分类号： A61B18/203 , A61B18/201 , A61B2017/00123 , A61B2017/00199 , A61B2017/00477 , A61B2017/00725 , A61B2017/00973 , A61B2018/00452 , A61B2018/00642 , A61B2018/2025 , A61B2018/2095 , A61B2218/005 , A61B2218/008
摘要： A laser treatment apparatus has a hand-piece unit with a laser scanner which deflects a laser beam emitted from a laser source to scan a treatment portion of a patient's skin. In the laser treatment apparatus, the first control device controls the laser scanner to perform a laser scanning irradiation. The detection device detects whether the hand-piece unit is electrically connected with the first control device. When the detection device detects the electrical disconnection of the hand-piece unit to the first control device, the second control device forbids the first control device to conduct the laser scanning irradiation.
摘要翻译：激光治疗装置具有带有激光扫描器的手持单元，该激光扫描器使从激光源发射的激光束偏转以扫描患者皮肤的治疗部分。在激光治疗装置中，第一控制装置控制激光扫描仪进行激光扫描照射。检测装置检测手持单元是否与第一控制装置电连接。当检测装置检测到手持单元与第一控制装置的断电时，第二控制装置禁止第一控制装置进行激光扫描照射。

48. 发明授权

US5982695A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5982695A
公开(公告)日：1999-11-09
申请号：US64047
申请日：1998-04-22
申请人： Hideo Mukai
发明人： Hideo Mukai
IPC分类号： G11C11/401 , G11C5/14 , G11C7/12 , G11C8/10 , G11C11/407 , G11C11/409 , G11C7/00 , G11C11/24
CPC分类号： G11C5/147 , G11C5/145 , G11C7/12 , G11C8/10
摘要： A semiconductor memory includes memory cell array, a voltage boosting circuit, a potential generating circuit and a sense amplifier. The memory cell array is composed of a matrix arrangement of memory cells. Each memory cell is composed of a storage device which is selectively controlled by a word line control signal and a bit line control signal supplied to a word line and a bit line at a predetermined timing. The voltage boosting circuit boosts a potential on a word line selected by the word line control signal up to a first potential that is higher than an internal power source potential. The potential generating circuit sets the potential of the bit line selected by the bit line control signal. The potential of the bit line is set to a second potential that is higher than a potential that is lower than the first potential by a threshold of the memory cell. The sense amplifier is operated using the second potential as an operating power source. The sense amplifier amplifies a potential difference between a reference bit line and a read bit line to which data stored in the selectively controlled memory cell is transmitted.
摘要翻译：半导体存储器包括存储单元阵列，升压电路，电位发生电路和读出放大器。存储单元阵列由存储单元的矩阵排列组成。每个存储单元由存储装置组成，存储装置由字线控制信号和提供给字线和位线的位线控制信号在预定定时被选择地控制。升压电路将由字线控制信号选择的字线上的电位升高到高于内部电源电位的第一电位。电位发生电路设定由位线控制信号选择的位线的电位。位线的电位被设置为比存储器单元的阈值低于第一电位的电位的第二电位。使用第二电位作为工作电源来操作读出放大器。读出放大器放大参考位线和存储在选择性控制的存储单元中的数据被发送到的读位线之间的电位差。

49. 发明授权

US4745429A Developing apparatus for an electrostatic photocopier 失效
标题翻译：静电复印机显影装置
公开(公告)号：US4745429A
公开(公告)日：1988-05-17
申请号：US66110
申请日：1987-06-25
申请人： Hideo Mukai , Sachiko Yasuda , Minoru Yoshida , Tomoyuji Asada
发明人： Hideo Mukai , Sachiko Yasuda , Minoru Yoshida , Tomoyuji Asada
IPC分类号： G03G15/08 , G03G15/06
CPC分类号： G03G15/0815 , G03G2215/0614 , G03G2215/0636
摘要： In a developing apparatus for developing an electrostaticlatent image by applying a charged developer to the electrostatic-latent image formed on a surface of an image carrier, a housing which stores the developer and has a developing roller for feeding the developer therefrom to a developing position. A recovering blade for recovering a residual developer on the developer roller in the housing is urged against developer roller. The recovering blade has a conductive portion in contact with the developing roller so as not to non-uniformly or abnormaly triboelectrically charge a developer passing over it into the housing.
摘要翻译：在用于通过将带电显影剂施加到形成在图像载体的表面上的静电潜像来显影静电潜像的显影装置中，存储显影剂并具有用于将显影剂从显影剂供给到显影位置的显影辊的壳体。用于回收外壳中的显影辊上的残留显影剂的回收刀片被推压到显影辊上。回收刀片具有与显影辊接触的导电部分，以便不会对通过其的外壳中的显影剂进行摩擦电荷的非均匀或异常的充电。

50. 发明授权

US4455078A Charging device having a conductive particle impregnated strand lined contact member 失效
标题翻译：充电装置具有导电颗粒浸渍的绞线接触构件
公开(公告)号：US4455078A
公开(公告)日：1984-06-19
申请号：US310721
申请日：1981-10-13
申请人： Hideo Mukai , Toshimasa Takano
发明人： Hideo Mukai , Toshimasa Takano
IPC分类号： G03G15/02 , H01B1/20 , H01B1/24 , H01T19/00 , G03G15/00
CPC分类号： G03G15/0233 , G03G2215/1661
摘要： A charging device comprises a contact piled cloth which is formed of pliable material, has an electric resistance chosen to be 10.sup.8 .OMEGA..cm and contacts with a photosensitive layer of a photosensitive drum, an electrode which is electrically connected to the contact piled cloth and has an electric resistance lower than the predetermined electric resistance of the contact piled cloth, and D.C. power source and A.C. power source for supplying a voltage on the electrode to charge the photosensitive layer. The contact piled cloth is provided with a multitude of raised furs formed of artificial fibers with conductive particles dispersed therein.
摘要翻译：充电装置包括由柔韧材料形成的接触堆叠布，电阻选择为108欧姆·厘米，并与感光鼓的感光层接触，电连接到接触堆叠布并具有低于接触堆积布的预定电阻的电阻，以及用于在电极上提供电压以对感光层充电的DC电源和AC电源。接触堆叠布被提供有由其中分散有导电颗粒的人造纤维形成的大量凸起毛皮。

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