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41. 发明授权

US07800091B2 Nonvolatile semiconductor memory device and manufacturing method thereof 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07800091B2
公开(公告)日：2010-09-21
申请号：US12108783
申请日：2008-04-24
申请人： Takeshi Kamigaichi , Hirofumi Inoue
发明人： Takeshi Kamigaichi , Hirofumi Inoue
IPC分类号： H01L29/04
CPC分类号： H01L27/2409 , H01L27/2436 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/147
摘要： A nonvolatile semiconductor memory device includes a first stacked structure in which a plurality of electrode layers are stacked on a substrate via insulating layers, a first resistance changing layer provided on a side surface of the first stacked structure and in contact with the first electrode layers, the first resistance changing layer having a resistance value changing on the basis of an applied voltage, a second electrode layer provided on a side surface of the first resistance changing layer, and a bit line provided on the first stacked structure and electrically connected to the second electrode layer.
摘要翻译：非易失性半导体存储器件包括：第一堆叠结构，其中多个电极层经由绝缘层堆叠在衬底上;第一电阻改变层，设置在第一堆叠结构的侧表面上并与第一电极层接触; 所述第一电阻变化层具有基于施加电压而变化的电阻值，设置在所述第一电阻变化层的侧面上的第二电极层和设置在所述第一堆叠结构上并与所述第二电阻变化层电连接的位线电极层。

42. 发明授权

US07616491B2 Semiconductor memory device improved in data writing 失效
标题翻译：半导体存储器件改进了数据写入
公开(公告)号：US07616491B2
公开(公告)日：2009-11-10
申请号：US11738636
申请日：2007-04-23
申请人： Takeshi Kamigaichi , Riichiro Shirota
发明人： Takeshi Kamigaichi , Riichiro Shirota
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/24 , H01L27/115 , H01L27/11524
摘要： A bit line is shared by first and second NAND units. First and second selection transistors are connected in series between the bit line and the first NAND unit. Third and fourth selection transistors are connected in series between the bit line and the second NAND unit. A control unit changes a first and second signals and a potential of the bit line from a first level to a second level higher than a first level, and changes the potential of the bit line from the second level to the first level after changing the first signal from the second level to the first level.
摘要翻译：位线由第一和第二NAND单元共享。第一和第二选择晶体管串联在位线和第一NAND单元之间。第三和第四选择晶体管串联在位线和第二NAND单元之间。控制单元将第一和第二信号和位线的电位从第一电平改变到高于第一电平的第二电平，并且在改变第一电平之后将位线的电位从第二电平改变到第一电平信号从第二级到第一级。

43. 发明申请

US20090090960A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：US20090090960A1
公开(公告)日：2009-04-09
申请号：US12245199
申请日：2008-10-03
申请人： Tatsuo IZUMI , Takeshi Kamigaichi
发明人： Tatsuo IZUMI , Takeshi Kamigaichi
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.
摘要翻译：非易失性半导体存储装置包括：基板; 设置在所述基板上的控制电路层; 设置在所述控制电路层上的支撑层; 以及设置在支撑层上的存储单元阵列层。存储单元阵列层包括：第一层叠部分，其具有交替层叠在其中的第一绝缘层和第一导电层; 以及设置在相应的第一层叠部分的顶表面或底表面上并层压以在第二绝缘层之间形成第二导电层的第二层压部件。所述控制电路层包括以下中的至少一个：行解码器驱动设置在所述存储单元阵列层中的字线，以及读出放大器，用于感测和放大来自设置在所述存储单元阵列层中的位线的信号。

44. 发明授权

US07449745B2 Nonvolatile semiconductor memory device having element isolating region of trench type 有权
标题翻译：具有沟槽型元件隔离区域的非易失性半导体存储器件
公开(公告)号：US07449745B2
公开(公告)日：2008-11-11
申请号：US11687019
申请日：2007-03-16
申请人： Michiharu Matsui , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
发明人： Michiharu Matsui , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11543 , H01L29/7887
摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.
摘要翻译：公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上，元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电子经由开口部与第一电极层连接。

45. 发明申请

US20080265235A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20080265235A1
公开(公告)日：2008-10-30
申请号：US12108783
申请日：2008-04-24
申请人： Takeshi Kamigaichi , Hirofumi Inoue
发明人： Takeshi Kamigaichi , Hirofumi Inoue
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： H01L27/2409 , H01L27/2436 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/147
摘要： A nonvolatile semiconductor memory device includes a first stacked structure in which a plurality of electrode layers are stacked on a substrate via insulating layers, a first resistance changing layer provided on a side surface of the first stacked structure and in contact with the first electrode layers, the first resistance changing layer having a resistance value changing on the basis of an applied voltage, a second electrode layer provided on a side surface of the first resistance changing layer, and a bit line provided on the first stacked structure and electrically connected to the second electrode layer.
摘要翻译：非易失性半导体存储器件包括：第一堆叠结构，其中多个电极层经由绝缘层堆叠在衬底上;第一电阻改变层，设置在第一堆叠结构的侧表面上并与第一电极层接触; 所述第一电阻变化层具有基于施加电压而变化的电阻值，设置在所述第一电阻变化层的侧面上的第二电极层和设置在所述第一堆叠结构上并与所述第二电阻变化层电连接的位线电极层。

46. 发明授权

US07348627B2 Nonvolatile semiconductor memory device having element isolating region of trench type 有权
标题翻译：具有沟槽型元件隔离区域的非易失性半导体存储器件
公开(公告)号：US07348627B2
公开(公告)日：2008-03-25
申请号：US11399657
申请日：2006-04-07
申请人： Michiharu Matsui , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
发明人： Michiharu Matsui , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11543 , H01L29/7887
摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electrically connected to the first electrode layer via the open portion.
摘要翻译：公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上，元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电气经由开口部与第一电极层连接。

47. 发明授权

US07119413B2 High-voltage transistor having shielding gate 有权
公开(公告)号：US07119413B2
公开(公告)日：2006-10-10
申请号：US10967128
申请日：2004-10-19
申请人： Hiroyuki Kutsukake , Kikuko Sugimae , Takeshi Kamigaichi
发明人： Hiroyuki Kutsukake , Kikuko Sugimae , Takeshi Kamigaichi
IPC分类号： H01L29/00
CPC分类号： H01L27/11526 , G11C16/0408 , G11C16/08 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/0649 , H01L29/402 , H01L29/404
摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.

48. 发明申请

US20060197226A1 Nonvolatile semiconductor memory device having element isolating region of trench type 有权
标题翻译：具有沟槽型元件隔离区域的非易失性半导体存储器件
公开(公告)号：US20060197226A1
公开(公告)日：2006-09-07
申请号：US11399657
申请日：2006-04-07
申请人： Michiharu Matsui , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
发明人： Michiharu Matsui , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11543 , H01L29/7887
摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electrically connected to the first electrode layer via the open portion.
摘要翻译：公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上，元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电气经由开口部与第一电极层连接。

49. 发明申请

US20060038232A1 High-voltage transistor having shielding gate 有权
公开(公告)号：US20060038232A1
公开(公告)日：2006-02-23
申请号：US10967128
申请日：2004-10-19
申请人： Hiroyuki Kutsukake , Kikuko Sugimae , Takeshi Kamigaichi
发明人： Hiroyuki Kutsukake , Kikuko Sugimae , Takeshi Kamigaichi
IPC分类号： H01L29/76
CPC分类号： H01L27/11526 , G11C16/0408 , G11C16/08 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/0649 , H01L29/402 , H01L29/404
摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.

50. 发明申请

US20050139904A1 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20050139904A1
公开(公告)日：2005-06-30
申请号：US10983744
申请日：2004-11-09
申请人： Takeshi Kamigaichi , Hiroyuki Kutsukake , Kikuko Sugimae
发明人： Takeshi Kamigaichi , Hiroyuki Kutsukake , Kikuko Sugimae
IPC分类号： H01L21/28 , G11C5/02 , G11C16/04 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/8247 , H01L27/06 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C5/025 , G11C16/04 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： A nonvolatile semiconductor memory on a semiconductor chip includes: a cell array region configured with a memory cell transistor having a first metallic salicide film, a first control gate electrode electrically coupled with the first metallic salicide film, and a floating gate electrode adjacent to the first control gate electrode; a high voltage circuit region including a high voltage transistor made of a second metallic salicide film, a first source region and a first drain region, and a first gate region arranged between the first source region and the first drain region; and a low voltage circuit region including a low voltage transistor made of a third metallic salicide film, a second source region and a second drain region electrically coupled with the third metallic salicide film, and a second gate region arranged between the second source region and the second drain region and is electrically coupled with the third metallic salicide film.
摘要翻译：半导体芯片上的非易失性半导体存储器包括：单元阵列区域，其配置有具有第一金属自对离硅化物膜的存储单元晶体管，与第一金属硅化物膜电耦合的第一控制栅电极和与第一金属化物质相邻的浮置栅电极控制栅电极; 包括由第二金属硅化物膜制成的高压晶体管，第一源极区和第一漏极区以及布置在第一源极区和第一漏极区之间的第一栅极区的高电压电路区; 以及包括由第三金属硅化物膜制成的低压晶体管的低电压电路区域，与第三金属硅化物膜电耦合的第二源极区域和第二漏极区域，以及布置在第二源极区域和第二源极区域之间的第二栅极区域第二漏区，并与第三金属硅化物膜电耦合。

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