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41. 发明授权

US08441829B2 Stable SRAM cell 有权
公开(公告)号：US08441829B2
公开(公告)日：2013-05-14
申请号：US12727985
申请日：2010-03-19
申请人： Huai-Ying Huang , Yu-Kuan Lin , Sheng Chiang Hung , Feng-Ming Chang , Jui-Lin Chen , Ping-Wei Wang
发明人： Huai-Ying Huang , Yu-Kuan Lin , Sheng Chiang Hung , Feng-Ming Chang , Jui-Lin Chen , Ping-Wei Wang
IPC分类号： G11C15/00
CPC分类号： G11C11/412 , G11C11/419
摘要： SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

42. 发明申请

US20130094035A1 MULTIPLE PATTERNING TECHNOLOGY METHOD AND SYSTEM FOR ACHIEVING MINIMAL PATTERN MISMATCH 有权
标题翻译：用于实现最小图案误差的多种格局技术方法和系统
公开(公告)号：US20130094035A1
公开(公告)日：2013-04-18
申请号：US13275899
申请日：2011-10-18
申请人： Feng-Ming Chang , Chang-Ta Yang , Ping-Wei Wang , Min Cao
发明人： Feng-Ming Chang , Chang-Ta Yang , Ping-Wei Wang , Min Cao
IPC分类号： H04N1/60
CPC分类号： G03F1/68 , G03F1/70 , G03F7/0005 , H01L27/0207 , H01L27/1104
摘要： The present disclosure provides for many different embodiments of a multiple patterning technology method and system. An exemplary method includes receiving a pattern layout having a plurality of features; coloring each of the plurality of features one of at least two colors, thereby forming a colored pattern layout, wherein the coloring includes coloring match-sensitive features a same color; and fabricating at least two masks with the features of the colored pattern layout, wherein each mask includes features of a single color.
摘要翻译：本公开提供了多种图案化技术方法和系统的许多不同实施例。一种示例性方法包括接收具有多个特征的图案布局; 将多个特征中的每一个着色为至少两种颜色中的一种，从而形成着色图案布局，其中着色包括对相同颜色的匹配敏感特征进行着色; 以及制造具有着色图案布局的特征的至少两个掩模，其中每个掩模包括单一颜色的特征。

43. 发明申请

US20110284972A1 Modifying Work Function in PMOS Devices by Counter-Doping 有权
标题翻译：通过反掺杂修改PMOS器件中的工作功能
公开(公告)号：US20110284972A1
公开(公告)日：2011-11-24
申请号：US13204461
申请日：2011-08-05
申请人： Chun-Yi Lee , Harry Chuang , Ping-Wei Wang , Kong-Beng Thei
发明人： Chun-Yi Lee , Harry Chuang , Ping-Wei Wang , Kong-Beng Thei
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L27/0883 , G11C11/412 , H01L27/092 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/1083 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , Y10S438/919
摘要： A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.
摘要翻译：提供了包括SRAM /反相器单元的半导体结构及其形成方法，其中SRAM /反相器单元具有改善的写入裕度。 SRAM /反相器单元包括上拉PMOS器件，其包括半导体衬底上的栅极电介质，栅极电介质上的栅电极，其中栅电极包括p型杂质和n型杂质，以及形成在源极/漏极区域。上拉PMOS器件的器件驱动电流由于栅电极的反掺杂而降低。

44. 发明授权

US08053839B2 Doping of semiconductor fin devices 有权
标题翻译：掺杂半导体鳍片器件
公开(公告)号：US08053839B2
公开(公告)日：2011-11-08
申请号：US12732011
申请日：2010-03-25
申请人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/26586 , H01L29/66803
摘要： A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.
摘要翻译：半导体结构包括覆盖绝缘体层的多个半导体鳍片，覆盖所述半导体鳍片的一部分的栅极电介质和覆盖栅极电介质的栅电极。每个半导体翅片具有顶表面，第一侧壁表面和第二侧壁表面。掺杂离子相对于半导体鳍片的顶表面的法线以第一角度（例如，大于约7°）注入，以掺杂第一侧壁表面和顶表面。相对于半导体鳍片的顶表面的法线注入另外的掺杂剂离子以掺杂第二侧壁表面和顶表面。

45. 发明申请

US20110198699A1 INTEGRATED SEMICONDUCTOR STRUCTURE FOR SRAM AND FABRICATION METHODS THEREOF 有权
标题翻译：用于SRAM及其制造方法的集成半导体结构
公开(公告)号：US20110198699A1
公开(公告)日：2011-08-18
申请号：US12706809
申请日：2010-02-17
申请人： Sheng Chiang Hung , Huai-Ying Huang , Ping-Wei Wang
发明人： Sheng Chiang Hung , Huai-Ying Huang , Ping-Wei Wang
IPC分类号： H01L27/092
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L27/11 , H01L29/495 , H01L29/4966 , H01L29/66545 , H01L29/7848
摘要： A SRAM device with metal gate transistors is provided. The SRAM device includes a PMOS structure and an NMOS structure over a substrate. Each of the PMOS and the NMOS structure includes a p-type metallic work function layer and an n-type metallic work function layer. The p-type work metallic function layer and the n-type metallic work function layer form a combined work function for the PMOS and the NMOS structures.
摘要翻译：提供了具有金属栅极晶体管的SRAM器件。 SRAM器件在衬底上包括PMOS结构和NMOS结构。 PMOS和NMOS结构中的每一个包括p型金属功函数层和n型金属功函数层。 p型工作金属功能层和n型金属功函数层形成PMOS和NMOS结构的组合功函数。

46. 发明申请

US20110068400A1 Methods and Apparatus for SRAM Bit Cell with Low Standby Current, Low Supply Voltage and High Speed 有权
标题翻译：具有低待机电流，低电源电压和高速的SRAM位单元的方法和装置
公开(公告)号：US20110068400A1
公开(公告)日：2011-03-24
申请号：US12748098
申请日：2010-03-26
申请人： Ping-Wei Wang , Chang-Ta Yang , Yuh-Jier Mii
发明人： Ping-Wei Wang , Chang-Ta Yang , Yuh-Jier Mii
IPC分类号： H01L27/12 , H01L29/78
CPC分类号： G11C11/412 , H01L27/0207 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116
摘要： Circuits and methods for providing an SRAM or CAM bit cell. In one embodiment, a bit cell portion with thicker gate oxides in the storage cell transistors, and thinner gate oxides in a read port section having transistors are disclosed. The use of the thick gate oxides in the storage cell transistors provides a stable storage of data and lower standby leakage current. The use of the thinner gate oxides in the read port transistors provides fast read accesses and allows a lower Vcc,min in the read port. The methods used to form the dual gate oxide thickness SRAM cells have process steps compatible with the existing semiconductor manufacturing processes. Embodiments using high k gate dielectrics, dual gate dielectric materials in a single bit cell, and using finFET and planar devices in a bit cell are described. Methods for forming the structures are disclosed.
摘要翻译：用于提供SRAM或CAM位单元的电路和方法。在一个实施例中，公开了存储单元晶体管中具有较厚栅极氧化物的位单元部分，以及具有晶体管的读取端口部分中较薄的栅极氧化物。在存储单元晶体管中使用厚栅极氧化物提供数据的稳定存储和较低待机漏电流。在读端口晶体管中使用较薄的栅极氧化物提供快速的读取访问，并允许在读取端口中较低的Vcc，min。用于形成双栅极氧化物厚度SRAM单元的方法具有与现有半导体制造工艺兼容的工艺步骤。描述了在单个位单元中使用高k栅极电介质，双栅介质材料以及在位单元中使用finFET和平面器件的实施例。公开了形成结构的方法。

47. 发明授权

US07750416B2 Modifying work function in PMOS devices by counter-doping 失效
标题翻译：通过反掺杂改进PMOS器件的功能
公开(公告)号：US07750416B2
公开(公告)日：2010-07-06
申请号：US11416938
申请日：2006-05-03
申请人： Chun-Yi Lee , Harry Chuang , Ping-Wei Wang , Kong-Beng Thei
发明人： Chun-Yi Lee , Harry Chuang , Ping-Wei Wang , Kong-Beng Thei
IPC分类号： H01L29/76
CPC分类号： H01L27/0883 , G11C11/412 , H01L27/092 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/1083 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , Y10S438/919
摘要： A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.
摘要翻译：提供了包括SRAM /反相器单元的半导体结构及其形成方法，其中SRAM /反相器单元具有改善的写入裕度。 SRAM /反相器单元包括上拉PMOS器件，其包括半导体衬底上的栅极电介质，栅极电介质上的栅电极，其中栅电极包括p型杂质和n型杂质，以及形成在源极/漏极区域。上拉PMOS器件的器件驱动电流由于栅电极的反掺杂而降低。

48. 发明申请

US20090289325A1 Semiconductor Device with Crack Prevention Ring 有权
标题翻译：具有防裂环的半导体器件
公开(公告)号：US20090289325A1
公开(公告)日：2009-11-26
申请号：US12511720
申请日：2009-07-29
申请人： Ping-Wei Wang , Chii-Ming Morris Wu
发明人： Ping-Wei Wang , Chii-Ming Morris Wu
IPC分类号： H01L29/06 , H01L23/00
CPC分类号： H01L23/562 , H01L23/585 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A crack prevention ring at the exterior edge of an integrated circuit prevents delamination and cracking during the separation of the integrated circuits into individual die. The crack prevention ring extends vertically into a semiconductor workpiece to at least a metallization layer of the integrated circuit. The crack prevention ring may be formed simultaneously with the formation of test pads of the integrated circuits. The crack prevention ring may be partially or completely filled with conductive material. An air pocket may be formed within the crack prevention ring beneath a passivation layer of the integrated circuit. The crack prevention ring may be removed during the singulation process.
摘要翻译：在集成电路的外部边缘处的防裂环防止在将集成电路分离成单个管芯期间的分层和破裂。防裂环垂直延伸到半导体工件中至少到集成电路的金属化层。防裂环可以与集成电路的测试焊盘的形成同时形成。防裂环可以部分或完全填充导电材料。可以在集成电路的钝化层下方的防裂环内形成气穴。在切割过程中可以除去防裂环。

49. 发明授权

US07436696B2 Read-preferred SRAM cell design 有权
标题翻译：读取优先的SRAM单元设计
公开(公告)号：US07436696B2
公开(公告)日：2008-10-14
申请号：US11582116
申请日：2006-10-17
申请人： Ping-Wei Wang , Yuh-Jier Mii , Hung-Jen Liao
发明人： Ping-Wei Wang , Yuh-Jier Mii , Hung-Jen Liao
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L21/26586 , H01L29/66659
摘要： A read-preferred SRAM cell includes a pull-up MOS device having a first drive current, a pull-down MOS device coupled to the pull-up MOS device, the pull-down MOS device having a second drive current, and a pass-gate MOS device having a third drive current coupled to the pull-up MOS device and the pull-down MOS device. The first drive current and the third drive current preferably have an α ratio of between about 0.5 and about 1. The second drive current and the third drive current preferably have a β ratio of between about 1.45 and 5.
摘要翻译：读优选SRAM单元包括具有第一驱动电流的上拉MOS器件，耦合到上拉MOS器件的下拉MOS器件，具有第二驱动电流的下拉MOS器件，栅极MOS器件具有耦合到上拉MOS器件和下拉MOS器件的第三驱动电流。第一驱动电流和第三驱动电流优选地具有在约0.5和约1之间的α比率。第二驱动电流和第三驱动电流优选具有在约1.45和5之间的β比率。

50. 发明申请

US20080244482A1 INTEGRATED CIRCUIT DESIGN USAGE AND SANITY VERIFICATION 有权
标题翻译：集成电路设计使用和SANITY验证
公开(公告)号：US20080244482A1
公开(公告)日：2008-10-02
申请号：US11949311
申请日：2007-12-03
申请人： Gwan Sin Chang , Cheng-Hung Yeh , Feng-Ming Chang , Ping-Wei Wang
发明人： Gwan Sin Chang , Cheng-Hung Yeh , Feng-Ming Chang , Ping-Wei Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： An automated system and method for sanity checking an integrated circuit cell layout. The method generally includes searching the cell layout for a sub-area containing a predefined identifier, determining a reference cell layout corresponding to the predefined identifier, verifying the cell layout by comparing the cell layout to the reference cell layout to determine if a cell is of concern, and reporting the cell of concern to a user.
摘要翻译：一种用于整合集成电路单元格布局的自动化系统和方法。该方法通常包括在单元布局中搜索包含预定义标识符的子区域，确定与预定标识符对应的参考单元布局，通过将单元格布局与参考单元格布局进行比较来确定单元格布局，以确定单元格是否为关注并报告用户关注的单元格。

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