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41. 发明授权

US08264213B2 Variable-frequency and multi-phase voltage regulator module and control method of the same 有权
标题翻译：变频和多相电压调节器模块及其控制方法相同
公开(公告)号：US08264213B2
公开(公告)日：2012-09-11
申请号：US12470424
申请日：2009-05-21
申请人： Chih-Wei Lin , Nung-Te Huang , Chih-Wan Hsu
发明人： Chih-Wei Lin , Nung-Te Huang , Chih-Wan Hsu
IPC分类号： G05F1/575 , G05F1/618
CPC分类号： H02M3/1584 , H02M3/157 , H02M2001/0032 , H02M2003/1586 , Y02B70/16
摘要： A control method of a variable-frequency and multi-phase voltage regulator module is provided. The variable-frequency and multi-phase voltage regulator module is connected to a central processing unit and embedded on a motherboard for providing a central-processing-unit current. The control method includes steps of: detecting an intensity of a central-processing-unit current of the central processing unit; providing a power to the central processing unit via M number of phases based on a first switching frequency if the intensity of the central-processing-unit current is greater than a reference-current value; and providing a power to the central processing unit via N number of phases based on a second switching frequency if the intensity of the central-processing-unit current is less than the reference-current value.
摘要翻译：提供了一种变频和多相电压调节器模块的控制方法。可变频率和多相电压调节器模块连接到中央处理单元并嵌入在主板上以提供中央处理单元电流。该控制方法包括以下步骤：检测中央处理单元的中央处理单元电流的强度; 如果中央处理单元电流的强度大于参考电流值，则基于第一开关频率经由M个相位来向中央处理单元提供电力; 以及如果所述中央处理单元电流的强度小于所述基准电流值，则基于第二开关频率经由N个相位来向所述中央处理单元提供电力。

42. 发明授权

US08214664B2 Power supply system and power supplying control method 有权
标题翻译：电源系统和供电控制方法
公开(公告)号：US08214664B2
公开(公告)日：2012-07-03
申请号：US12483941
申请日：2009-06-12
申请人： Chih-Wei Lin , Chih-Wan Hsu , Nung-Te Huang
发明人： Chih-Wei Lin , Chih-Wan Hsu , Nung-Te Huang
IPC分类号： G06F1/26
CPC分类号： G06F1/263
摘要： A power supplying control method of a computer system for use with a first power supply and a second power supply both providing a first specific voltage to a motherboard, including steps of: detecting whether the first power supply and the second power supply, outputting the first specific voltage, are at a stable state; outputting the first specific voltage to a first pin when the first power supply is at the stable state; outputting the first specific voltage to the first pin when the second power supply is at the stable state; and outputting the first specific voltage to the motherboard via the first pin.
摘要翻译：一种与向主板提供第一特定电压的第一电源和第二电源一起使用的计算机系统的供电控制方法，包括以下步骤：检测第一电源和第二电源，输出第一电源具体电压处于稳定状态; 当第一电源处于稳定状态时，将第一特定电压输出到第一引脚; 当第二电源处于稳定状态时，将第一特定电压输出到第一引脚; 以及经由所述第一引脚将所述第一特定电压输出到所述母板。

43. 发明申请

US20080197260A1 COMPUTER HOUSING 审中-公开
标题翻译：电脑外壳
公开(公告)号：US20080197260A1
公开(公告)日：2008-08-21
申请号：US11676294
申请日：2007-02-18
申请人： I-Ching Chou , Chih-Wei Lin , Yuh-Wen Huang
发明人： I-Ching Chou , Chih-Wei Lin , Yuh-Wen Huang
IPC分类号： A47B96/00
CPC分类号： G11B33/128 , G06F1/187
摘要： A computer housing includes: a housing body; a first supporting plate mounted in the housing body; a second supporting plate mounted in the housing body and cooperating with the first supporting plate to define a mounting space therebetween; and an operating lever pivoted to the second supporting plate, formed with an engaging tongue, and rotatable relative to the second supporting plate between a first angular position, in which the engaging tongue extends into the mounting space for retaining a box-like device in the mounting space, and a second angular position, in which the engaging tongue is disposed outside of the mounting space for permitting removal of the box-like device.
摘要翻译：计算机壳体包括：壳体; 安装在所述壳体内的第一支撑板; 第二支撑板，其安装在所述壳体中并与所述第一支撑板协作以在其间限定安装空间; 以及操作杆，其枢转到第二支撑板，形成有接合舌片，并且可相对于第二支撑板在第一角位置之间旋转，第一角位置中，接合舌片延伸到安装空间中，以将盒状装置保持在安装空间和第二角位置，其中接合舌片设置在安装空间的外部，以允许移除盒状装置。

44. 发明授权

US09991190B2 Packaging with interposer frame 有权
公开(公告)号：US09991190B2
公开(公告)日：2018-06-05
申请号：US13475674
申请日：2012-05-18
申请人： Hui-Min Huang , Yen-Chang Hu , Chih-Wei Lin , Ming-Da Cheng , Chung-Shi Liu , Chen-Shien Chen
发明人： Hui-Min Huang , Yen-Chang Hu , Chih-Wei Lin , Ming-Da Cheng , Chung-Shi Liu , Chen-Shien Chen
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/495 , H01L23/00 , H01L23/31 , H01L21/56 , H01L23/498 , H01L25/10
CPC分类号： H01L23/495 , H01L21/568 , H01L23/3107 , H01L23/3121 , H01L23/3128 , H01L23/49811 , H01L23/49827 , H01L24/19 , H01L25/105 , H01L2224/12105 , H01L2224/16225 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2924/181 , H01L2924/00014 , H01L2924/00012
摘要： The mechanisms of using an interposer frame to package a semiconductor die enables fan-out structures and reduces form factor for the packaged semiconductor die. The mechanisms involve using a molding compound to attach the semiconductor die to the interposer frame and forming a redistribution layer on one or both sides of the semiconductor die. The redistribution layer(s) in the package enables fan-out connections and formation of external connection structures. Conductive columns in the interposer frame assist in thermal management.

45. 发明授权

US09786622B2 Semiconductor package 有权
公开(公告)号：US09786622B2
公开(公告)日：2017-10-10
申请号：US13277575
申请日：2011-10-20
申请人： Ming-Da Cheng , Chih-Wei Lin , Kuei-Wei Huang , Yu-Peng Tsai , Chun-Cheng Lin , Chung-Shi Liu
发明人： Ming-Da Cheng , Chih-Wei Lin , Kuei-Wei Huang , Yu-Peng Tsai , Chun-Cheng Lin , Chung-Shi Liu
IPC分类号： H01L23/488 , H01L23/00
CPC分类号： H01L24/16 , H01L24/13 , H01L24/81 , H01L2224/05572 , H01L2224/1146 , H01L2224/11849 , H01L2224/13005 , H01L2224/13012 , H01L2224/13014 , H01L2224/1308 , H01L2224/13082 , H01L2224/1601 , H01L2224/16104 , H01L2224/16238 , H01L2224/81191 , H01L2224/81203 , H01L2224/81815 , H01L2224/8191 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/206 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The distance between the conductive pillar and the conductive trace is less than or equal to about 16 μm.

46. 发明授权

US09543185B2 Packaging process tools and systems, and packaging methods for semiconductor devices 有权
标题翻译：包装工艺和系统以及半导体器件的封装方法
公开(公告)号：US09543185B2
公开(公告)日：2017-01-10
申请号：US13309311
申请日：2011-12-01
申请人： Wei-Hung Lin , Kuei-Wei Huang , Chih-Wei Lin , Chun-Cheng Lin , Ming-Da Cheng , Chung-Shi Liu
发明人： Wei-Hung Lin , Kuei-Wei Huang , Chih-Wei Lin , Chun-Cheng Lin , Ming-Da Cheng , Chung-Shi Liu
IPC分类号： B23Q3/00 , H01L21/683 , H01L23/31 , H01L23/00 , H01L21/56
CPC分类号： H01L21/6835 , H01L21/561 , H01L21/563 , H01L23/3128 , H01L23/562 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/97 , H01L2221/68372 , H01L2224/0401 , H01L2224/05027 , H01L2224/05124 , H01L2224/05554 , H01L2224/05572 , H01L2224/05599 , H01L2224/11444 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/14135 , H01L2224/16225 , H01L2224/16238 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/75754 , H01L2224/7698 , H01L2224/81001 , H01L2224/81136 , H01L2224/81191 , H01L2224/81203 , H01L2224/81815 , H01L2224/81907 , H01L2224/83102 , H01L2224/9205 , H01L2224/92125 , H01L2224/95001 , H01L2224/97 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/3511 , H01L2924/3512 , H01L2924/3841 , Y10T29/41 , H01L2924/00 , H01L2224/81 , H01L2924/00012 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2224/05552 , H01L2924/013
摘要： Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.
摘要翻译：公开了用于半导体器件的封装加工工具和系统以及封装方法。在一个实施例中，用于半导体器件的封装处理工具包括用于在集成电路管芯的封装工艺期间支撑封装衬底或集成电路管芯的机械结构。机械结构包括设置在其上的低热导率材料。

47. 发明申请

US20150018484A1 POLYIMIDE FILM AND FABRICATION METHOD THEREOF 有权
标题翻译：聚酰亚胺膜及其制造方法
公开(公告)号：US20150018484A1
公开(公告)日：2015-01-15
申请号：US14249702
申请日：2014-04-10
申请人： Chih-Wei Lin , Meng-Ying Tsai
发明人： Chih-Wei Lin , Meng-Ying Tsai
IPC分类号： C08J5/18 , B29C39/00
CPC分类号： C08J5/18 , B29C39/003 , B29K2079/08 , B29K2105/0032 , C08G73/1067 , C08G73/1071 , C08J2379/08 , C09D179/08
摘要： A polyimide film includes a polyimide polymer forming a main molecular structure of the polyimide film, and polyimide particles present in the polyimide film at a weight ratio between about 15 wt % and 30 wt % of a total weight of the polyimide film, the polyimide particles having an average diameter between about 3 μm and 8 μm. The polyimide film can have a 60° gloss value equal to or smaller than 10, a haze equal to or higher than 90%, and a Young's modulus equal to or higher than 280 kgf/mm2. In some embodiments, methods of fabricating the polyimide film are also described.
摘要翻译：聚酰亚胺膜包括形成聚酰亚胺膜的主要分子结构的聚酰亚胺聚合物和以聚酰亚胺膜的总重量的约15重量％至30重量％的重量比存在于聚酰亚胺膜中的聚酰亚胺颗粒，聚酰亚胺颗粒平均直径约3μm至8μm。聚酰亚胺膜可以具有等于或小于10的60°光泽值，雾度等于或高于90％，杨氏模量等于或高于280kgf / mm2。在一些实施例中，还描述了制造聚酰亚胺膜的方法。

48. 发明授权

US08703546B2 Activation treatments in plating processes 有权
标题翻译：电镀工艺中的激活处理
公开(公告)号：US08703546B2
公开(公告)日：2014-04-22
申请号：US12784314
申请日：2010-05-20
申请人： Chih-Wei Lin , Ming-Da Cheng , Ming-Che Ho , Chung-Shi Liu
发明人： Chih-Wei Lin , Ming-Da Cheng , Ming-Che Ho , Chung-Shi Liu
IPC分类号： H01L21/82 , H01L21/288
CPC分类号： H01L21/288 , C25D7/123 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03831 , H01L2224/0401 , H01L2224/05166 , H01L2224/05181 , H01L2224/05572 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/11424 , H01L2224/11462 , H01L2224/11464 , H01L2224/11622 , H01L2224/1181 , H01L2224/11901 , H01L2224/1308 , H01L2224/13083 , H01L2224/13118 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/93 , H01L2924/00013 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2224/11 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552 , H01L2924/00 , H01L2224/1146
摘要： A method of forming a device includes performing a first plating process to form a first metallic feature, and performing an activation treatment to a surface of the first metallic feature in an activation treatment solution, wherein the activation treatment solution includes a treatment agent in de-ionized (DI) water. After the step of performing the activation treatment, performing a second plating process to form a second metallic feature and contacting the surface of the first metallic feature.
摘要翻译：一种形成装置的方法包括进行第一电镀工艺以形成第一金属特征，并且在活化处理溶液中对第一金属特征的表面进行活化处理，其中活化处理溶液包括处理剂，电离（DI）水。在执行激活处理的步骤之后，执行第二电镀处理以形成第二金属特征并接触第一金属特征的表面。

49. 发明申请

US20130093097A1 Package-On-Package (PoP) Structure and Method 有权
标题翻译：封装封装（PoP）结构和方法
公开(公告)号：US20130093097A1
公开(公告)日：2013-04-18
申请号：US13271952
申请日：2011-10-12
申请人： Chen-Hua Yu , Chung-Shi Liu , Mirng-Ji Lii , Ming-Da Cheng , Chih-Wei Lin
发明人： Chen-Hua Yu , Chung-Shi Liu , Mirng-Ji Lii , Ming-Da Cheng , Chih-Wei Lin
IPC分类号： H01L23/48 , H01L21/56
CPC分类号： H01L25/50 , H01L21/31051 , H01L21/4846 , H01L21/4853 , H01L21/4857 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/76802 , H01L21/76819 , H01L21/76877 , H01L21/76898 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5383 , H01L24/16 , H01L24/19 , H01L24/32 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L2221/68345 , H01L2224/04105 , H01L2224/12105 , H01L2224/13082 , H01L2224/131 , H01L2224/16225 , H01L2224/16237 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/73204 , H01L2224/73253 , H01L2224/73267 , H01L2224/81005 , H01L2224/81191 , H01L2224/81815 , H01L2224/83104 , H01L2225/06513 , H01L2225/06548 , H01L2225/06555 , H01L2225/06572 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H05K1/185 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2924/0665 , H01L2224/48
摘要： A package-on-package (PoP) structure comprises a first package and a second package. The first package comprises a first die, a second die, and a core material. The core material has a first surface and a second surface. A first redistribution layer (RDL) is on the first surface, and a second RDL is on the second surface. The first die is disposed in the core material between the first surface and the second surface. The second die is coupled to one of the first RDL and the second RDL. The second package comprises a third die and an interposer. The interposer has a first side and a second side. The third die is coupled to the second side of the interposer. The first package is coupled to the second package by first electrical connectors coupled to the second side of the interposer and the first RDL.
摘要翻译：封装封装（PoP）结构包括第一封装和第二封装。第一包装包括第一模具，第二模具和芯材料。芯材料具有第一表面和第二表面。第一再分配层（RDL）位于第一表面上，第二RDL位于第二表面上。第一模具设置在第一表面和第二表面之间的芯材料中。第二管芯耦合到第一RDL和第二RDL之一。第二包装包括第三管芯和插入件。插入器具有第一侧和第二侧。第三裸片耦合到插入器的第二侧。第一封装通过耦合到插入件的第二侧和第一RDL的第一电连接器耦合到第二封装。

50. 发明申请

US20120181669A1 FRAME CELL FOR SHOT LAYOUT FLEXIBILITY 有权
标题翻译：用于拍摄布局灵活性的框架单元
公开(公告)号：US20120181669A1
公开(公告)日：2012-07-19
申请号：US13409517
申请日：2012-03-01
申请人： Chin-Ming LIN , Chia-hung Huang , Chi-Ming Yang , Chin-Hsiang Lin , Yung-Cheng Chen , Chih-Wei Lin
发明人： Chin-Ming LIN , Chia-hung Huang , Chi-Ming Yang , Chin-Hsiang Lin , Yung-Cheng Chen , Chih-Wei Lin
IPC分类号： H01L23/544 , G06F17/50
CPC分类号： G03F7/70433
摘要： A method includes establishing an initial shot layout in which a number of shots are arranged in vertically aligned columns and horizontally aligned rows to cover a semiconductor wafer. At least one of a row of shots or a column of shots is shifted relative to an adjacent row or column of shots to establish at least one additional shot layout that differs from the initial shot layout in that shots in the at least one shifted row or column of shots are not aligned with the shots in the adjacent row or column of shots with which they were aligned in the initial shot layout. One of the initial shot layout and the at least one additional shot layout is selected as a final shot layout. The wafer is exposed to light using the final shot layout.
摘要翻译：一种方法包括建立初始照片布局，其中多个照片布置在垂直排列的列和水平排列的行中以覆盖半导体晶片。一排照片或一列照片中的至少一列相对于相邻的行或列发射位移，以建立与至少一个移位行中的拍摄中的初始镜头布局不同的至少一个附加镜头布局，或一列照片不与在初始镜头布局中对齐的相邻行或照片列中的镜头对齐。选择初始镜头布局和至少一个附加镜头布局之一作为最终镜头布局。使用最终镜头布局将晶片曝光。

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