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41. 发明授权

US6064216A Apparatus for testing semiconductor wafers 有权
标题翻译：半导体晶片测试装置
公开(公告)号：US6064216A
公开(公告)日：2000-05-16
申请号：US241553
申请日：1999-02-01
申请人： Warren M. Farnworth , Salman Akram , Alan G. Wood , David R. Hembree , James M. Wark , John O. Jacobson
发明人： Warren M. Farnworth , Salman Akram , Alan G. Wood , David R. Hembree , James M. Wark , John O. Jacobson
IPC分类号： G01R1/04 , G01R31/28 , G01R31/02
CPC分类号： G01R1/0491 , G01R31/2886
摘要： A method, apparatus and system for testing semiconductor wafers are provided. The method includes providing a wafer carrier to provide an electrical path for receiving and transmitting test signals to the wafer. The wafer carrier includes a base for retaining the wafer, and an interconnect having contact members configured to establish electrical communication with contact locations on the wafer. The wafer carrier can include one or more compressible spring members configured to bias the wafer and interconnect together in the assembled carrier. The wafer carrier can be assembled, with the wafer in alignment with the interconnect, using optical alignment techniques, and an assembly tool similar to aligner bonder tools used for flip chip bonding semiconductor dice. A system for use with the carrier can include a testing apparatus configured to apply test signals through the carrier to the wafer while the wafer is subjected to temperature cycling.
摘要翻译：提供了一种用于测试半导体晶片的方法，装置和系统。该方法包括提供晶片载体以提供用于接收和传输测试信号到晶片的电路径。晶片载体包括用于保持晶片的基座和具有被配置为与晶片上的接触位置建立电连通的接触构件的互连。晶片载体可以包括被配置为偏置晶片并在组装的载体中互连在一起的一个或多个可压缩弹簧构件。可以使用光学对准技术来组装晶片载体，其中晶片与互连对准，以及类似于用于倒装芯片接合半导体晶片的对准器焊接工具的组装工具。与载体一起使用的系统可以包括测试装置，其被配置为在晶片受到温度循环的同时将测试信号通过载体施加到晶片。

42. 发明授权

US6060893A Carrier having slide connectors for testing unpackaged semiconductor dice 失效
标题翻译：载体具有用于测试未封装的半导体骰子的滑动连接器
公开(公告)号：US6060893A
公开(公告)日：2000-05-09
申请号：US976846
申请日：1997-11-24
申请人： Warren M. Farnworth , Salman Akram , Mike Brooks
发明人： Warren M. Farnworth , Salman Akram , Mike Brooks
IPC分类号： G01R1/04 , G01R1/067 , G01R1/073 , G01R3/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L21/68 , H01L23/13 , H01L23/498 , H05K3/00 , H05K3/42 , G01R31/02
CPC分类号： G01R1/0466 , G01R1/0483 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/80 , H01L24/85 , H05K3/4007 , G01R3/00 , G01R31/2863 , H01L2224/16145 , H01L2224/451 , H01L2224/48 , H01L2224/85001 , H01L2225/06562 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H05K3/0058 , H05K3/0067 , H05K3/423
摘要： A carrier for testing an unpackaged semiconductor die is provided. The carrier comprises a base for holding the die, an interconnect for establishing a temporary electrical connection with the die, and a force applying mechanism for biasing the die and interconnect together. The base includes external contacts arranged as flat metal pads in a dense grid array and electrically connected to a pattern of contact pads. The carrier also includes a pair of slide connector members which provide an electrical p ath between the contact pads on the base and corresponding contact pads on the interconnect. The slide connector members can be formed of molded plastic or ceramic and include tine contacts that slidably engage the contact pads on the interconnect and base. The slide connector members permit the interconnect to be easily replaced for testing of different types of dice.
摘要翻译：提供了用于测试未封装的半导体管芯的载体。载体包括用于保持模具的基座，用于建立与模具的临时电连接的互连件，以及用于偏压模具并互连在一起的施力机构。底座包括以致密网格阵列布置成平坦金属焊盘并电连接到接触焊盘图案的外部触点。载体还包括一对滑动连接器构件，其在基座上的接触焊盘和互连件上的对应接触垫之间提供电气连接。滑动连接器构件可以由模制塑料或陶瓷形成，并且包括滑动接合互连和底座上的接触垫的齿接触。滑动连接器构件允许容易地替换互连以测试不同类型的骰子。

43. 发明授权

US6040239A Non-oxidizing touch contact interconnect for semiconductor test systems and method of fabrication 失效
标题翻译：用于半导体测试系统的非氧化触点互连和制造方法
公开(公告)号：US6040239A
公开(公告)日：2000-03-21
申请号：US916892
申请日：1997-08-22
申请人： Salman Akram , Warren M. Farnworth
发明人： Salman Akram , Warren M. Farnworth
IPC分类号： G01R1/04 , G01R1/067 , G01R3/00 , H01L21/60 , H01L21/44 , H01L21/66
CPC分类号： G01R1/06761 , H01L24/11 , G01R1/0466 , G01R3/00 , H01L2224/05571 , H01L2224/05573 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/0104 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14
摘要： An interconnect for testing semiconductor components including dice, wafers, and chip scale packages, is provided. The interconnect includes: a substrate; contact members formed on the substrate configured to make temporary electrical connections with the components; and conductors and bonding pads on the substrate for providing electrical paths to the contact members. The contact members, conductors and bonding pads can be covered with an electrolessly deposited barrier layer, and an electrolessly deposited non-oxidizing layer. The non-oxidizing layer on the contact members forms a touch contact surface for forming low resistance electrical connections with the contacts on the components. Preferred materials for the non-oxidizing layer include palladium, gold, tungsten and platinum. Also provided are a method for fabricating the interconnect, and test systems employing the interconnect.
摘要翻译：提供了用于测试包括晶片，晶片和芯片级封装的半导体元件的互连。互连包括：衬底; 形成在所述基板上的接触构件被构造成与所述部件进行临时电连接; 以及衬底上的导体和接合焊盘，用于提供到接触构件的电路径。接触构件，导体和接合焊盘可被无电沉积的阻挡层和无电沉积的非氧化层覆盖。接触构件上的非氧化层形成用于与部件上的触点形成低电阻电连接的触摸接触表面。用于非氧化层的优选材料包括钯，金，钨和铂。还提供了制造互连的方法以及采用互连的测试系统。

44. 发明授权

US6028365A Integrated circuit package and method of fabrication 失效
标题翻译：集成电路封装及其制造方法
公开(公告)号：US6028365A
公开(公告)日：2000-02-22
申请号：US49939
申请日：1998-03-30
申请人： Salman Akram , Warren M. Farnworth
发明人： Salman Akram , Warren M. Farnworth
IPC分类号： H01L23/31 , H01L25/10 , H05K3/30 , H05K3/34 , H05K3/36 , H01L23/48 , H01L23/34
CPC分类号： H05K3/305 , H01L23/3107 , H01L25/105 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/00014 , H01L2924/01079 , H01L2924/12044 , H01L2924/15331 , H05K2201/10689 , H05K3/3436 , H05K3/363 , Y02P70/613
摘要： The present invention is directed to a semiconductor package and its method of manufacture. Conductors mounted on a flexible polymer tape are used to connect a semiconductor chip to a substrate. The flexible polymer tape can be folded back under the chip to reduce the size necessary for mounting the assembly to almost that of the chip itself. The polymer tape also provides flexibility to reduce stresses on the electrical connections caused by thermal expansion and compression. Additionally, the present invention allows for the stacking of semiconductor chips on top of one another, reducing signal propagation delays between them.
摘要翻译：本发明涉及半导体封装及其制造方法。安装在柔性聚合物胶带上的导体用于将半导体芯片连接到基板。柔性聚合物带可以折叠在芯片下方，以减小将组件安装到芯片本身几乎所需的尺寸。聚合物胶带还提供灵活性，以减少由热膨胀和压缩引起的电连接上的应力。此外，本发明允许将半导体芯片堆叠在一起，减少它们之间的信号传播延迟。

45. 发明授权

US6002180A Multi chip module with conductive adhesive layer 失效
标题翻译：多芯片模块带导电胶层
公开(公告)号：US6002180A
公开(公告)日：1999-12-14
申请号：US65361
申请日：1998-04-23
申请人： Salman Akram , Alan G. Wood , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , Warren M. Farnworth
IPC分类号： H01L21/56 , H01L21/60 , H01L23/13 , H05K3/32 , H05K3/40 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/83 , H01L21/563 , H01L23/13 , H01L24/29 , H01L24/81 , H01L2224/1319 , H01L2224/29101 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/73203 , H01L2224/81801 , H01L2224/8319 , H01L2224/838 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/07811 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/15151 , H01L2924/30105 , H05K3/321 , H05K3/4007
摘要： A method for forming a chip module such as a multi chip module or a memory module is provided. The multi chip module includes a substrate configured to mount a plurality of semiconductor dice thereon. The substrate includes raised contact members formed in patterns that correspond to the locations of bond pads on the dice. An anisotropic conductive adhesive layer is formed between the contact members on the substrate and the bond pads on the dice to secure the dice to the substrate and form an electrical connection therebetween. In addition, an underfill layer can be formed between the dice and substrate to fill the gap therebetween and further secure the dice to the substrate. Conductors and input/output pads formed on the substrate form electrical paths to and from the contact members. To form a memory module, one or more multi chip modules can be mounted to a supporting substrate having an edge connector in electrical communication with the conductors and with contact members on the substrates.
摘要翻译：提供了一种用于形成诸如多芯片模块或存储器模块的芯片模块的方法。多芯片模块包括被配置为在其上安装多个半导体晶片的衬底。衬底包括形成为对应于骰子上的接合焊盘的位置的图案的凸起接触构件。在基板上的接触构件和骰子上的接合垫之间形成各向异性导电粘合剂层，以将骰子固定到基板上并在其间形成电连接。此外，可以在骰子和衬底之间形成底部填充层以填充它们之间的间隙，并进一步将骰子固定到衬底上。形成在基板上的导体和输入/输出焊盘形成到和接触构件的电路。为了形成存储器模块，可以将一个或多个多芯片模块安装到具有与导体电连通的边缘连接器和基板上的接触部件的支撑基板。

46. 发明授权

US5925930A IC contacts with palladium layer and flexible conductive epoxy bumps 失效
标题翻译： IC接触钯层和柔性导电环氧树脂凸块
公开(公告)号：US5925930A
公开(公告)日：1999-07-20
申请号：US651816
申请日：1996-05-21
申请人： Warren M. Farnworth , Salman Akram
发明人： Warren M. Farnworth , Salman Akram
IPC分类号： H01L21/288 , H01L21/48 , H01L21/56 , H01L21/60 , H01L23/485 , H01L23/498 , H05K3/24 , H05K3/32 , H01L23/48
CPC分类号： H01L24/81 , H01L21/288 , H01L21/4853 , H01L21/563 , H01L23/49816 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/29 , H01L24/75 , H01L24/83 , H05K3/321 , H01L2224/13099 , H01L2224/1319 , H01L2224/16225 , H01L2224/29101 , H01L2224/2919 , H01L2224/29298 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/75 , H01L2224/81801 , H01L2224/8319 , H01L2224/838 , H01L2924/00013 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/10253 , H01L2924/12044 , H01L2924/14 , H05K2201/10674 , H05K2201/10977 , H05K2201/10984 , H05K3/244
摘要： An apparatus and method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a two-stage epoxy, on the palladium plated contact point. The present invention also relates to assemblies comprising one or more of these substrates.
摘要翻译：一种用于在所述镀钯触点上形成具有钯金属层的衬底的装置和方法，所述衬底在所述衬底的至少一个接触点上并且具有柔性导电聚合物凸点，优选两级环氧树脂。本发明还涉及包括一个或多个这些基底的组件。

47. 发明授权

US5915977A System and interconnect for making temporary electrical connections with bumped semiconductor components 有权
标题翻译：用于与凸起的半导体部件进行临时电连接的系统和互连
公开(公告)号：US5915977A
公开(公告)日：1999-06-29
申请号：US138612
申请日：1998-08-24
申请人： David R. Hembree , John O. Jacobson , James M. Wark , Warren M. Farnworth , Salman Akram , Alan G. Wood
发明人： David R. Hembree , John O. Jacobson , James M. Wark , Warren M. Farnworth , Salman Akram , Alan G. Wood
IPC分类号： G01R1/04 , H01L21/00 , H01R12/04 , H05K3/32 , H01R9/09
CPC分类号： H01L21/67144 , G01R1/0408 , H05K3/326 , H01L2224/1601 , H01L2224/16237 , H01L2224/81141 , H01L2224/81191 , H01L2224/81385
摘要： An interconnect and system for establishing temporary electrical communication with semiconductor components having contact bumps are provided. The interconnect includes a substrate with patterns of contact members adapted to electrically contact the contact bumps. The substrate can be formed of a material such as ceramic, silicon, FR-4, or photo-chemically machineable glass. The contact members can be formed as recesses covered with conductive layers in electrical communication with conductors and terminal contacts on the substrate. Alternately, the contact members can be formed as projections adapted to penetrate the contact bumps, as microbumps with a rough textured surface, or as a deposited layer formed with recesses. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare bumped dice or bumped chip scale packages.
摘要翻译：提供了一种用于与具有接触凸块的半导体部件建立临时电连通的互连和系统。互连包括具有适于电接触接触凸块的接触部件图案的基板。衬底可由诸如陶瓷，硅，FR-4或光刻化学可加工玻璃的材料形成。接触构件可以形成为覆盖有与衬底上的导体和端子触点电连通的导电层的凹陷。或者，接触构件可以形成为适于穿透接触凸块的突起，作为具有粗糙纹理表面的微胶囊，或者形成为具有凹陷的沉积层。互连可以用于晶片级测试系统中，用于测试包含在晶片上的骰子，或者用于测试裸露的骰子或凸起的芯片级封装的芯片级测试系统。

48. 发明授权

US5801452A Multi chip module including semiconductor wafer or dice, interconnect substrate, and alignment member 失效
标题翻译：包括半导体晶片或芯片，互连基板和对准部件的多芯片模块
公开(公告)号：US5801452A
公开(公告)日：1998-09-01
申请号：US736998
申请日：1996-10-25
申请人： Warren M. Farnworth , Salman Akram
发明人： Warren M. Farnworth , Salman Akram
IPC分类号： H01L21/98 , H01L23/13 , H01L23/48 , H01L25/065 , G01R1/02 , H01L23/34 , H05K3/02
CPC分类号： H01L25/50 , H01L23/13 , H01L24/72 , H01L25/0655 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/14
摘要： An improved multi chip module (MCM) and a method for forming the multi chip module are provided. The multi chip module includes a semiconductor wafer and an interconnect substrate having contact members adapted to establish electrical communication with dice contained on the wafer. The contact members can be formed as etched pillars with penetrating projections or as microbumps on a flexible tape. An alignment plate associated with the interconnect substrate includes an alignment opening adapted to mechanically align bond pads, or other contact locations, on the wafer with the contact members on the interconnect substrate. The multi chip module also includes a force applying member in the form of a compressible bladder or elastomeric member, adapted to press the wafer against the interconnect substrate. In an alternate embodiment, the multi chip module includes tested singulated dice and the alignment plate includes multiple alignment openings.
摘要翻译：提供了一种改进的多芯片模块（MCM）和一种用于形成多芯片模块的方法。多芯片模块包括半导体晶片和具有适于与晶片上包含的裸片建立电连通的接触部件的互连基板。接触构件可以形成为具有穿透突出部的蚀刻柱或柔性带上的微丸。与互连衬底相关联的对准板包括适于将晶片上的接合焊盘或其它接触位置与互连衬底上的接触构件机械对准的对准开口。多芯片模块还包括可压缩囊或弹性体构件形式的施力构件，其适于将晶片压靠在互连衬底上。在替代实施例中，多芯片模块包括经测试的单个裸片，对准板包括多个对准开口。

49. 发明授权

US5789278A Method for fabricating chip modules 失效
标题翻译：制造芯片模块的方法
公开(公告)号：US5789278A
公开(公告)日：1998-08-04
申请号：US688368
申请日：1996-07-30
申请人： Salman Akram , Alan G. Wood , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , Warren M. Farnworth
IPC分类号： H01L21/56 , H01L21/60 , H01L23/13 , H05K3/32 , H05K3/40 , H01L21/44
CPC分类号： H01L24/83 , H01L21/563 , H01L23/13 , H01L24/29 , H01L24/81 , H01L2224/1319 , H01L2224/29101 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/73203 , H01L2224/81801 , H01L2224/8319 , H01L2224/838 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/07811 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/15151 , H01L2924/30105 , H05K3/321 , H05K3/4007
摘要： A method for forming a chip module such as a multi chip module or a memory module is provided. The multi chip module includes a substrate configured to mount a plurality of semiconductor dice thereon. The substrate includes raised contact members formed in patterns that correspond to the locations of bond pads on the dice. An anisotropic conductive adhesive layer is formed between the contact members on the substrate and the bond pads on the dice to secure the dice to the substrate and form an electrical connection therebetween. In addition, an underfill layer can be formed between the dice and substrate to fill the gap therebetween and further secure the dice to the substrate. Conductors and input/output pads formed on the substrate form electrical paths to and from the contact members. To form a memory module, one or more multi chip modules can be mounted to a supporting substrate having an edge connector in electrical communication with the conductors and with contact members on the substrates.
摘要翻译：提供了一种用于形成诸如多芯片模块或存储器模块的芯片模块的方法。多芯片模块包括被配置为在其上安装多个半导体晶片的衬底。衬底包括形成为对应于骰子上的接合焊盘的位置的图案的凸起接触构件。在基板上的接触构件和骰子上的接合垫之间形成各向异性导电粘合剂层，以将骰子固定到基板上并在其间形成电连接。此外，可以在骰子和衬底之间形成底部填充层以填充它们之间的间隙，并进一步将骰子固定到衬底上。形成在基板上的导体和输入/输出焊盘形成到和接触构件的电路。为了形成存储器模块，可以将一个或多个多芯片模块安装到具有与导体电连通的边缘连接器和基板上的接触部件的支撑基板。

50. 发明授权

US07960829B2 Support structure for use in thinning semiconductor substrates and for supporting thinned semiconductor substrates 有权
标题翻译：用于减薄半导体衬底和用于支撑薄化半导体衬底的支撑结构
公开(公告)号：US07960829B2
公开(公告)日：2011-06-14
申请号：US11216617
申请日：2005-08-31
申请人： Alan G. Wood , Warren M. Farnworth , David R. Hembree , Sidney B. Rigg , William M. Hiatt , Peter Benson , Kyle K. Kirby , Salman Akram
发明人： Alan G. Wood , Warren M. Farnworth , David R. Hembree , Sidney B. Rigg , William M. Hiatt , Peter Benson , Kyle K. Kirby , Salman Akram
IPC分类号： H01L23/12
CPC分类号： G03F7/0037 , B33Y30/00 , B33Y70/00 , B33Y80/00 , G03F7/0047
摘要： A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion that extends substantially along and around an outer periphery of the semiconductor substrate to impart the thinned semiconductor substrate with rigidity. The support structure may be configured as a ring or as a member that substantially covers an active surface of the semiconductor substrate and forms a protective structure over each semiconductor device carried by the active surface.
摘要翻译：用于半导体衬底的减薄或后研磨以及在半导体衬底的后变薄处理期间的支撑结构包括基本上沿着半导体衬底的外周延伸并围绕半导体衬底的外周延伸的部分，以使半导体衬底基板具有刚性。支撑结构可以被构造为环或作为基本上覆盖半导体衬底的有源表面并且在由有源表面承载的每个半导体器件上形成保护结构的构件。

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