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41. 发明授权

US08629029B2 Vertical SOI bipolar junction transistor and manufacturing method thereof 失效
标题翻译：垂直SOI双极结型晶体管及其制造方法
公开(公告)号：US08629029B2
公开(公告)日：2014-01-14
申请号：US13055577
申请日：2010-07-14
申请人： Jing Chen , Jiexin Luo , Qingqing Wu , Jianhua Zhou , Xiaolu Huang , Xi Wang
发明人： Jing Chen , Jiexin Luo , Qingqing Wu , Jianhua Zhou , Xiaolu Huang , Xi Wang
IPC分类号： H01L21/331
CPC分类号： H01L29/7317 , H01L29/66265
摘要： The present invention discloses a vertical SOI bipolar junction transistor and a manufacturing method thereof. The bipolar junction transistor includes an SOI substrate from down to up including a body region, a buried oxide layer and a top silicon film; an active region located in the top silicon film formed by STI process; a collector region located in the active region deep close to the buried oxide layer formed by ion implantation; a base region located in the active region deep close to the top silicon film formed by ion implantation; an emitter and a base electrode both located over the base region; a side-wall spacer located around the emitter and the base electrode. The present invention utilizing a simple double poly silicon technology not only can improve the performance of the transistor, but also can reduce the area of the active region in order to increase the integration density. Furthermore, the present invention utilizes side-wall spacer process to improve the compatibility of SOI BJT and SOI CMOS, which simplifies the SOI BiCMOS process and thus reduce the cost.
摘要翻译：本发明公开了一种垂直SOI双极结型晶体管及其制造方法。双极结型晶体管包括从下到上的包括主体区域，掩埋氧化物层和顶部硅膜的SOI衬底; 位于由STI工艺形成的顶部硅膜中的有源区; 位于靠近由离子注入形成的掩埋氧化物层的有源区域的集电极区域; 位于靠近通过离子注入形成的顶部硅膜的深度的有源区域中的基极区域; 发射极和基极两者都位于基极区域之上; 位于发射极和基极周围的侧壁间隔物。利用简单的双重多晶硅技术的本发明不仅可以改善晶体管的性能，而且可以减小有源区的面积，以增加集成密度。此外，本发明利用侧壁间隔物工艺来改善SOI BJT和SOI CMOS的相容性，这简化了SOI BiCMOS工艺，从而降低了成本。

42. 发明授权

US08600054B2 Method, apparatus, and system for preventing abuse of authentication vector 有权
标题翻译：用于防止认证向量滥用的方法，装置和系统
公开(公告)号：US08600054B2
公开(公告)日：2013-12-03
申请号：US12892757
申请日：2010-09-28
申请人： Yanmei Yang , Yixian Xu , Jing Chen
发明人： Yanmei Yang , Yixian Xu , Jing Chen
IPC分类号： H04L9/32
CPC分类号： H04W12/04 , H04W12/10 , H04W12/12
摘要： A method for preventing abuse of an Authentication Vector (AV) and a system and apparatus for implementing the method are provided. Access network information of a non-3rd Generation Partnership Project (3GPP) access network where a user resides is bound to an AV of the user, so that when the user accesses an Evolved Packet System (EPS) through the non-3GPP access network, even if an entity in the non-3GPP access network is breached, or an Evolved Packet Data Gateway (ePDG) connected to an untrusted non-3GPP access network is breached, the stolen AV cannot be applied to other non-3GPP access networks by an attacker.
摘要翻译：提供了防止认证向量（AV）的滥用的方法以及用于实现该方法的系统和装置。用户驻留的非第三代合作伙伴计划（3GPP）接入网络的接入网络信息被绑定到用户的AV，使得当用户通过非3GPP接入网络访问演进分组系统（EPS）时，即使违反非3GPP接入网络中的实体，或者违反连接到非信任非3GPP接入网络的演进分组数据网关（ePDG），则被盗AV不能通过以下方式应用于其他非3GPP接入网络攻击者

43. 发明授权

US08564394B2 Power module and circuit board assembly thereof 有权
标题翻译：电源模块及其电路板组件
公开(公告)号：US08564394B2
公开(公告)日：2013-10-22
申请号：US13408631
申请日：2012-02-29
申请人： Han Li , Gang Liu , Jing Chen , Jinfa Zhang
发明人： Han Li , Gang Liu , Jing Chen , Jinfa Zhang
IPC分类号： H01F5/00
CPC分类号： H05K7/1432 , H01F27/292 , H01F2027/408 , H02M3/33592 , Y02B70/1475
摘要： A power module mounted on a system board comprises a printed circuit board having an extension part, at least one primary winding coil disposed on a first side of the extension part. The at least one primary winding coil is disposed at a primary side of the power module. The power module further comprises a PCB winding formed on the extension part at a secondary side of the power module, a first magnetic core assembly, and a connector. The first magnetic core assembly comprises a first magnetic part and a second magnetic part. The at least one primary winding coil and the extension part are enclosed between the first magnetic part and the second magnetic part.
摘要翻译：安装在系统板上的功率模块包括具有延伸部分的印刷电路板，设置在延伸部分的第一侧上的至少一个初级绕组线圈。所述至少一个初级绕组线圈设置在所述功率模块的初级侧。功率模块还包括形成在功率模块的次级侧的延伸部分上的PCB绕组，第一磁芯组件和连接器。第一磁芯组件包括第一磁性部分和第二磁性部分。所述至少一个初级绕组线圈和所述延伸部分被封装在所述第一磁性部分和所述第二磁性部分之间。

44. 发明授权

US08564020B2 Transistors and rectifiers utilizing hybrid electrodes and methods of fabricating the same 有权
标题翻译：使用混合电极的晶体管和整流器及其制造方法
公开(公告)号：US08564020B2
公开(公告)日：2013-10-22
申请号：US12843313
申请日：2010-07-26
申请人： Jing Chen , Chunhua Zhou
发明人： Jing Chen , Chunhua Zhou
IPC分类号： H01L29/66
CPC分类号： H01L29/7786 , H01L21/28575 , H01L29/1029 , H01L29/2003 , H01L29/205 , H01L29/41725 , H01L29/42312 , H01L29/66212 , H01L29/66462 , H01L29/872
摘要： Systems, methods, and apparatus described herein are associated with devices including hybrid electrodes. A heterostructure semiconductor transistor can include a III-N-type semiconductor heterostructure including a barrier layer overlying an active layer and a hybrid electrode region including a hybrid drain electrode region. Further, a heterostructure semiconductor rectifier can include a III-N-type semiconductor heterostructure and a hybrid electrode region including a hybrid cathode electrode region. Furthermore, the hybrid electrode region of the transistor and rectifier can include permanently trapped charge located under a Schottky contact of the hybrid electrode region.
摘要翻译：本文描述的系统，方法和装置与包括混合电极的装置相关联。异质结构半导体晶体管可以包括包括有源层上的阻挡层的III-N型半导体异质结构和包括混合漏电极区的混合电极区。此外，异质结构半导体整流器可以包括III-N型半导体异质结构和包括混合阴极电极区的混合电极区。此外，晶体管和整流器的混合电极区域可以包括位于混合电极区域的肖特基接触下的永久俘获的电荷。

45. 发明授权

US08450195B2 Method of reducing floating body effect of SOI MOS device via a large tilt ion implantation 有权
标题翻译：通过大型倾斜离子注入降低SOI MOS器件浮体效应的方法
公开(公告)号：US08450195B2
公开(公告)日：2013-05-28
申请号：US12937258
申请日：2010-07-14
申请人： Jing Chen , Xiaolu Huang , Jiexin Luo , Qingqing Wu , Xi Wang
发明人： Jing Chen , Xiaolu Huang , Jiexin Luo , Qingqing Wu , Xi Wang
IPC分类号： H01L21/425
CPC分类号： H01L21/26586 , H01L29/66545 , H01L29/78615
摘要： The present invention discloses a method of reducing floating body effect of SOI MOS device via a large tilt ion implantation including a step of: (a) implanting ions in an inclined direction into an NMOS with a buried insulation layer forming a highly doped P region under a source region of the NMOS and above the buried insulation layer, wherein the angle between a longitudinal line of the NMOS and the inclined direction is ranging from 15 to 45 degrees. Through this method, the highly doped P region under the source region and a highly doped N region form a tunnel junction so as to reduce the floating body effect. Furthermore, the chip area will not be increased, manufacturing process is simple and the method is compatible with conventional CMOS process.
摘要翻译：本发明公开了一种通过大的倾斜离子注入降低SOI MOS器件的浮体效应的方法，包括以下步骤：（a）将倾斜方向的离子注入到具有形成高掺杂P区的掩埋绝缘层的NMOS中 NMOS的源极区域和掩埋绝缘层之上，其中NMOS的纵向线与倾斜方向之间的角度为15至45度。通过这种方法，源区下的高掺杂P区和高掺杂N区形成隧道结，以减少浮体效应。此外，芯片面积不会增加，制造工艺简单，方法与常规CMOS工艺兼容。

46. 发明授权

US08422288B2 DRAM cell utilizing floating body effect and manufacturing method thereof 有权
标题翻译：利用浮体效应的DRAM单元及其制造方法
公开(公告)号：US08422288B2
公开(公告)日：2013-04-16
申请号：US12937257
申请日：2010-07-14
申请人： Deyuan Xiao , Xiaolu Huang , Jing Chen , Xi Wang
发明人： Deyuan Xiao , Xiaolu Huang , Jing Chen , Xi Wang
IPC分类号： G11C11/34
CPC分类号： H01L29/7841 , G11C11/404 , G11C2211/4016 , H01L27/10802
摘要： The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a P type semiconductor region provided on a buried oxide layer, an N type semiconductor region provided on the P type semiconductor region, a gate region provided on the N type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode of floating body effect is taken as a storage node. Via a tunneling effect between bands, electrons gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, electrons are emitted out from the floating body or holes are injected into the floating body, which is defined as a second storage state. The present invention provides a highly efficient DRAM cell utilizing floating body effect with high density, which has low power consumption, has simple manufacturing process, and is compatible to the conventional CMOS and conventional logic circuit manufacturing process.
摘要翻译：本发明公开了一种利用浮体效应的DRAM单元及其制造方法。 DRAM单元包括设置在掩埋氧化物层上的P型半导体区域，设置在P型半导体区域上的N型半导体区域，设置在N型半导体区域上的栅极区域和围绕P型半导体的电隔离区域区域和N型半导体区域。将浮体效应的二极管作为存储节点。通过带之间的隧道效应，电子聚集在浮体中，其被定义为第一存储状态; 通过PN结的正向偏压，电子从浮体发出，或者将空穴注入到浮动体中，其被定义为第二存储状态。本发明提供一种利用高密度的浮体效应的高效率DRAM单元，其具有低功耗，制造工艺简单，并且与常规CMOS和常规逻辑电路制造工艺兼容。

47. 发明授权

US08354714B2 SOI MOS device having BTS structure and manufacturing method thereof 有权
标题翻译：具有BTS结构的SOI MOS器件及其制造方法
公开(公告)号：US08354714B2
公开(公告)日：2013-01-15
申请号：US13132879
申请日：2010-09-07
申请人： Jing Chen , Jiexin Luo , Qingqing Wu , Xiaolu Huang , Xi Wang
发明人： Jing Chen , Jiexin Luo , Qingqing Wu , Xiaolu Huang , Xi Wang
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L29/78615 , H01L29/458 , H01L29/78621
摘要： The present invention discloses a SOI MOS device having BTS structure and manufacturing method thereof. The source region of the SOI MOS device comprises: two heavily doped N-type regions, a heavily doped P-type region formed between the two heavily doped N-type regions, a silicide formed above the heavily doped N-type regions and the heavily doped P-type region, and a shallow N-type region which is contact to the silicide; an ohmic contact is formed between the heavily doped P-type region and the silicide thereon to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof without increasing the chip area and also overcome the disadvantages such as decreased effective channel width of the devices in the BTS structure of the prior art. The manufacturing method comprises steps of: forming a heavily doped P-type region via ion implantation, forming a metal layer above the source region and forming a silicide via the heat treatment between the metal layer and the Si underneath. The device in the present invention could be fabricated via simplified fabricating process with great compatibility with traditional CMOS technology.
摘要翻译：本发明公开了一种具有BTS结构的SOI MOS器件及其制造方法。 SOI MOS器件的源极区域包括：两个重掺杂N型区域，形成在两个重掺杂N型区域之间的重掺杂P型区域，在重掺杂N型区域上形成的硅化物，掺杂P型区域和与硅化物接触的浅N型区域; 在重掺杂的P型区域和其上的硅化物之间形成欧姆接触以释放积聚在SOI MOS器件的体区中的空穴，并且消除其浮体效应而不增加芯片面积，并且还克服了诸如降低有效性现有技术的BTS结构中的设备的信道宽度。该制造方法包括以下步骤：通过离子注入形成重掺杂的P型区，在源区上方形成金属层，并通过金属层与Si之间的Si之间的热处理形成硅化物。本发明中的器件可以通过简化的制造工艺制造，与传统CMOS技术具有很好的兼容性。

48. 发明授权

US08354310B2 SOI MOS device having a source/body ohmic contact and manufacturing method thereof 有权
标题翻译：具有源/体欧姆接触的SOI MOS器件及其制造方法
公开(公告)号：US08354310B2
公开(公告)日：2013-01-15
申请号：US13131126
申请日：2010-09-07
申请人： Jing Chen , Qingqing Wu , Jiexin Luo , Xiaolu Huang , Xi Wang
发明人： Jing Chen , Qingqing Wu , Jiexin Luo , Xiaolu Huang , Xi Wang
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336 , H01L21/8234 , H01L21/331
CPC分类号： H01L29/458 , H01L29/66772 , H01L29/78615 , H01L29/78621
摘要： The present invention discloses a manufacturing method of SOI MOS device having a source/body ohmic contact. The manufacturing method comprises steps of: firstly creating a gate region, then performing high dose source and drain light doping to form the lightly doped N-type source region and lightly doped N-type drain region; forming an insulation spacer surrounding the gate region; performing large tilt heavily-doped P ion implantation in an inclined direction via a mask with an opening at the position of the N type Si source region and implanting P ions into the space between the N type Si source region and the N type drain region to form a heavily-doped P-type region; finally forming a metal layer on the N type Si source region, then allowing the reaction between the metal layer and the remained Si material underneath to form silicide by heat treatment. In the device prepared by the method of the present invention, an ohmic contact is formed between the silicide and the heavily-doped P-type region nearby in order to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof. Besides, the device of the present invention also has following advantages, such as limited chip area, simplified fabricating process and great compatibility with traditional CMOS technology.
摘要翻译：本发明公开了一种具有源/体欧姆接触的SOI MOS器件的制造方法。该制造方法包括以下步骤：首先产生栅极区域，然后进行高剂量源和漏极掺杂以形成轻掺杂的N型源极区域和轻掺杂的N型漏极区域; 形成围绕所述栅极区域的绝缘间隔物; 通过在N型Si源极区域的位置处具有开口的掩模在倾斜方向上进行大倾斜重掺杂P离子注入，并且将P离子注入到N型Si源极区域和N型漏极区域之间的空间中，以形成重掺杂P型区; 最后在N型Si源区上形成金属层，然后通过热处理使金属层与下面残留的Si材料之间的反应形成硅化物。在通过本发明的方法制备的器件中，在硅化物和附近的重掺杂P型区域之间形成欧姆接触，以释放积累在SOI MOS器件的体区中的空穴并消除浮体效应其中。此外，本发明的器件还具有以下优点，例如有限的芯片面积，简化的制造工艺和与传统CMOS技术的很好的兼容性。

49. 发明授权

US08330228B2 Hybrid material inversion mode GAA CMOSFET 失效
标题翻译：混合材料反演模式GAA CMOSFET
公开(公告)号：US08330228B2
公开(公告)日：2012-12-11
申请号：US12810694
申请日：2010-02-11
申请人： Deyuan Xiao , Xi Wang , Miao Zhang , Jing Chen , Zhongying Xue
发明人： Deyuan Xiao , Xi Wang , Miao Zhang , Jing Chen , Zhongying Xue
IPC分类号： H01L27/092
CPC分类号： H01L27/1211 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L29/42392
摘要： A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device.
摘要翻译： Ge和Si混合材料反转模式GAA（Gate-All-Around）CMOSFET包括具有第一沟道的PMOS区域，具有第二沟道的NMOS区域和栅极区域。第一通道和第二通道具有圆形截面并分别由n型Ge和p型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。在反相模式下，电流流过整个圆柱形通道，以实现高载流子迁移率，降低低频噪声，防止多晶硅栅极耗尽和短沟道效应，并增加器件的阈值电压。

50. 发明授权

US08291365B2 Conditionally routing a portion of an integrated circuit design with a different pitch to overcome a design rule violation 有权
标题翻译：有条件地以不同的音调路由集成电路设计的一部分，以克服违反设计规则
公开(公告)号：US08291365B2
公开(公告)日：2012-10-16
申请号：US11327226
申请日：2006-01-06
申请人： Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
发明人： Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： An innovative routing method for an integrated circuit design layout. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
摘要翻译：一种用于集成电路设计布局的创新布线方法。布局可以包括设计网表和库单元格。多级全局路由可以为每个网络生成拓扑线。可以执行设计上面向图形的基于图形的详细路由。可以执行详细路由后的路由优化，以进一步提高路由质量。一些方法可以是单线程的全部或部分时间，和/或多线程的一些或所有的时间。

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